WO2001048619A3 - Distributed memory control and bandwidth optimization - Google Patents

Distributed memory control and bandwidth optimization Download PDF

Info

Publication number
WO2001048619A3
WO2001048619A3 PCT/US2000/042663 US0042663W WO0148619A3 WO 2001048619 A3 WO2001048619 A3 WO 2001048619A3 US 0042663 W US0042663 W US 0042663W WO 0148619 A3 WO0148619 A3 WO 0148619A3
Authority
WO
WIPO (PCT)
Prior art keywords
memory
memory control
distributed memory
bandwidth optimization
control logic
Prior art date
Application number
PCT/US2000/042663
Other languages
French (fr)
Other versions
WO2001048619A2 (en
Inventor
Gilbert Wolrich
Debra Bernstein
Matthew J Adiletta
William Wheeler
Original Assignee
Intel Corp
Gilbert Wolrich
Debra Bernstein
Matthew J Adiletta
William Wheeler
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Gilbert Wolrich, Debra Bernstein, Matthew J Adiletta, William Wheeler filed Critical Intel Corp
Priority to DE60044209T priority Critical patent/DE60044209D1/en
Priority to AU57880/01A priority patent/AU5788001A/en
Priority to AT00993654T priority patent/ATE464604T1/en
Priority to EP00993654A priority patent/EP1282862B1/en
Publication of WO2001048619A2 publication Critical patent/WO2001048619A2/en
Publication of WO2001048619A3 publication Critical patent/WO2001048619A3/en
Priority to HK03103312.2A priority patent/HK1051241A1/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing

Abstract

A controller for a random access memory has control logic, including an arbiter that detects a status of outstanding memory references. The controller selects a memory reference from one of a plurality queues of memory references. The control logic is responsive to a memory reference chaining bit that when set allows for special handling of contiguous memory references.
PCT/US2000/042663 1999-12-28 2000-12-06 Distributed memory control and bandwidth optimization WO2001048619A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
DE60044209T DE60044209D1 (en) 1999-12-28 2000-12-06 DISTRIBUTED MEMORY CONTROL AND BANDWIDTH OPTIMIZATION
AU57880/01A AU5788001A (en) 1999-12-28 2000-12-06 Distributed memory control and bandwidth optimization
AT00993654T ATE464604T1 (en) 1999-12-28 2000-12-06 DISTRIBUTED STORAGE CONTROL AND BANDWIDTH OPTIMIZATION
EP00993654A EP1282862B1 (en) 1999-12-28 2000-12-06 Distributed memory control and bandwidth optimization
HK03103312.2A HK1051241A1 (en) 1999-12-28 2003-05-13 Distributed memory control and bandwidth optimization

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/473,112 1999-12-28
US09/473,112 US6560667B1 (en) 1999-12-28 1999-12-28 Handling contiguous memory references in a multi-queue system

Publications (2)

Publication Number Publication Date
WO2001048619A2 WO2001048619A2 (en) 2001-07-05
WO2001048619A3 true WO2001048619A3 (en) 2002-11-14

Family

ID=23878258

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/042663 WO2001048619A2 (en) 1999-12-28 2000-12-06 Distributed memory control and bandwidth optimization

Country Status (9)

Country Link
US (1) US6560667B1 (en)
EP (1) EP1282862B1 (en)
CN (1) CN1238793C (en)
AT (1) ATE464604T1 (en)
AU (1) AU5788001A (en)
DE (1) DE60044209D1 (en)
HK (1) HK1051241A1 (en)
TW (1) TWI229259B (en)
WO (1) WO2001048619A2 (en)

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US6868476B2 (en) * 2001-08-27 2005-03-15 Intel Corporation Software controlled content addressable memory in a general purpose execution datapath
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US7853778B2 (en) 2001-12-20 2010-12-14 Intel Corporation Load/move and duplicate instructions for a processor
US7895239B2 (en) 2002-01-04 2011-02-22 Intel Corporation Queue arrays in network devices
US6934951B2 (en) * 2002-01-17 2005-08-23 Intel Corporation Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section
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US20050204111A1 (en) * 2004-03-10 2005-09-15 Rohit Natarajan Command scheduling for dual-data-rate two (DDR2) memory devices
US7418540B2 (en) * 2004-04-28 2008-08-26 Intel Corporation Memory controller with command queue look-ahead
US7162567B2 (en) * 2004-05-14 2007-01-09 Micron Technology, Inc. Memory hub and method for memory sequencing
US7277990B2 (en) 2004-09-30 2007-10-02 Sanjeev Jain Method and apparatus providing efficient queue descriptor memory access
US20060067348A1 (en) * 2004-09-30 2006-03-30 Sanjeev Jain System and method for efficient memory access of queue control data structures
US20060129764A1 (en) * 2004-12-09 2006-06-15 International Business Machines Corporation Methods and apparatus for storing a command
US7555630B2 (en) * 2004-12-21 2009-06-30 Intel Corporation Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit
US7418543B2 (en) 2004-12-21 2008-08-26 Intel Corporation Processor having content addressable memory with command ordering
US7467256B2 (en) * 2004-12-28 2008-12-16 Intel Corporation Processor having content addressable memory for block-based queue structures
US20060140203A1 (en) * 2004-12-28 2006-06-29 Sanjeev Jain System and method for packet queuing
US20060236011A1 (en) * 2005-04-15 2006-10-19 Charles Narad Ring management
CN100346285C (en) * 2006-01-06 2007-10-31 华为技术有限公司 Processor chip, storage control system and method
US20070245074A1 (en) * 2006-03-30 2007-10-18 Rosenbluth Mark B Ring with on-chip buffer for efficient message passing
US7926013B2 (en) * 2007-12-31 2011-04-12 Intel Corporation Validating continuous signal phase matching in high-speed nets routed as differential pairs
CN101625625B (en) * 2008-07-11 2011-11-30 鸿富锦精密工业（深圳）有限公司 Signal relay device and method for accessing external memory using same
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Also Published As

Publication number Publication date
CN1437730A (en) 2003-08-20
AU5788001A (en) 2001-07-09
CN1238793C (en) 2006-01-25
TWI229259B (en) 2005-03-11
US6560667B1 (en) 2003-05-06
ATE464604T1 (en) 2010-04-15
HK1051241A1 (en) 2003-07-25
WO2001048619A2 (en) 2001-07-05
DE60044209D1 (en) 2010-05-27
EP1282862A2 (en) 2003-02-12
EP1282862B1 (en) 2010-04-14

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