WO2001048606A3 - Allocation of data to threads in multi-threaded network processor - Google Patents

Allocation of data to threads in multi-threaded network processor Download PDF

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Publication number
WO2001048606A3
WO2001048606A3 PCT/US2000/042716 US0042716W WO0148606A3 WO 2001048606 A3 WO2001048606 A3 WO 2001048606A3 US 0042716 W US0042716 W US 0042716W WO 0148606 A3 WO0148606 A3 WO 0148606A3
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WO
WIPO (PCT)
Prior art keywords
memory
references
processor
threads
allocation
Prior art date
Application number
PCT/US2000/042716
Other languages
French (fr)
Other versions
WO2001048606A2 (en
Inventor
Gilbert Wolrich
Donald Hooper
Debra Bernstein
Matthew J Adiletta
William Wheeler
Original Assignee
Intel Corp
Gilbert Wolrich
Donald Hooper
Debra Bernstein
Matthew J Adiletta
William Wheeler
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp, Gilbert Wolrich, Donald Hooper, Debra Bernstein, Matthew J Adiletta, William Wheeler filed Critical Intel Corp
Priority to EP00992412A priority Critical patent/EP1242883B1/en
Priority to DE60030767T priority patent/DE60030767T2/en
Priority to AU43116/01A priority patent/AU4311601A/en
Publication of WO2001048606A2 publication Critical patent/WO2001048606A2/en
Publication of WO2001048606A3 publication Critical patent/WO2001048606A3/en
Priority to HK02107607A priority patent/HK1046050A1/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming

Abstract

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple program threads. The processor also includes a memory control system that has a first memory controller that sorts memory references based on whether the memory references are directed to an even bank or an odd bank of memory and a second memory controller that optimizes memory references based upon whether the memory references are read references or write references. A program thread communication scheme for packet processing is also described.
PCT/US2000/042716 1999-12-28 2000-12-08 Allocation of data to threads in multi-threaded network processor WO2001048606A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP00992412A EP1242883B1 (en) 1999-12-28 2000-12-08 Allocation of data to threads in multi-threaded network processor
DE60030767T DE60030767T2 (en) 1999-12-28 2000-12-08 DATA ALLOCATION TO THREADS IN A MULTI-THREADED NETWORK PROCESSOR
AU43116/01A AU4311601A (en) 1999-12-28 2000-12-08 Thread signaling in multi-threaded network processor
HK02107607A HK1046050A1 (en) 1999-12-28 2002-10-21 Allocation of data to threads in multi-threaded network processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/473,799 US6625654B1 (en) 1999-12-28 1999-12-28 Thread signaling in multi-threaded network processor
US09/473,799 1999-12-28

Publications (2)

Publication Number Publication Date
WO2001048606A2 WO2001048606A2 (en) 2001-07-05
WO2001048606A3 true WO2001048606A3 (en) 2002-07-11

Family

ID=23881024

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/042716 WO2001048606A2 (en) 1999-12-28 2000-12-08 Allocation of data to threads in multi-threaded network processor

Country Status (10)

Country Link
US (3) US6625654B1 (en)
EP (1) EP1242883B1 (en)
CN (1) CN100351798C (en)
AT (1) ATE339724T1 (en)
AU (1) AU4311601A (en)
DE (1) DE60030767T2 (en)
HK (1) HK1046050A1 (en)
SG (1) SG145543A1 (en)
TW (1) TW544629B (en)
WO (1) WO2001048606A2 (en)

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CN1643499A (en) 2005-07-20
WO2001048606A2 (en) 2001-07-05
ATE339724T1 (en) 2006-10-15
US6625654B1 (en) 2003-09-23
EP1242883A2 (en) 2002-09-25
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US7111296B2 (en) 2006-09-19
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US20040098496A1 (en) 2004-05-20
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