WO2001046940A1 - Signal driver with ramp generator for electro-optic display device - Google Patents
Signal driver with ramp generator for electro-optic display device Download PDFInfo
- Publication number
- WO2001046940A1 WO2001046940A1 PCT/EP2000/011542 EP0011542W WO0146940A1 WO 2001046940 A1 WO2001046940 A1 WO 2001046940A1 EP 0011542 W EP0011542 W EP 0011542W WO 0146940 A1 WO0146940 A1 WO 0146940A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- column
- bnghtness
- digital
- pixels
- level
- Prior art date
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Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2011—Display of intermediate tones by amplitude modulation
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0259—Details of the generation of driving signals with use of an analog or digital ramp generator in the column driver or in the pixel circuit
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals
- G09G3/2022—Display of intermediate tones by time modulation using two or more time intervals using sub-frames
- G09G3/2025—Display of intermediate tones by time modulation using two or more time intervals using sub-frames the sub-frames having all the same time duration
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2007—Display of intermediate tones
- G09G3/2044—Display of intermediate tones using dithering
- G09G3/2051—Display of intermediate tones using dithering with use of a spatial dither pattern
Definitions
- the invention relates to color display systems which employ one or more electro-optic display devices
- a display device serves as a light modulator, either in the reflective or transmissive mode, to control the grey level of projected light at each pixel point.
- the invention relates to such a color display system having digital- to-analog (DAC) controlled ramp generator circuitry to convert incoming digital display signals to analog signals, and circuitry to address the individual pixels of the display device with such analog signals.
- DAC digital- to-analog
- Color display systems are known in which light bars of different colors are sequentially scrolled across a single electro-optic light modulator panel to produce a color display. See, for example, commonly assigned U.S. Patent No. 5,532,763, incorporated herein by reference.
- These display systems are particularly suitable for displaying color information m the form of continuously updated image information signals arranged in successive frames, such as color video information, in which each frame is composed of component color sub-frames, e.g., red, green and blue sub-frames.
- a plurality of column pixel d ⁇ ver circuits receive a common ramp signal which is repeatedly generated, dunng a plurality of cycles, by the output buffer of a digital-to-analog converter (DAC) controlled ramp generator.
- DAC digital-to-analog converter
- Each column dnver is coupled to all the pixels in a column of the electro-optic display device.
- the column dnver applies a prescnbed voltage, corresponding to a desired pixel bnghtness level, to a pixel in a particular row in the respective column.
- the pixels in a column are selected by a row control circuit which selects successive pixel rows dunng successive ramp cycles
- the DAC controlled ramp generator becomes a performance "bottleneck" at higher frame rates (greater than 120 frames/second) which are desirable to reduce color artifacts and flicker
- the finite conversion time (cycle time) of the DAC poses a limitation on the maximum speed of operation
- An increase in the frame rate is achieved by (1) by reducing the grey scale resolution, thus reducing the number of times that the DAC must convert a digital number to an analog voltage dunng each ramp cycle, and restonng the onginal resolution using
- temporary dithenng i.e., interpolation between the bnghtness levels of pixels in successive frames — and/or (2) by providing a multi-phase clock and multiplexer which enables a selection from among several analog levels dunng each clock cycle (DAC conversion).
- the present invention thus affords an improvement in speed in a system for applying vanous levels of voltage to the individual pixels in an electro-optic display device having a matnx of pixels arranged vertically in columns and honzontally in rows.
- the average bnghtness level of each pixel is caused to approximate the desired bnghtness level although the numbers stored in the column register for each pixel may not represent a value that is equal to the desired bnghtness level
- the end result is what may be called "temporal dithenng"; that is, the interpolation between the bnghtness levels of each pixel in successive frames
- the input circuit for the column registers may be constructec so as to separately supply digital numbers to the odd column registers and to the even colurrr registers and to phase shift the control signals for the two sets of column registers In this way, the visibility of the temporal artifacts can be reduced
- the column control circuit may be constructed to provide "spacial dithenng"; that is, to alternate the bnghtness levels of two pixels in adjacent columns of the given row or two pixels in adjacent rows of a given column
- "spacial dithenng” that is, to alternate the bnghtness levels of two pixels in adjacent columns of the given row or two pixels in adjacent rows of a given column
- the human eye can interpolate between these two adjacent pixels so that the brightness appears to be intermediate between the brightness of each pixel alone.
- Fig. 1 is a block diagram of an analog electro-optic light modulator panel, and its associated driver circuits, of the type to which the present invention relates.
- Fig. 2 is a block diagram of a portion of the system of Fig. 1 showing details of the digital-to-analog converter (DAC) ramp generator.
- DAC digital-to-analog converter
- Fig. 3 is an explanatory diagram (not to scale) illustrating the operation of the DAC ramp generator of Fig. 2.
- Fig. 4 is a time diagram illustrating the operation of the system of Fig. 1 with a full-resolution DAC.
- Fig. 5 is a time diagram illustrating the operation of the system of Fig. 1 with a half-resolution DAC in accordance with the invention.
- Fig. 6 is a time diagram showing a change of phase in the drive waveform (upper diagram) to avoid DC build up on the opto-electronic display device and showing the resulting brightness modulation for a pixel (bottom diagram).
- Fig. 7 is a table illustrating how two discrete levels, M and M+l, may be sampled to provide a four level data interpolation scheme for a pixel.
- Fig. 8 illustrates the drive waveform upon inversion (upper diagram) and the brightness waveform (lower diagram) for the four level interpolation scheme.
- Fig. 9 is a block diagram of the preferred embodiment of a column control circuit for the system of Fig. 1.
- Fig. 1 illustrates a typical arrangement for controlling and driving an electro- optic display device.
- a liquid crystal display or light modulator 10 has a matrix of pixels arranged vertically in columns and horizontally in rows. These pixels are located at the intersections of the column conductors 12 and the row conductors 14.
- the column conductors 12 provide analog voltages to the pixels in each column whereas the row conductors 14 provide a switching voltage to each associated row, permitting the column voltages to be supplied to the pixels of that row.
- Rows are successively addressed in a prescribed order by means of a row decoder 16 which activates successive ones of the row drivers 18.
- Column voltages are supplied by column driver circuits 20 which are realized as track and hold circuits. These track and hold circuits receive a ramp voltage from a digital-to-analog converter (DAC) controlled ramp generator 22.
- the DAC 22 receives successive digital numbers from a counter 24 that counts pulses produced by a clock 25. The count commences either from some minimum number or maximum number and increases or decreases steadily until it reaches, at the opposite end of the scale, a maximum or minimum number, respectively.
- the DAC thus produces an increasing or decreasing ramp signal, in repetitive cycles, which approximates its digital input.
- the output of the counter 24 is also supplied to a number of comparators 26, one for each column. This number is then compared in each comparator to a digital number representing the desired brightness level of a pixel in the associated column. The number representing this brightness level is stored in an associated pixel register 28 during each complete cycle of the system.
- the respective comparator 26 When the count supplied by the counter 24 is equal to the digital number stored in a pixel register, the respective comparator 26 produces a pulse which is passed to the track and hold circuit 20 for that column. Upon receiving such an enable pulse, the associated column driver 20 stores a voltage equal to the instantaneous output of the ramp generator 22.
- the voltages stored in the column driver circuits are supplied to a pixel in a particular row selected by the row drivers 18.
- Fig. 2 illustrates the ramp generator 22 in greater detail.
- the counter 24 increments its output which is supplied as an address to a look up table 30.
- the LUT supplies the contents of this address, a digital number, to a DAC 32.
- this DAC converts the digital number to an analog voltage signal which is passed globally to all column drivers 20 (Fig. 1) via a ramp buffer amplifier 34.
- This buffer amplifier serves to isolate the ramp waveform from the load and other disturbances
- the low intnnsic output impedance Z, of the buffer output stage 36 is further reduced by feedback
- the operational speed of the system of Fig 1 is limited by the conversion time of the DAC 32, that is, the minimum time within which the DAC can convert a digital number to an analog voltage
- Fig 3 shows a ramp voltage 40 (lower line) which nas been generated from 10 digital numbers, each successively higher than the next Since the total time allocated to this ramp 40 is 15 ns, each digital number must be supplied and converted within a time penod of 1 5 ns If this conversion time of 1 5 ns is the minimum time required by the DAC, the ramp 40 cannot be generated at a faster rate This places an upper limitation on the frame rate of the system of Fig 1
- the look up table 30 is programmed to provide larger voltage steps to the DAC in response to successive addresses received from the counter 24 This permits the ramp penod to be reduced, as indicated by the ramp voltage 42 (upper line) in Fig 3 As may be seen, the ramp 42 is generated in 5 steps rather than 10 Even though the entire ramp is generated in only 10 ns, rather than 15 ns as in the case of the ramp 40, the DAC conversion time, between the individual steps (indicated by an "x" on each ramp 40 and 42) is longer for the ramp 42 than for the ramp 40
- Fig. 3 shows a relatively course resolution for the ramps 40 and 42 (10 steps and 5 steps, respectively), it will be understood that in practice the ramp will be generated with a resolution of 256 steps (8 bits) or even greater (up to 10 bits)
- the present invention makes it possible to increase the frame rate of the system without sacnficing display performance or increasing cost Although it would be possible to provide two DACs and to alternate their use for odd and even rows of the displa ⁇ device, such a modification would substantially increase the cost of the display
- the resolution of the DAC is reduced by dropping one (or more) input bits from the look up table 30 and restonng the resolution (grey scale) of the display by temporal dithenng, l e , interpolation through averaging by the human v ⁇ sua_ system of a vanable bnghtness produced by the DAC m successne frames
- Figs 4 ana An example of this scheme, according to the invention, is shown in Figs 4 ana
- Fig 4 shows the present, known technique whereby a high resolution waveform is created by a senes of closely spaced analog levels —e g , A, B and C— which is provided to and tracked by the column drivers of the display If the desired bnghtness of a pixel in a particular column is B, for example, the column dnver will sample (store) the analog voltage when it reaches the level B.
- Fig. 5 shows a courser ramp waveform having fewer steps, A and C, which is tracked by the column d ⁇ vers This waveform enables sto ⁇ ng of the corresponding levels A and C but not the desired voltage B
- the column d ⁇ ver circuits store the levels A and C, respectively, dunng alternate frame penods, thus creating an average analog level equivalent to B
- This scheme of temporal dithenng can be further refined by dithenng pixels in adjacent columns or rows, e.g., by alternating the phase of adjacent pixels.
- the temporal dithenng can be supplemented with spacial dithenng as is disclosed, for example, in the U.S. Patent No. 5,189,406, which patent is incorporated by reference
- the pixel of the electro-optic (liquid crystal) display device must be supplied with a purely analog voltage, it is necessary to pe ⁇ odically invert the pola ⁇ ty, advantageously from frame to frame, in order to prevent DC build up, however small. Since the temporal dithenng process is synchronous with each frame, the pixel phase is changed regularly as is illustrated in Fig. 6.
- phase of the dnve waveform (upper diagram in Fig. 6) is repeatedly changed, as shown at time T. This results in a bnghtness modulation of the respective pixel (lower diagram).
- the phase transitions can be designed to occur at a different moment fcr different pixels or groups of pixels. In this way the transitions are no longer global and, thus less likely to be noticeable Since dithenng represents modulation at the lowest bit level — i.e., bnghtness modulation in the order of 1 % in the case of 8 bit data — the visual effect of dithenng is small so that great freedom exists in the realization of this scheme
- the temporal dithenng process can be implemented, without changes to the electro-optic display itself, by modifying the data sent to the column registers of the d ⁇ spla ⁇ device and increasing the DAC step size by changing the data in its look up table 30
- N 0 N 255
- N M 4 + L, whereO M 64 andO L 3
- the new word is truncated to 6 bits by dropping the less significant part
- This four level data interpolation scneme is illustrated m the table of Fig 7 and in the time diagrams of Fig. 8.
- interpolation is achieved by sampling two discrete levels, M and M+l, in proportion to the value of the two lower bits
- the table of Fig 7 shows the sampled values of M_new for each of the four frames
- Fig. 8 illustrates the dnve waveform (upper time diagram) after inversion ana the bnghtness waveform (lower diagram) for this four level data interpolation scheme
- Fig 9 shows a preferred embodiment of a device for implementing the temporal dithenng scheme.
- the look up table 30 has been programmed to provide the DAC 32 with larger steps between successive conversion cycles.
- the less significant bit data (2 bits) are decoded in a decoder 50, providing output signals at one of four output terminals (0, 1. 2 and 3)
- This decoded LSB data is added to the MSB data under control of global control signals A, B and C, which are indicated in the legends at the bottom of the diagram.
- Control signals for the odd column registers 281 and the even column registers 280 are phase shifted with respect to each other to reduce the visibility of temporal artifacts. As shown in the upper part of the diagram, the output of the adder 52 is passed to the odd column registers 281. Identical hardware is provided, as shown in dashed lines in the lower part of the diagram, to supply data to the even column registers 280.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020017010511A KR20010111264A (en) | 1999-12-21 | 2000-11-20 | Signal driver with ramp generator for electro-optic display device |
JP2001547381A JP2003518267A (en) | 1999-12-21 | 2000-11-20 | Signal driver with lamp generator for electro-optical display devices |
EP00979604A EP1159730A1 (en) | 1999-12-21 | 2000-11-20 | Signal driver with ramp generator for electro-optic display device |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/469,449 | 1999-12-21 | ||
US09/469,449 US6462728B1 (en) | 1999-12-21 | 1999-12-21 | Apparatus having a DAC-controlled ramp generator for applying voltages to individual pixels in a color electro-optic display device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001046940A1 true WO2001046940A1 (en) | 2001-06-28 |
Family
ID=23863846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2000/011542 WO2001046940A1 (en) | 1999-12-21 | 2000-11-20 | Signal driver with ramp generator for electro-optic display device |
Country Status (6)
Country | Link |
---|---|
US (1) | US6462728B1 (en) |
EP (1) | EP1159730A1 (en) |
JP (1) | JP2003518267A (en) |
KR (1) | KR20010111264A (en) |
TW (1) | TW503386B (en) |
WO (1) | WO2001046940A1 (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003030135A2 (en) * | 2001-09-28 | 2003-04-10 | Koninklijke Philips Electronics N.V. | Liquid crystal displays with reduced flicker |
WO2003105118A1 (en) * | 2002-06-10 | 2003-12-18 | Koninklijke Philips Electronics N.V. | Load adaptive column driver |
CN100421147C (en) * | 2002-05-09 | 2008-09-24 | 三星电子株式会社 | Grey scale voltage generator and generating method, and corresponding liquid crystal display device therefor |
CN100423072C (en) * | 2001-11-22 | 2008-10-01 | 索尼株式会社 | Display drive method and display apparatus |
GB2477384A (en) * | 2011-01-04 | 2011-08-03 | Prysm Inc | Fine brightness control in panels or screens with pixels |
US11386830B2 (en) | 2017-09-19 | 2022-07-12 | Sony Semiconductor Solutions Corporation | Display apparatus and driving method of display apparatus |
Families Citing this family (19)
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JP4637315B2 (en) * | 1999-02-24 | 2011-02-23 | 株式会社半導体エネルギー研究所 | Display device |
US7193594B1 (en) * | 1999-03-18 | 2007-03-20 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
US7145536B1 (en) | 1999-03-26 | 2006-12-05 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
US6952194B1 (en) | 1999-03-31 | 2005-10-04 | Semiconductor Energy Laboratory Co., Ltd. | Liquid crystal display device |
US6753854B1 (en) | 1999-04-28 | 2004-06-22 | Semiconductor Energy Laboratory Co., Ltd. | Display device |
US7301520B2 (en) * | 2000-02-22 | 2007-11-27 | Semiconductor Energy Laboratory Co., Ltd. | Image display device and driver circuit therefor |
JP4545386B2 (en) * | 2003-04-03 | 2010-09-15 | シャープ株式会社 | Data holding display device and driving method thereof |
JP4114655B2 (en) * | 2003-11-12 | 2008-07-09 | セイコーエプソン株式会社 | Brightness unevenness correction method, brightness unevenness correction circuit, electro-optical device, and electronic apparatus |
KR100541975B1 (en) * | 2003-12-24 | 2006-01-10 | 한국전자통신연구원 | Source Driving Circuit for Active Matrix Display |
JP2005208407A (en) * | 2004-01-23 | 2005-08-04 | Ricoh Co Ltd | Image output device and image display device |
US7098801B1 (en) | 2005-06-28 | 2006-08-29 | Seagate Technology Llc | Using bitmasks to provide visual indication of operational activity |
KR100812644B1 (en) * | 2006-02-22 | 2008-03-13 | 삼성전기주식회사 | Display apparatus comprising spatial optical modulator and spatial optical modulator compensating method |
GB0622900D0 (en) * | 2006-11-16 | 2006-12-27 | Liquavista Bv | Display of electro-optic displays |
WO2008062578A1 (en) * | 2006-11-24 | 2008-05-29 | Sharp Kabushiki Kaisha | Image display apparatus |
CN201081774Y (en) * | 2006-12-21 | 2008-07-02 | 比亚迪股份有限公司 | Radial circuit for driving LCD |
FR2930993B1 (en) * | 2008-05-07 | 2010-04-23 | Commissariat Energie Atomique | SCANNING DEVICE WITH A PROPAGATION LINE |
US8659701B2 (en) * | 2011-12-19 | 2014-02-25 | Sony Corporation | Usage of dither on interpolated frames |
CN114387909B (en) * | 2022-02-21 | 2023-11-24 | 北京京东方显示技术有限公司 | Source driving device, control method thereof and display system |
CN117037635A (en) * | 2023-10-08 | 2023-11-10 | 长春希达电子技术有限公司 | Arrangement structure of light emitting components and display control method |
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US4766430A (en) | 1986-12-19 | 1988-08-23 | General Electric Company | Display device drive circuit |
-
1999
- 1999-12-21 US US09/469,449 patent/US6462728B1/en not_active Expired - Fee Related
-
2000
- 2000-11-20 WO PCT/EP2000/011542 patent/WO2001046940A1/en not_active Application Discontinuation
- 2000-11-20 EP EP00979604A patent/EP1159730A1/en not_active Withdrawn
- 2000-11-20 KR KR1020017010511A patent/KR20010111264A/en not_active Application Discontinuation
- 2000-11-20 JP JP2001547381A patent/JP2003518267A/en active Pending
-
2001
- 2001-03-07 TW TW090105230A patent/TW503386B/en not_active IP Right Cessation
Patent Citations (2)
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US5712651A (en) * | 1994-07-22 | 1998-01-27 | Kabushiki Kaisha Toshiba | Apparatus for performing a full-color emulation on the TFT display device |
US5828357A (en) * | 1996-03-27 | 1998-10-27 | Sharp Kabushiki Kaisha | Display panel driving method and display apparatus |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2003030135A2 (en) * | 2001-09-28 | 2003-04-10 | Koninklijke Philips Electronics N.V. | Liquid crystal displays with reduced flicker |
WO2003030135A3 (en) * | 2001-09-28 | 2003-10-09 | Koninkl Philips Electronics Nv | Liquid crystal displays with reduced flicker |
CN100423072C (en) * | 2001-11-22 | 2008-10-01 | 索尼株式会社 | Display drive method and display apparatus |
CN100421147C (en) * | 2002-05-09 | 2008-09-24 | 三星电子株式会社 | Grey scale voltage generator and generating method, and corresponding liquid crystal display device therefor |
WO2003105118A1 (en) * | 2002-06-10 | 2003-12-18 | Koninklijke Philips Electronics N.V. | Load adaptive column driver |
GB2477384A (en) * | 2011-01-04 | 2011-08-03 | Prysm Inc | Fine brightness control in panels or screens with pixels |
GB2477384B (en) * | 2011-01-04 | 2011-12-21 | Prysm Inc | Fine brightness control in panels or screens with pixels |
US8379063B2 (en) | 2011-01-04 | 2013-02-19 | Prysm, Inc. | Fine brightness control in panels or screens with pixels |
US11386830B2 (en) | 2017-09-19 | 2022-07-12 | Sony Semiconductor Solutions Corporation | Display apparatus and driving method of display apparatus |
Also Published As
Publication number | Publication date |
---|---|
US6462728B1 (en) | 2002-10-08 |
TW503386B (en) | 2002-09-21 |
EP1159730A1 (en) | 2001-12-05 |
JP2003518267A (en) | 2003-06-03 |
KR20010111264A (en) | 2001-12-17 |
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