WO2001046806A1 - Firmware mechanism for correcting soft errors - Google Patents
Firmware mechanism for correcting soft errors Download PDFInfo
- Publication number
- WO2001046806A1 WO2001046806A1 PCT/US2000/041079 US0041079W WO0146806A1 WO 2001046806 A1 WO2001046806 A1 WO 2001046806A1 US 0041079 W US0041079 W US 0041079W WO 0146806 A1 WO0146806 A1 WO 0146806A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- processor
- execution
- state data
- mode
- data
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1629—Error detection by comparing the output of redundant processing systems
- G06F11/165—Error detection by comparing the output of redundant processing systems with continued operation after detection of the error
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1658—Data re-synchronization of a redundant component, or initial sync of replacement, additional or spare unit
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1675—Temporal synchronisation or re-synchronisation of redundant processing components
- G06F11/1679—Temporal synchronisation or re-synchronisation of redundant processing components at clock signal level
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
- G06F2201/845—Systems in which the redundancy can be transformed in increased performance
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB0215171A GB2373900B (en) | 1999-12-21 | 2000-10-04 | Firmware mechanism for correcting soft errors |
AU16318/01A AU1631801A (en) | 1999-12-21 | 2000-10-04 | Firmware mechanism for correcting soft errors |
DE10085324T DE10085324T1 (en) | 1999-12-21 | 2000-10-04 | Firmware mechanism for correcting soft errors |
HK02108125.9A HK1046573B (en) | 1999-12-21 | 2002-11-08 | Firmware mechanism for correcting soft errors |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/469,963 | 1999-12-21 | ||
US09/469,963 US6625749B1 (en) | 1999-12-21 | 1999-12-21 | Firmware mechanism for correcting soft errors |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001046806A1 true WO2001046806A1 (en) | 2001-06-28 |
Family
ID=23865722
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2000/041079 WO2001046806A1 (en) | 1999-12-21 | 2000-10-04 | Firmware mechanism for correcting soft errors |
Country Status (8)
Country | Link |
---|---|
US (2) | US6625749B1 (en) |
CN (2) | CN100489801C (en) |
AU (1) | AU1631801A (en) |
DE (1) | DE10085324T1 (en) |
GB (1) | GB2373900B (en) |
HK (1) | HK1046573B (en) |
TW (1) | TWI247986B (en) |
WO (1) | WO2001046806A1 (en) |
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Also Published As
Publication number | Publication date |
---|---|
GB2373900B (en) | 2004-12-29 |
DE10085324T1 (en) | 2002-12-05 |
CN1434941A (en) | 2003-08-06 |
US6625749B1 (en) | 2003-09-23 |
US20040019771A1 (en) | 2004-01-29 |
GB0215171D0 (en) | 2002-08-07 |
GB2373900A (en) | 2002-10-02 |
CN101539875B (en) | 2012-04-11 |
TWI247986B (en) | 2006-01-21 |
HK1046573A1 (en) | 2003-01-17 |
HK1046573B (en) | 2005-05-06 |
CN100489801C (en) | 2009-05-20 |
CN101539875A (en) | 2009-09-23 |
US7134047B2 (en) | 2006-11-07 |
AU1631801A (en) | 2001-07-03 |
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