WO2001043193B1 - Dual-die integrated circuit package - Google Patents

Dual-die integrated circuit package

Info

Publication number
WO2001043193B1
WO2001043193B1 PCT/US2000/041466 US0041466W WO0143193B1 WO 2001043193 B1 WO2001043193 B1 WO 2001043193B1 US 0041466 W US0041466 W US 0041466W WO 0143193 B1 WO0143193 B1 WO 0143193B1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
integrated circuit
circuit package
die
chips
Prior art date
Application number
PCT/US2000/041466
Other languages
French (fr)
Other versions
WO2001043193A3 (en
WO2001043193A2 (en
Inventor
Julius A Kovats
Ken M Lam
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Priority to CA002392975A priority Critical patent/CA2392975A1/en
Priority to KR1020027007245A priority patent/KR20020055603A/en
Priority to JP2001543781A priority patent/JP2003516637A/en
Priority to EP00986833A priority patent/EP1238430A2/en
Publication of WO2001043193A2 publication Critical patent/WO2001043193A2/en
Publication of WO2001043193A3 publication Critical patent/WO2001043193A3/en
Publication of WO2001043193B1 publication Critical patent/WO2001043193B1/en
Priority to NO20022736A priority patent/NO20022736L/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Landscapes

  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Credit Cards Or The Like (AREA)

Abstract

A dual-die integrated circuit package (10) having two integrated circuit chips (14, 16) 'flip chip' attached to each other and with one of the chips (14) being aligned at a specified angle in relation to the other chip (16) to allow access to bonding pads on the surface of each chip for wirebonding connection into the chip package. In a first embodiment, the two chips are rectangular in shape and are aligned at an angle of 90 degrees with respect to each other, thus allowing the end portions of the bottom chip to be accessible for connection into the chip package. Other embodiments maintain the chips at angles of less than 90 degrees, such that corner portions of each chip are accessible for connection into the chip package. The invention allows two identically constructed chips to be used for doubling or even greater multiplication of the functionality or memory of the IC package, while still using the same package footprint as for a single chip. Also, being able to use two chips that are identically constructed from a wafer fabrication standpoint provides the advantage of requiring only one IC design process.

Claims

-14 -AMENDED CLAIMS[received by the International Bureau on 9 November 2001 (09.1 1.01); original claims 1, 2 and 14 amended; original claim 10 cancelled; new claims 16-19 added; remaining claims unchanged (4 pages)]
1. A dual-die integrated circuit package comprising: a flat die-attachment surface having a plurality of external electrical contacts for connecting the package to external circuits, a first IC chip having a first surface and a second surface, and having a plurality of bonding pads on the first surface, the second surface being mounted on the die-attachment surface, a second IC chip having a first surface and a second surface wherein said second IC chip is larger than said first IC chip and is mounted on top of said first IC chip, and said second chip being mechanically and electrically connected by its second surface to the first surface of the first IC chip, wherein the second IC chip is aligned at a specified angle in skewed relation to the first IC chip in a covering relation, said specified angle being greater than zero degrees, with bonding pads on the first surface of the first IC chip remaining uncovered and electrically connected to the external electrical contacts of the die-attachment surface, and an encapsulant material enclosing the first and second IC chip and covering a portion of the die- attachment surface such that the plurality of electrical contacts remain at least partially uncovered.
2. The integrated circuit package of claim 1, wherein the first and second IC chips are of the same size.
3. The integrated circuit package of claim 1, wherein the first and second IC chips have a rectangular shape.
4. The integrated circuit package of claim 3, wherein the specified angle of alignment is 90 degrees. -15 -
5. The integrated circuit package of claim 1, wherein the specified angle of alignment is less than 90 degrees.
6. The integrated circuit package of claim 1, wherein the second surface of the second IC chip and the first surface of the first IC chip include a series of solder bumps to enable electrical and mechanical connection between the second IC chip and the first IC chip.
7. The integrated circuit package of claim 1, wherein the die-attachment surface is a part of a leadframe, with a plurality of leads being disposed on a perimeter of the die-attachment surface.
8. The integrated circuit package of claim 7, wherein the plurality of leads are electrically connected to the first and second IC chips by wirebond connection between the leads and the plurality of bonding pads on the first surface of the first IC chip.
9. The integrated circuit package of claim 1, wherein the first IC chip is mounted to the die-attachment surface by epoxy.
10. (cancelled)
11. The integrated circuit package of claim 1, wherein the die-attachment surface is a part of a ball grid array type structure and includes a series of solder bumps on a bottom surface of the chip package.
-16- 12. The integrated circuit package of claim 6, wherein the series of solder bumps are arranged in a diagonal pattern .
13. The integrated circuit package of claim 6, wherein the series of solder bumps are arranged in a "X-shaped" pattern.
14. A method of forming a dual-die integrated circuit package comprising: arranging a plurality of solder bumps on a first surface of a first IC chip and on a first surface of a second IC chip, the first and second IC chips having a plurality of bonding pads arranged thereon wherein said second IC chip is larger than said first IC chip, arranging a series of routing traces on the first surfaces of the first and second IC chips, the routing traces interconnecting the solder bumps and the bonding pads, adding a passivation layer over the first surfaces of each of the first and second chips, the solder bumps and the bonding pads remaining exposed through the passivation layer, aligning the second chip at a specified angle in skewed relation to the first chip, said angle being greater than zero degrees, such that the bonding pads on the first surface of the first IC chip remain at least partially uncovered, connecting the second chip to the first chip through the solder reflow attachment of the solder bumps of each of the chips, attaching the first chip to a flat die- attachment surface being in mechanical and electrical communication with a plurality of electrical contacts, and covering the first and second chips and an inner part of the die-attachment surface with an encapsulant material. -17-
15. The method of forming a dual-die integrated circuit package, as in claim 14, wherein the step of connecting the second chip to the first chip is carried out by using an anisotropic epoxy.
16. The integrated circuit package of claim 1 wherein the specified angle of alignment is greater than 45 degrees and less than 90 degrees.
17. The integrated circuit package of claim 1 wherein the specified angle of alignment is less than 45 degrees.
18. The method of forming a dual-die integrated circuit package, as in claim 14, wherein the specified angle of alignment is greater than 45 degrees and less than ninety degrees.
19. The method of forming a dual-die integrated circuit package, as in claim 14, wherein the specified angle of alignment is less than 45 degrees.
-18 -
STATEMENT UNDERARTICLE 19 (1)
Applicant is amending claims 1 and 14 to incorporate the limitations of dependent claim 10, which has been cancelled. None of the cited prior art references discloses a dual-die integrated circuit package or a method of forming a dual-die integrated circuit package wherein a second IC chip is larger than a first IC chip and is mounted on top of said first IC chip such that bonding pads on a first surface of the first IC chip remain uncovered. This is advantageous, for example, to a manufacturer who controls the design of the smaller IC chip but purchases the larger IC chip from a second source. Additionally, dependent claims 16-19 were added to emphasize that the IC chips can be skewed in various angles of alignment depending upon the shape and size of the IC chips.
Claim 14 has also been amended to reflect correct antecedent basis.
PCT/US2000/041466 1999-12-09 2000-10-23 Dual-die integrated circuit package WO2001043193A2 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CA002392975A CA2392975A1 (en) 1999-12-09 2000-10-23 Dual-die integrated circuit package
KR1020027007245A KR20020055603A (en) 1999-12-09 2000-10-23 Dual-die integrated circuit package
JP2001543781A JP2003516637A (en) 1999-12-09 2000-10-23 Dual die integrated circuit package
EP00986833A EP1238430A2 (en) 1999-12-09 2000-10-23 Dual-die integrated circuit package
NO20022736A NO20022736L (en) 1999-12-09 2002-06-07 Circuit enclosure with an integrated double chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/458,264 US6376914B2 (en) 1999-12-09 1999-12-09 Dual-die integrated circuit package
US09/458,264 1999-12-09

Publications (3)

Publication Number Publication Date
WO2001043193A2 WO2001043193A2 (en) 2001-06-14
WO2001043193A3 WO2001043193A3 (en) 2002-03-28
WO2001043193B1 true WO2001043193B1 (en) 2002-05-30

Family

ID=23820062

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/041466 WO2001043193A2 (en) 1999-12-09 2000-10-23 Dual-die integrated circuit package

Country Status (10)

Country Link
US (1) US6376914B2 (en)
EP (1) EP1238430A2 (en)
JP (1) JP2003516637A (en)
KR (1) KR20020055603A (en)
CN (1) CN1408125A (en)
CA (1) CA2392975A1 (en)
MY (1) MY135947A (en)
NO (1) NO20022736L (en)
TW (1) TW472327B (en)
WO (1) WO2001043193A2 (en)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3847997B2 (en) * 1999-01-22 2006-11-22 東芝マイクロエレクトロニクス株式会社 Semiconductor device and double-sided MCP chip
US6621155B1 (en) 1999-12-23 2003-09-16 Rambus Inc. Integrated circuit device having stacked dies and impedance balanced transmission lines
JP2001196529A (en) * 2000-01-17 2001-07-19 Mitsubishi Electric Corp Semiconductor device and wiring method therefor
JP4637380B2 (en) * 2001-02-08 2011-02-23 ルネサスエレクトロニクス株式会社 Semiconductor device
TW544901B (en) * 2001-06-13 2003-08-01 Matsushita Electric Ind Co Ltd Semiconductor device and manufacture thereof
US6900528B2 (en) * 2001-06-21 2005-05-31 Micron Technology, Inc. Stacked mass storage flash memory package
JP2003007971A (en) * 2001-06-25 2003-01-10 Toshiba Corp Semiconductor device
KR100415279B1 (en) * 2001-06-26 2004-01-16 삼성전자주식회사 Chip stack package and manufacturing method thereof
US6979894B1 (en) 2001-09-27 2005-12-27 Marvell International Ltd. Integrated chip package having intermediate substrate
US6880145B1 (en) * 2001-12-21 2005-04-12 Cypress Semiconductor Corp. Method for determining die placement based on global routing architecture
CN100394598C (en) * 2002-07-31 2008-06-11 旺宏电子股份有限公司 Ultrathin stack components
US20040021230A1 (en) * 2002-08-05 2004-02-05 Macronix International Co., Ltd. Ultra thin stacking packaging device
US7091602B2 (en) * 2002-12-13 2006-08-15 Freescale Semiconductor, Inc. Miniature moldlocks for heatsink or flag for an overmolded plastic package
US6879028B2 (en) * 2003-02-21 2005-04-12 Freescale Semiconductor, Inc. Multi-die semiconductor package
US6815254B2 (en) * 2003-03-10 2004-11-09 Freescale Semiconductor, Inc. Semiconductor package with multiple sides having package contacts
US6856009B2 (en) * 2003-03-11 2005-02-15 Micron Technology, Inc. Techniques for packaging multiple device components
US6936929B1 (en) * 2003-03-17 2005-08-30 National Semiconductor Corporation Multichip packages with exposed dice
KR100541393B1 (en) * 2003-04-26 2006-01-10 삼성전자주식회사 Multi-chip BGA package
US7098541B2 (en) * 2003-05-19 2006-08-29 Hewlett-Packard Development Company, L.P. Interconnect method for directly connected stacked integrated circuits
JP4160447B2 (en) * 2003-05-28 2008-10-01 シャープ株式会社 Electronic component and module, module assembling method, identification method and environment setting method
US7073702B2 (en) 2003-10-17 2006-07-11 International Business Machines Corporation Self-locking wire bond structure and method of making the same
US20050133241A1 (en) * 2003-12-18 2005-06-23 Taiwan Semiconductor Manufacturing Co., Ltd. Chip orientation and attachment method
US7078792B2 (en) * 2004-04-30 2006-07-18 Atmel Corporation Universal interconnect die
US20050242425A1 (en) * 2004-04-30 2005-11-03 Leal George R Semiconductor device with a protected active die region and method therefor
US7863720B2 (en) * 2004-05-24 2011-01-04 Honeywell International Inc. Method and system for stacking integrated circuits
US7700409B2 (en) * 2004-05-24 2010-04-20 Honeywell International Inc. Method and system for stacking integrated circuits
TWI285422B (en) * 2005-09-15 2007-08-11 Chipmos Technologies Inc Chip structure and stacked chip package structure
US7385282B2 (en) * 2005-10-19 2008-06-10 Chipmos Technologies Inc. Stacked-type chip package structure
US7298038B2 (en) * 2006-02-25 2007-11-20 Stats Chippac Ltd. Integrated circuit package system including die stacking
JP5313887B2 (en) * 2007-05-31 2013-10-09 三洋電機株式会社 Semiconductor module and portable device
US7872335B2 (en) * 2007-06-08 2011-01-18 Broadcom Corporation Lead frame-BGA package with enhanced thermal performance and I/O counts
TWI335055B (en) * 2007-06-29 2010-12-21 Chipmos Technologies Inc Chip-stacked package structure
US7855445B2 (en) * 2008-04-29 2010-12-21 Silicon Laboratories, Inc. Circuit device including rotated stacked die
US8315068B2 (en) 2009-11-12 2012-11-20 International Business Machines Corporation Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same
US8258619B2 (en) * 2009-11-12 2012-09-04 International Business Machines Corporation Integrated circuit die stacks with translationally compatible vias
US8310841B2 (en) 2009-11-12 2012-11-13 International Business Machines Corporation Integrated circuit die stacks having initially identical dies personalized with switches and methods of making the same
US8417974B2 (en) * 2009-11-16 2013-04-09 International Business Machines Corporation Power efficient stack of multicore microprocessors
EP2586058A4 (en) * 2010-06-25 2014-01-01 Symbolic Logic Ltd Memory device
CN101958302B (en) * 2010-09-04 2012-04-11 江苏长电科技股份有限公司 Double-side graph chip inverse single package structure and package method thereof
KR20130016466A (en) * 2011-08-08 2013-02-18 삼성전자주식회사 Semiconductor package
US20130256883A1 (en) * 2012-03-27 2013-10-03 Intel Mobile Communications GmbH Rotated semiconductor device fan-out wafer level packages and methods of manufacturing rotated semiconductor device fan-out wafer level packages
KR102111742B1 (en) * 2014-01-14 2020-05-15 삼성전자주식회사 Stacked semiconductor package
DE102015014589B4 (en) * 2015-11-12 2021-08-26 Tesat-Spacecom Gmbh & Co. Kg Spacecraft with redundant data processing system
US10128199B1 (en) 2017-07-17 2018-11-13 International Business Machines Corporation Interchip backside connection
KR102508552B1 (en) * 2018-04-30 2023-03-10 에스케이하이닉스 주식회사 Stack package including through mold vias
CN112151513A (en) 2019-06-27 2020-12-29 恩智浦美国有限公司 Power die package

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61287133A (en) 1985-06-13 1986-12-17 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
JPH04155954A (en) 1990-10-19 1992-05-28 Nec Kyushu Ltd Semiconductor device
FR2670322B1 (en) 1990-12-05 1997-07-04 Matra Espace SOLID STATE MEMORY MODULES AND MEMORY DEVICES CONTAINING SUCH MODULES
JPH05129516A (en) 1991-11-01 1993-05-25 Hitachi Ltd Semiconductor device
US5339216A (en) * 1993-03-02 1994-08-16 National Semiconductor Corporation Device and method for reducing thermal cycling in a semiconductor package
KR0149798B1 (en) * 1994-04-15 1998-10-01 모리시다 요이치 Semiconductor device and method of manufacture and lead frame
WO1996013855A1 (en) * 1994-10-27 1996-05-09 National Semiconductor Corporation A leadframe for an integrated circuit package which electrically interconnects multiple integrated circuit die
US6005778A (en) * 1995-06-15 1999-12-21 Honeywell Inc. Chip stacking and capacitor mounting arrangement including spacers
US5874781A (en) * 1995-08-16 1999-02-23 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5721452A (en) 1995-08-16 1998-02-24 Micron Technology, Inc. Angularly offset stacked die multichip device and method of manufacture
US5952725A (en) * 1996-02-20 1999-09-14 Micron Technology, Inc. Stacked semiconductor devices
US5696031A (en) * 1996-11-20 1997-12-09 Micron Technology, Inc. Device and method for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
US5760478A (en) * 1996-08-20 1998-06-02 International Business Machines Corporation Clock skew minimization system and method for integrated circuits
US6133637A (en) * 1997-01-24 2000-10-17 Rohm Co., Ltd. Semiconductor device having a plurality of semiconductor chips
US6057598A (en) * 1997-01-31 2000-05-02 Vlsi Technology, Inc. Face on face flip chip integration
JP3349058B2 (en) * 1997-03-21 2002-11-20 ローム株式会社 Structure of a semiconductor device having a plurality of IC chips
JP3545200B2 (en) * 1997-04-17 2004-07-21 シャープ株式会社 Semiconductor device
US6030885A (en) * 1997-04-18 2000-02-29 Vlsi Technology, Inc. Hexagonal semiconductor die, semiconductor substrates, and methods of forming a semiconductor die
US5923090A (en) * 1997-05-19 1999-07-13 International Business Machines Corporation Microelectronic package and fabrication thereof
US5987357A (en) * 1997-07-30 1999-11-16 Intermedics Inc. Stackable microelectronic components with self-addressing scheme
KR100265730B1 (en) * 1997-10-24 2000-09-15 윤종용 Laser scanning system
US6091138A (en) * 1998-02-27 2000-07-18 Advanced Micro Devices, Inc. Multi-chip packaging using bump technology

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KR20020055603A (en) 2002-07-09
CA2392975A1 (en) 2001-06-14
EP1238430A2 (en) 2002-09-11
US6376914B2 (en) 2002-04-23
WO2001043193A3 (en) 2002-03-28
TW472327B (en) 2002-01-11
MY135947A (en) 2008-07-31
NO20022736D0 (en) 2002-06-07
CN1408125A (en) 2003-04-02
NO20022736L (en) 2002-06-07
WO2001043193A2 (en) 2001-06-14
US20010003375A1 (en) 2001-06-14
JP2003516637A (en) 2003-05-13

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