WO2001024230A3 - Techniques for improving etching in a plasma processing chamber - Google Patents

Techniques for improving etching in a plasma processing chamber Download PDF

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Publication number
WO2001024230A3
WO2001024230A3 PCT/US2000/026454 US0026454W WO0124230A3 WO 2001024230 A3 WO2001024230 A3 WO 2001024230A3 US 0026454 W US0026454 W US 0026454W WO 0124230 A3 WO0124230 A3 WO 0124230A3
Authority
WO
WIPO (PCT)
Prior art keywords
plasma processing
techniques
processing chamber
critical dimension
improving etching
Prior art date
Application number
PCT/US2000/026454
Other languages
French (fr)
Other versions
WO2001024230A2 (en
Inventor
Thomas D Nguyen
George Mueller
Peter Mcgrath
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Priority to AU77184/00A priority Critical patent/AU7718400A/en
Priority to JP2001527323A priority patent/JP2003510834A/en
Publication of WO2001024230A2 publication Critical patent/WO2001024230A2/en
Publication of WO2001024230A3 publication Critical patent/WO2001024230A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

Abstract

Improved methods and apparatus for chemically assisted etch processing in a plasma processing system are disclosed. In accordance with one aspect of the invention, improved techniques suitable for performing an etch process in the plasma processing can be realized. The invention operates to reduce the critical dimension bias that is associated with the etch process. Lower critical dimension bias provides many benefits. One such benefit is that features with higher aspect ratio can be etched correctly. In addition, several other undesired effects, e.g., micro loading, bowing and passivation, can be curtailed using the techniques of the present invention.
PCT/US2000/026454 1999-09-27 2000-09-26 Techniques for improving etching in a plasma processing chamber WO2001024230A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU77184/00A AU7718400A (en) 1999-09-27 2000-09-26 Techniques for improving etching in a plasma processing chamber
JP2001527323A JP2003510834A (en) 1999-09-27 2000-09-26 Techniques for improving etching in plasma processing chambers.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/405,949 1999-09-27
US09/405,949 US6410451B2 (en) 1999-09-27 1999-09-27 Techniques for improving etching in a plasma processing chamber

Publications (2)

Publication Number Publication Date
WO2001024230A2 WO2001024230A2 (en) 2001-04-05
WO2001024230A3 true WO2001024230A3 (en) 2001-10-25

Family

ID=23605899

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/026454 WO2001024230A2 (en) 1999-09-27 2000-09-26 Techniques for improving etching in a plasma processing chamber

Country Status (5)

Country Link
US (1) US6410451B2 (en)
JP (1) JP2003510834A (en)
KR (1) KR100743873B1 (en)
AU (1) AU7718400A (en)
WO (1) WO2001024230A2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2429720C (en) 2000-11-29 2009-12-29 Schering Corporation Tricyclic compounds useful for the inhibition of farnesyl protein transferase
TW567554B (en) * 2001-08-08 2003-12-21 Lam Res Corp All dual damascene oxide etch process steps in one confined plasma chamber
US6846747B2 (en) 2002-04-09 2005-01-25 Unaxis Usa Inc. Method for etching vias
US7399711B2 (en) * 2002-08-13 2008-07-15 Lam Research Corporation Method for controlling a recess etch process
US6979578B2 (en) 2002-08-13 2005-12-27 Lam Research Corporation Process endpoint detection method using broadband reflectometry
US7019844B2 (en) * 2002-08-13 2006-03-28 Lam Research Corporation Method for in-situ monitoring of patterned substrate processing using reflectometry.
US6869542B2 (en) * 2003-03-12 2005-03-22 International Business Machines Corporation Hard mask integrated etch process for patterning of silicon oxide and other dielectric materials
US7256134B2 (en) * 2003-08-01 2007-08-14 Applied Materials, Inc. Selective etching of carbon-doped low-k dielectrics
US7164095B2 (en) * 2004-07-07 2007-01-16 Noritsu Koki Co., Ltd. Microwave plasma nozzle with enhanced plume stability and heating efficiency
US7806077B2 (en) 2004-07-30 2010-10-05 Amarante Technologies, Inc. Plasma nozzle array for providing uniform scalable microwave plasma generation
US20060021980A1 (en) * 2004-07-30 2006-02-02 Lee Sang H System and method for controlling a power distribution within a microwave cavity
US7271363B2 (en) * 2004-09-01 2007-09-18 Noritsu Koki Co., Ltd. Portable microwave plasma systems including a supply line for gas and microwaves
US7189939B2 (en) * 2004-09-01 2007-03-13 Noritsu Koki Co., Ltd. Portable microwave plasma discharge unit
US20060052883A1 (en) * 2004-09-08 2006-03-09 Lee Sang H System and method for optimizing data acquisition of plasma using a feedback control module
US7867403B2 (en) * 2006-06-05 2011-01-11 Jason Plumhoff Temperature control method for photolithographic substrate
US7932181B2 (en) * 2006-06-20 2011-04-26 Lam Research Corporation Edge gas injection for critical dimension uniformity improvement
US9793127B2 (en) * 2013-11-13 2017-10-17 Taiwan Semiconductor Manufacturing Company Limited Plasma generation and pulsed plasma etching

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997024750A1 (en) * 1995-12-29 1997-07-10 Trikon Technologies, Inc. Method for etching silicon dioxide using unsaturated fluorocarbons
JPH10199869A (en) * 1997-01-08 1998-07-31 Tokyo Electron Ltd Dry-etching method
WO1999016110A2 (en) * 1997-09-19 1999-04-01 Applied Materials, Inc. Plasma process for selectively etching oxide using fluoropropane or fluoropropylene

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07249586A (en) * 1993-12-22 1995-09-26 Tokyo Electron Ltd Treatment device and its manufacturing method and method for treating body to be treated
JP3223692B2 (en) * 1994-03-17 2001-10-29 株式会社日立製作所 Dry etching method
US6043164A (en) * 1996-06-10 2000-03-28 Sharp Laboratories Of America, Inc. Method for transferring a multi-level photoresist pattern
US5973799A (en) * 1997-07-30 1999-10-26 Cyberscan Technology, Inc. ID card image reader

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1997024750A1 (en) * 1995-12-29 1997-07-10 Trikon Technologies, Inc. Method for etching silicon dioxide using unsaturated fluorocarbons
JPH10199869A (en) * 1997-01-08 1998-07-31 Tokyo Electron Ltd Dry-etching method
US5972799A (en) * 1997-01-08 1999-10-26 Tokyo Electron Limited Dry etching method
WO1999016110A2 (en) * 1997-09-19 1999-04-01 Applied Materials, Inc. Plasma process for selectively etching oxide using fluoropropane or fluoropropylene

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
FEURPRIER Y, CHINZEI Y, OGATA M, KIKUCHI T, OZAWA M, ICHIKI T, HORIIKE Y: "Microloading effect in ultrafine SiO2 hole/trench etching", JOURNAL OF VACUUM SCIENCE AND TECHNOLOGY A, vol. 17, no. 4, July 1999 (1999-07-01) - August 1999 (1999-08-01), pages 1556 - 1561, XP002155551 *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 12 31 October 1998 (1998-10-31) *

Also Published As

Publication number Publication date
AU7718400A (en) 2001-04-30
US6410451B2 (en) 2002-06-25
KR100743873B1 (en) 2007-07-30
US20010044212A1 (en) 2001-11-22
WO2001024230A2 (en) 2001-04-05
JP2003510834A (en) 2003-03-18
KR20020041447A (en) 2002-06-01

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