WO2001024104A1 - High-speed on-chip windowed centroiding using photodiode-based cmos imager - Google Patents
High-speed on-chip windowed centroiding using photodiode-based cmos imager Download PDFInfo
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- WO2001024104A1 WO2001024104A1 PCT/US2000/027169 US0027169W WO0124104A1 WO 2001024104 A1 WO2001024104 A1 WO 2001024104A1 US 0027169 W US0027169 W US 0027169W WO 0124104 A1 WO0124104 A1 WO 0124104A1
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- Prior art keywords
- reset
- computation
- pixel signals
- averaging
- imager
- Prior art date
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/60—Analysis of geometric attributes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T5/00—Image enhancement or restoration
- G06T5/20—Image enhancement or restoration by the use of local operators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T7/00—Image analysis
- G06T7/60—Analysis of geometric attributes
- G06T7/66—Analysis of geometric attributes of image moments or centre of gravity
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/62—Detection or reduction of noise due to excess charges produced by the exposure, e.g. smear, blooming, ghost image, crosstalk or leakage between pixels
- H04N25/626—Reduction of noise due to residual charges remaining after image readout, e.g. to remove ghost images or afterimages
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
Definitions
- the applications may include object tracking in robotic systems, autonomous navigation, image compression, and document copyright protection.
- Other applications may include space guidance and navigation systems, and deep- space optical communication systems that require accurate and stable beam pointing for high speed data transfer.
- Off-focal-plane digital processors may yield accurate centroid values, but only at the cost of increased latency, power and size.
- On or near focal - plane centroid computation using current mode circuits, and neuro-MOS circuits have been implemented.
- neither approach may be compatibly integrated with high performance image sensors .
- a photodiode-based active pixel imager (API) sensor may be used for high quality imaging applications such as the centroid computation.
- the photodiode-based sensor provides higher quantum efficiency than a photogate-based sensor.
- noise in the photodiode-type CMOS API sensors causes high reset (kTC) noise at the sense node.
- the present disclosure describes a centroid computation system having an imager array, a switching network, computation elements, and a divider circuit.
- the imager array has columns and rows of pixels.
- the switching network is adapted to receive pixel signals from the image array.
- the plurality of computation elements operates to compute inner products for at least x and y centroids.
- the plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network.
- the divider circuit is adapted to receive the inner products and compute the x and y centroids.
- FIG. 1 shows an embodiment of the windowed- centroiding active pixel sensor (APS) system
- FIGS. 2A and 2B illustrate circuits used for inner- product computations for the X- and Y-centroid blocks, respectively;
- FIG. 3 shows an embodiment a divider circuit
- FIG. 4 shows a layout of a prototype imager of
- FIG. 5 shows a measured centroid error versus window size
- FIG. 6 shows a plot of a centroid error as a function of average signal strength
- FIG. 7 is a schematic diagram of a photodiode-type CMOS APS pixel according to an embodiment of the present disclosure
- FIG. 8 is a timing diagram of an imager running in digital still mode
- FIG. 9 shows a plot of a response non-linearity with the pixel held in reset state during idling phase
- FIG. 10 is a SPICE simulation showing the sense node potentials for different sense node signal excursions as the pixel is periodically reset;
- FIG. 11A shows a schematic of a flushed photodiode APS pixel in accordance with an embodiment
- FIG. 11B shows a schematic of an HTS photodiode APS pixel in accordance with an embodiment
- FIG. 12 shows pixel timing diagrams
- FIG. 13 is a SPICE simulation showing the sense node potentials for different sense node signal excursions as the pixel is periodically reset;
- FIG. 14 shows a plot of measured photodiode APS pixel linearity
- FIG. 15 shows a plot of measured image lag from different photodiodes .
- FIG. 16 shows a plot of a noise as a function of the pixel conversion gain.
- the present disclosure describes an on-focal plane centroid computation circuit that is compatible and integrated with CMOS imagers implemented in conventional or modified CMOS technology.
- CMOS imagers implemented in conventional or modified CMOS technology.
- APS photodiode-based CMOS active pixel sensor
- the centroid computation circuit design allows accurate X- and Y-centroid computation from a user- selectable window of interest.
- the circuit also allows window location and size to be programmable.
- the circuit may be designed to dissipate less power than the prior art designs, which may enable a real-time, miniature tracking system.
- the centroid computation circuit utilizes a switched capacitor network having only passive elements such as capacitors and switches.
- the circuit further allows column-parallel computation that enables X- and Y-centroid computations to be performed substantially simultaneously. This provides low power consumption and high accuracy computation to better than 0.05 pixel accuracy. The accuracy may be achieved under most lighting conditions, while maintaining high update rates (20-50 KHz) that make the chip attractive for use in real-time image-based control systems .
- the photodiode-based CMOS imager design provides improved steady state and dynamic response.
- both the pixel sensor and the clocking scheme are modified to allow imager operation with reset level independent of signal strength under steady state or dynamic conditions.
- the pixel is reset in "soft-reset” allowing low-reset noise and high power supply rejection ratio ("PSRR").
- PSRR power supply rejection ratio
- its steady state and dynamic response may be made to follow that obtained with "hard- reset”.
- the design provides substantially reduced image lag and high linearity even under low-light levels compared to conventional imager designs.
- the image lag was measured to be less than 1% compared to 10% in conventional imagers with soft-reset. Further, no dead zone was found, with greater than 40 dB enhancement of low-light response.
- the present imager design also provides low noise and high PSRR.
- the noise was measured to be less than half the conventional devices with hard- reset.
- the PSRR was measured to be 40 dB higher than the hard-reset without bypass capacitor.
- FIG. 1 An embodiment of the windowed-centroiding active pixel sensor (APS) system 100 is shown in FIG. 1.
- the system provides on-chip 2-D centroid computation.
- the system includes a 2-D imager array 102, a switching network 104, inner-product (IP) computation circuits 106, 108, and an analog divider 110.
- IP inner-product
- the 2-D computation is performed by computing the relevant inner-products or weighted sums for a given row. Upon completion of all row-wise inner-products, these values are processed to generate the final X and Y inner-products.
- a divider circuit 110 is then used to generate the X- 112 and Y- centroids 114.
- the X- and Y-centroids 112, 114 provided by the on- focal-plane circuits 102-110 are computed as follows:
- FIG. 2A An embodiment of a circuit 200 used for inner- product computations for the X-centroid block 106 is shown in FIG. 2A.
- FIG. 2B An embodiment of a circuit 250 used for inner-product computations for the Y-centroid block 108 is shown in FIG. 2B. Only capacitors and switches are used to perform the computation, with different sized capacitors representing different weights. The capacitors in the column-averaging banks 202, 252 are used for sampling one row of pixel values. The capacitors are linearly scaled in the X-centroid block, while they are the same in successively enabling clocks EN1, EN2, ... EN(n-l) 254.
- Averaging over the columns, and sharing the result with one of the capacitors in the row-averaging bank 208, 258 is carried out by pulsing AVC 206, 256 and the appropriated DUMP(i) 210, 260 substantially simultaneously. This allows equal but reduced attenuation for all row signals.
- the capacitors 262 in the row-averaging bank 258 are linearly scaled for the Y-centroid block 250, while the capacitors 212 are equal for the X-centroid block 200.
- a switching network having an Nx9 (N is the imager format) switching array connects 9 consecutive columns of the imager array into the computation circuit. This allows centroid computation for blocks of size 3x3 to 9x9. Thus, the computation is performed in parallel with the imager readout. This parallel computation allows for a high computation speed and substantially reduced computational overhead .
- An embodiment shown in FIG. 3 may be used as the divider circuit 110.
- the circuit includes an op-amp 300 with a plurality of transistors 302 configured to generate the X- and Y-centroids from the row-wise inner products .
- FIG. 4 shows a layout of the prototype imager 400 of 128x128 format.
- Computation circuits 402 take up only a small area (1.7 mm x 0.9 mm), irrespective of the imager format.
- the imager 400 is fabricated using HP 0.5 ⁇ m CMOS technology with a 12 ⁇ m pixel pitch.
- the imager 400 has two ports: one for centroid output and the other for imager output .
- the performance of the illustrated imager 400 is summarized in Table 1.
- the Table shows imager performance exceeding that of conventional designs.
- the use of passive components and only one op-amp (for the divider circuit) enables low power operation on the order of about 3 mW.
- image centroid may be computed separately by acquiring the raw data from the imager port .
- the computed centroid may be compared against the value obtained from the centroid port.
- Relative error in pixels
- the measurements may be repeated for different window sizes, centroid values, mean signal strengths, and from different regions of the imager.
- the result indicates that a typical centroid error of 0.02 pixel may be achieved over most of the array.
- the worst-case error was around 0.07 pixel for the smallest sized (3x3) window.
- FIG. 5 also shows the smallest and the largest centroid error measured from the array.
- the error dependence on the window size was not large, although in general, the error is found to be lower for larger sized windows.
- Update rates vary from 20 to 50 KHz for window sizes scaling from 9x9 to 3x3.
- the total noise added by all three centroid computation circuits is small compared to the imager output r.m.s. noise of 225 ⁇ V ( ⁇ 9 e " ) . This is achieved by increasing capacitor sizes, with minimum being 2 pF . Large capacitance size also helps to minimize capacitance-matching errors. Residual error in the circuit is governed by matching errors and switch feed- through. Hence, as shown in FIG. 6, the centroiding inaccuracy tends to increase for mean signals less than 100 mV. The residual error also increases for larger mean signal ( ⁇ 800 mV) , due to non-linearities and signal saturation.
- FIG. 7 shows an embodiment of a photodiode-based CMOS active pixel sensor (APS) may be used as a CMOS imager that provides image signal input for the centroiding computation.
- FIG. 7 shows an embodiment of a photodiode- based APS pixel 700.
- Signal integrated on the photodiode sense node (SENSE) 702 is calculated by measuring the difference between the voltage on the column bus (COL) 704, before and after the reset (RST) 706 is pulsed.
- Other pixels 708, 709 may be connected to the same column bus 704.
- lower kTC noise may be achieved with photodiode-type pixels by employing "soft-reset" technique.
- the soft-reset includes resetting the pixel with both drain and gate of the n-channel reset transistor 710 kept at the same potential. This results in the sense node 702 being reset using sub-threshold MOSFET current. However, the noise may be lowered at the expense of higher image lag and low-light-level non-linearity. The noise behavior is analyzed and the evidence of degraded performance under low-light levels is shown below. Further, a new pixel design that substantially reduces non-linearity and image lag without compromising noise is presented.
- the reset noise at the sense node 702 may be estimated from the time-dependence of the probability distribution function (F n ) , defined as the probability of finding n electrons on the sense node at a particular
- I e mk ⁇ , where DV is the voltage difference between V GS (or V SD ) and the threshold voltage (V ⁇ ) , KT/q is the thermal potential ( ⁇ ⁇ ) , and m is the non-ideality factor. Since
- V DS V DS >> ⁇ ⁇ , the reverse current is minimal. This makes the current flow substantially unidirectional. Then, dF
- Equation 2 Equation 2 may then be solved to provide:
- ⁇ 2 is the variance at the onset of the reset process
- An is the average amount of electrons added to the sense node.
- reset noise is determined by the shot-noise in the amount of electrons.
- the reset noise may be substantially smaller than kTC.
- the reduction in reset noise may be caused by the feedback inherent to the reset mechanism. For an exponential current flow over the barrier, instantaneous current flow may decrease sooner if there is an increase in the node potential. As a result, the distribution of electrons narrows as the reset (under weak-inversion) progresses. This causes sub-kTC reset noise. Further, since the reverse current is negligible, the interaction between power supply fluctuations and the sense node 702 may be significantly reduced. This allows the soft reset to provide high PSRR.
- FIG. 8 illustrates a timing diagram (for still imaging mode) showing the reset (RST) pulse 800 and the signal (SHR) pulse 802 indicating when the reset level is sampled.
- RST reset
- SHR signal
- SENSE node 702 may not be discharged enough for the subsequent reset to affect the potential of the SENSE 702 node. Consequently, the difference between the signal and the reset levels significantly decrease for small signals thereby causing response non-linearity at low-light levels.
- actual reset levels may vary depending upon the signal in the previous frame. The actual signal may be calculated by the computed difference between the potential on the sense node before and after reset. Thus, variation of the reset level results in steady- state non-linearity due to modulation of the reset level by the average signal strength. Under dynamic lighting conditions, the reset level will vary from one frame to another depending upon the signal integrated in the previous frame. The variation of the reset levels between successive frames is the measure of image lag. Thus, both steady-state and dynamic response are degraded with soft-reset, even though it results in lower reset noise .
- FIG. 9 shows the response measured from a large format (e.g. 512x512) imager operated with the timing shown in FIG. 8.
- the response "dead-zone" may be seen for low-light levels.
- the dead-zone may be substantially reduced by holding the reset low during t idle . This may prevent biasing of the reset transistor in deep sub- threshold condition. However, the response non-linearity at low-light levels may still be significant. This is illustrated in the SPICE simulation results of FIG. 10.
- FIG. 10 plots the simulated potential variations of the SENSE node 702 as the node is periodically reset for different voltage excursions during the reset OFF state. The result indicates that the actual reset level is higher by more than 30 mV under low-light-levels .
- FIGS. 11A and 11B show the flushed 1100 and the hard-to-soft (HTS) 1150 photodiode APS pixels, respectively, in accordance with an embodiment of the present disclosure.
- the flushed photodiode pixel 1100 shown in FIG. 11A, includes of an additional line ( HTS ) 1102 that controls the potential at the drain 1104 of the reset transistor.
- the HTS photodiode APS 1150 (FIG. 11B) has the same pixel design as that of the flushed APS pixel 1100.
- the power supply (V dd ) 1156 is routed to each column 1158 through an n- 1152 or p- channel 1154 transistor.
- FIG. 12 shows a timing diagram of a pixel.
- HTS is a row-decoded signal for the flushed photodiode pixel 1100, and it is a common signal for the HTS pixel.
- the reset (RST) pulse ON causes the pixel to be reset first in hard-reset, followed by a soft -reset.
- the hard-reset level is determined by the sizing of the transistors, and is set to approximately i» ,dd"
- the hard reset erases the pixel memory.
- the soft-reset level reaches the same level irrespective of the photosignal strength, as shown in PSPICE simulations in FIG. 13. Unlike in FIG.
- the soft-reset level no longer depends upon voltage excursions at SENSE node.
- HTS mode of operation does not affect the reset noise. Since equation 3 indicates that as long as An is large, the contribution from the initial variance (due to hard- reset in this case) is low. Therefore, the imager performance does not depend upon the actual value of the hard-reset level.
- FIG. 14 shows the measured response linearity with the imager operated in double delta sampling mode. The results demonstrate that the imager operated in soft-reset mode exhibits significant low-light level non-linearity. The results also indicate that the non-linearity is undetectable in the other three modes down to the read noise levels
- FIG. 15 shows that the image lag is high ( ⁇ 2%) for large signals (in the previous frame) .
- the image lag drops sharply to less than 1% for smaller signals.
- the measured noise for hard-reset and HTS mode of operations is shown in FIG. 16.
- the noise performance closely follows the model, with the noise for hard-reset mode being given by kTC , and less than yj ⁇ .5-kTC for HTS mode .
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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JP2001526798A JP3908534B2 (en) | 1999-09-30 | 2000-10-02 | Fast on-chip windowed centroiding using photodiode-based CMOS imager |
AU11905/01A AU1190501A (en) | 1999-09-30 | 2000-10-02 | High-speed on-chip windowed centroiding using photodiode-based cmos imager |
Applications Claiming Priority (4)
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US15721199P | 1999-09-30 | 1999-09-30 | |
US60/157,211 | 1999-09-30 | ||
US15755699P | 1999-10-04 | 1999-10-04 | |
US60/157,556 | 1999-10-04 |
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PCT/US2000/027169 WO2001024104A1 (en) | 1999-09-30 | 2000-10-02 | High-speed on-chip windowed centroiding using photodiode-based cmos imager |
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US (2) | US6519371B1 (en) |
JP (2) | JP3908534B2 (en) |
KR (1) | KR100457283B1 (en) |
AU (1) | AU1190501A (en) |
WO (1) | WO2001024104A1 (en) |
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US5175802A (en) * | 1986-08-28 | 1992-12-29 | Hughes Aircraft Company | Macro image processing system |
US5648642A (en) * | 1992-06-08 | 1997-07-15 | Synaptics, Incorporated | Object position detector |
Also Published As
Publication number | Publication date |
---|---|
US20030133625A1 (en) | 2003-07-17 |
US6519371B1 (en) | 2003-02-11 |
JP3908534B2 (en) | 2007-04-25 |
JP2003510727A (en) | 2003-03-18 |
US6721464B2 (en) | 2004-04-13 |
JP2007110741A (en) | 2007-04-26 |
KR20020052185A (en) | 2002-07-02 |
AU1190501A (en) | 2001-04-30 |
KR100457283B1 (en) | 2004-11-16 |
JP4527100B2 (en) | 2010-08-18 |
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