WO2001015237A1

WO2001015237A1 - Chip-sized optical sensor package

Info

Publication number: WO2001015237A1
Application number: PCT/US2000/022836
Authority: WO
Inventors: Thomas P. Glenn; Roy D. Hollaway; Anthony Arellano
Original assignee: Amkor Technology, Inc.
Priority date: 1999-08-20
Filing date: 2000-08-18
Publication date: 2001-03-01

Abstract

One or more chip-sized optical sensor packages are fabricated simultaneously from a single insulating substrate having one or more chip-mounting stations defined on its upper surface. In each station, a photosensor chip is mechanically attached to the upper surface of the substrate such that a photosensitive surface of the chip faces upward and is parallel to the upper surface of the substrate. The chip is electrically interconnected to the upper surface of the substrate, and through the substrate, to electrical terminals on the bottom surface thereof. A dam is formed on the upper surface of the substrate around its perimeter, or alternatively, around each station on the substrate, to define one or more open-topped pockets containing the chips. The pockets are filled with an optically clear, liquid encapsulant to completely cover the chips and their respective interconnects, and the encapsulant is cured to solidify it, thereby forming a solid, optically clear layer of encapsulant over each of the chips. The layer of encapsulant has an upper surface that is inherently flat and parallel to the photosensitive surface of the chip. The substrate and the encapsulant are then cut, preferably by sawing, along the periphery of each station and closely adjacent to the edges of the associate chip such that the edges of the layer of encapsulant are coincident with the edges of the substrate and the one or more individual, chip-sized packages are thereby formed.

Description

CHIP-SIZED OPTICAL SENSOR PACKAGE

RELATED APPLICATIONS This is a continuation-in-part of Application Ser. No. 08/741,797, filed 10/31/96, the disclosure of which, by this reference, is incorporated herein in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention:

This invention relates to the electronic packaging art, and more particularly, to a method of packaging a solid state optical sensor microchip and the resulting structure.

2. Description of the Related Art:

As consumer-oriented electronic devices become increasingly more compact and lightweight, it becomes correspondingly more desirable to reduce the size of integrated circuit ("IC") chip packages, and at the same time, to reduce their manufacturing cost. It is even more desirable if this reduction in size and manufacturing cost can be achieved in a special-purpose IC chip package, such as an optical sensor package.

The advent of simple, relatively inexpensive semiconductor, or solid-state, optical sensors has changed the way light images are captured, manipulated, broad- cast, reproduced, and displayed. The last decade or so has seen a proliferation in the variety of such devices that are available, not only to high-end users, such as professional video studios and graphics art houses, but to ordinary consumers as well. These devices include relatively low-cost video cameras, digital still cameras, desktop scanners, film scanners, bar-code scanners, fingerprint recognition devices, and the like, that are capable of capturing relatively high resolution monochrome or color images, and converting them into analog or digital signals for storage, manipulation and/or distribution.

Such devices typically comprise a camera or other imaging device capable of capturing the light emitted by or reflected from a scene or subject, and focusing, reflecting or projecting that light onto a photosensitive surface, which typically comprises a square or rectangular array of tiny, solid state photosensor elements, or "pixels," such as charge-coupled-devices ("CCDs"), metal oxide semiconductor ("MOS"), or complementary metal oxide semiconductor ("CMOS") photorecep- tors. Examples of such semiconductor photosensor arrays can be found in the

"CMOS active pixel image sensor array" described by B. D. Ackland et al. in U.S. Pat. No. 5,835,141, the "staring array detectors ('SADs')" described by R. S. Holcomb in U.S. Pat. No. 5,864,132, and the "single chip color MOS image sensor" described by D. Chen et al. in U.S. Pat. No.5,901,257. These sensor microchips typically comprise planar, rectangular matrices, or arrays, of individual transducer elements fabricated on the surface of a semiconductor substrate, or microchip, typically silicon, by well known photolithographic techniques, that are capable, when electronically "addressed" on an element-by- element basis, of converting the light energy incident upon them into electrical signals. These signals, usually digital in nature, include information pertaining to, e.g., the intensity, color, hue, saturation, and other attributes of the light incident on the array, on a pixel-by-pixel basis. In some cases, particularly the so-called "cam- era-on-a-chip" applications, image signal processing and logic circuitry may also be integrated on the same chip as the sensor array.

Sensor array chips are typically individually packaged in moisture-proof packages having signal input/output terminals on a side or bottom surface, and a top surface comprising a clear glass or plastic window that exposes the light- sensitive elements of the sensor located below it to incident light. One such sensor package, known commercially as the Visionpak,™ is described in co-pending U.S.

Pat. App. Ser. No. 08/844,536, filed 04/18/97, and owned by the proprietor of this invention. Other types of optical sensor packages are known and commercially available. In light of the recent trend toward smaller, lower-cost consumer electronics described above, the desirability of a packaging method for optical sensors that results in both a smaller package size and a reduced packaging cost is evident.

BRIEF SUMMARY OF THE INVENTION In accordance with the present invention, a near-chip-sized optical sensor package and its method of manufacture are presented. In one embodiment, the package includes an IC optical sensor chip having a photo-sensitive upper surface with electrical bonding pads formed thereon. A lower surface of the sensor chip is mounted to the upper surface of an insulating substrate such that the photosensitive surface of the chip faces upward and is parallel to the upper surface of the underlying substrate. The upper surface of the substrate has first metallizations formed thereon. Each of the bonding pads on the chip is electrically connected to a corresponding one of the first metallizations. The photo-sensitive surface of the sensor chip, bonding pads, first metallizations, bond wires and the upper surface of the insulating substrate are then encapsulated in a layer of an optically clear, pro- tective encapsulant. The layer of encapsulant has an upper surface that is planar and parallel to the photo-sensitive surface of the chip, and edges that are coincident with the edges of the insulating substrate, and desirably, these two edges are spaced only slightly outboard of the edges of the sensor chip itself.

In a ball grid array ("BGA") type of sensor package, interconnection balls can be formed at bonding locations on the lower surface of the insulating substrate.

Alternatively, instead of interconnection balls, interconnection pads or through- pins can be formed or mounted at the bonding locations. Each of the interconnection balls, pads or pins are electrically coupled to a corresponding one of the first metallizations on the upper surface of the substrate, and thence, to the chip. The layer of encapsulant is formed of a material that is optically clear, so that light from, e.g., the lens of a camera, can be focused onto the underlying photo-sensitive surface of the encapsulated chip, e.g., a photo-detector array, and be converted thereby into an electronic image signal.

The sensor package formed in accordance with the present invention is nearly chip-sized (i.e., the distance between the edge of the insulating substrate and the sensor chip can be as small as 10 mil, and the package can have an overall thickness of less than 14 mils, excluding the height of the interconnection balls, pads or pins). Thus, the package is particularly advantageous in applications in which sensor package space is limited, such as in digital cameras, hand-held scanners, and laptop and hand held computers.

In accordance with the present invention, a method for fabricating several sensor chip packages simultaneously from a single substrate is also presented. The method includes providing a substantially planar insulating substrate having a plurality of chip-mounting stations on an upper surface thereof, each station having first metallizations formed thereon. A sensor chip is mounted in each of the stations. Each of the chips has a photo-sensitive upper surface, with bonding pads formed thereon, and the chips are attached to their respective stations such that the photo-sensitive surface of the chip faces upward and is parallel to the upper surface of the substrate. The bonding pads are electrically connected with bond wires to corresponding ones of the first metallizations on the upper surface of the corresponding stations. A dam is formed on, or attached to, the upper surface of the substrate around the perimeter of the substrate, or alternatively, around the pe- rimeter of each of the individual stations on the substrate, such that an open-topped pocket is defined around all of the attached and bonded chips, or alternatively, around each one of the chips.

An optically clear, liquid encapsulant is then poured into the one or more pockets surrounding the chips such that the photo-sensitive upper surfaces of the sensor chips, the bonding pads, the first metallizations, and the upper surface of the insulating substrate are completely covered and enclosed within a layer of clear, protective encapsulant. After curing, the encapsulant has an upper surface that is inherently flat and parallel to the upper surface of the substrate, and hence, to the upper, light-sensitive surface of the chip. The layer of encapsulant and the insulat- ing substrate are cut around the periphery of each of the stations along a line adjacent to the edges of the chip contained therein to form the plurality of individual, chip-sized, integrated circuit sensor chip packages.

As above, the method can further include forming interconnection balls, or alternatively, interconnection pads or through-pins, at substrate bonding locations on a second, lower surface of the insulating substrate, the interconnection balls, pads or pins being electrically connected to corresponding ones of the first metallizations on its upper surface, or directly to the chip itself.

The encapsulating layer is preferably formed of an optically clear resin or plastic such that its upper surface is substantially flat, or planar, and parallel to the underlying light-sensitive surface of the encapsulated sensor chip, so that light incident on the upper surface of the package passes through the thickness of the encapsulant to reach the light-sensitive surface of the sensor chip unimpeded and unalterefl in its optical characteristics. Fabricating a plurality of packages simultaneously (as opposed to individually) from a single substrate advantageously reduces handling costs and substrate waste, thereby reducing the cost of fabricating each individual package.

These and other objects, features and advantages of the present invention will become more readily understood from the detailed description of the preferred embodiments set forth below, especially if these are considered in conjunction with the accompanying drawings. A brief description of those drawings now follows. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS Figure 1 is a cross-sectional view of an optical sensor package in accordance with one embodiment of the present invention; Fig. 2A is a top plan view of a substrate in accordance with the present invention; Fig. 2B is a cross-sectional view into the substrate taken along the line IIB-IIB in

Fig. 2A; Fig. 3 A is a cross-sectional view of a chip-mounting station on the substrate of Fig.

2A, as revealed by the section taken along the line IIIA-IIIA in Fig. 2A; Figs. 3B and 3C are top and bottom plan views, respectively, of a chip-mounting station on the substrate shown in Fig. 2 A;

Figs. 4A and 4B are cross-sectional and top plan views, respectively of an optical sensor package in accordance with the present invention at a pre- wire- bonding stage of its fabrication; Figs. 5 A and 5B are cross-sectional and top plan views, respectively, of the optical sensor package of Figs. 4A and 4B after wire bonding and before encapsulation; and, Figs. 6A and 6B are cross-sectional and bottom plan views, respectively, of the optical sensor package of Figs. 5 A and 5B after encapsulation and before package cutting.

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a low-cost, chip-sized, optical sensor package, together with the method for its manufacture. Figure 1 is a cross-sectional view of a package 10 in accordance with the present invention. The package 10 includes an insulative substrate 12 having electrically conductive "vias," or through-holes 14. The conductive through-holes 14 may be formed by drilling holes in the substrate 12 and then plating the drilled holes with a conductive material, such as copper. Illustratively, copper is plated to

a minimum thickness of about 600 micro-inches (μin). Alternatively, electrically-

conductive through-pins (not illustrated) may extend through the substrate 12.

The substrate 12 is typically a ceramic, a multi-layer laminate, a passivated metal, or a printed circuit board substrate material. Examples of suitable ceramic substrates include 98% alumina or 98% aluminum nitride ceramic substrates available from Sumitomo, Kyocera, NTK and Coors. Examples of suitable laminate substrates include BT (Mitsubishi), FR-4, FR-5, Arlon and GTEK (Matsushita Electric) laminate substrates. An example of a suitable passivated metal substrate includes an anodized aluminum substrate available from Alcoa. Kovar substrates, available from a variety of vendors, are also used in optical sensor applications.

The vias, or conductive through-holes 14, extend from an upper surface 18 of the substrate 12 to a lower surface 20 thereof. Electrically conductive traces or metallizations 22, typically copper, are formed on the upper surface 18. Each of the traces 22 is electrically connected on a first end to a corresponding conductive through-hole 14. A contact 23 is formed on each metallization 22. The contact 23 is preferably a layer of gold or a multi-layer metallization with a gold outer layer, and may also include nickel. In one preferred embodiment, the contact 23 is a

nickel layer and an overlying gold layer having minimum thicknesses of 200 μin

and 20 μin, respectively. Electrically conductive traces or metallizations 26, typically copper, are also formed on the lower surface 20 of the substrate 12, and each of these is electrically connected on a first end to a corresponding conductive through-hole 14. A contact 27, similar to the contact 23, is formed on a second end of each metalliza- tion 26.

The metallizations 22, 26 can be formed, for example, by masking and etching conductive layers previously formed on the first and second surfaces 18, 20 of the substrate 12. Alternatively, the metallizations can be plated onto a bare substrate in the desired configuration. The contacts 23, 27 are formed using con- ventional processes, such as electroplating or electro-less plating.

In a ball grid array ("BGA") type of optical sensor package, interconnection balls 28, which are used as the input/output terminals of the package 10, are formed on the contacts 27. Each of these interconnection balls 28 is electrically connected to a second end of a metallization 26 by one of the contacts 27. The interconnection balls 28 enable electrical signal and power interconnections to be made between the package 10 and other electrical components and circuit elements (not shown). The interconnection balls 28 are typically arranged in a rectangular or square array, thus forming a "ball grid array."

In an alternative embodiment, the contacts 27 themselves may be used as interconnection pads instead of the interconnection balls 28. In this embodiment, the typical minimum spacing between adjacent interconnection pads (i.e., the contacts 27) is from about 0.30 millimeter (mm) to about 1.00 mm.

In yet another embodiment, through-pins (not illustrated) having a head corresponding to the contacts 23 on the upper surface 14 of the substrate 12 can be mounted in openings in the substrate to extend through the substrate and protrude vertically below its lower surface 20. In such an embodiment, vias are unnecessary, but in a substrate 12 made of an electrically conductive material, an insulator between the pin and the substrate is obviously required to prevent shorting between the two.

In Fig. 1, an exemplary electrically conductive pathway between an interconnection ball 28 and a metallization 22, comprising a contact 27, a metallization 26 and a conductive through-hole 14, is illustrated. However, it should be understood that other electrically conductive pathways can be established between the interconnection balls 28 (or the interconnection pads) and the metallizations 22.

For example, the substrate 12 can be a multilayer laminate substrate having a plurality of electrically conductive vias electrically connecting conductive traces formed in the various layers thereof, in a manner well known to those skilled in the art. Thus, it should be understood that the electrically conductive pathway formed by the contact 27, the metallization 26 and the conductive through-hole 14 is shown by way of example, and not by way of limitation, and that other electrically conductive pathways can be formed between the interconnection balls or interconnection pads and the corresponding metallizations 22.

In the package 10 of this invention, an integrated circuit (IC) optical sensor chip 30 is mounted to the upper surface 18 of the substrate 12. In particular, a first, lower surface 32 of the sensor chip 30 is mounted to the upper surface 18 of the substrate 12, typically by means of an epoxy adhesive 34, such that a light- sensitive second, upper surface 36 faces upwardly from the substrate 12. In the embodiment illustrated in Fig. 1, electrical bonding pads 38 are formed on the second, light-sensitive surface 36 of the sensor chip 30 adjacent to an optical sensor array 35 located on that surface of the chip (see Figs. 4A and 4B).

The bonding pads 38 are electrically connected to the internal electronic components of the sensor chip 30, and are typically formed during the fabrication of the chip. Each bonding pad 38 is electrically connected to a corresponding metallization 22 on the substrate 12 by means of an electrically conductive bonding wire 40, which is bonded at one end to the bonding pad 38 and at the other end to a contact 23. Thus, an electrically conductive pathway is established between each bonding pad 38 on the upper surface 32 of the sensor chip 30 and a corresponding interconnection ball 28 on the lower surface 20 of the substrate 12 (see Figs 5 A and

5B).

The entire upper surface 36 of the sensor chip 30, including the sensor array 35, the bonding pads 38, the bond wires 40, the exposed first surface 18 of the substrate 12, the contacts 23, and the metallizations 22 are then encapsulated, preferably by means of a "casting" process described in detail below, in a protective layer of a hard, optically transparent layer of encapsulant 42. As shown in Fig. 1, the edges 43 of the layer of the clear encapsulant 42 are formed coincident with the edges 46 of the substrate 12, in a manner described below, and are spaced only slightly outboard of the edges 44 of the chip 30. Importantly, as a result of the casting process used, the upper surface 48 of the clear encapsulant 42 is controlled to be substantially planar and parallel to the planar photo-sensitive upper surface 32 of the sensor chip 30, and the thickness C of the layer of encapsulant 42 over the upper surface 36 of the chip 30 is preferably controlled to be between from about 0.125 millimeters (mm) to about 0.50 mm. Optionally, an electrically insulating solder mask 39 that does not cover the contacts 27 or the interconnection balls 28 can be formed over selected portions of the lower surface 20 of the substrate 12 and the metallizations 26. The solder mask 39 is applied and patterned using conventional techniques to prevent electrical shorting between adjacent metallizations caused by unintended solder bridging.

The package 10 (Fig. 1) resulting from the method of the present invention is a near-chip-sized integrated circuit package, i.e., the distance A between any edge 44 of the sensor chip 30 and any edge 46 of the substrate 12 can be as small as 10 mil (1 mil = 1/1000 inch), and typically, is between 40 to 60 mil. Further, the distance B between the upper surface 48 of the layer of encapsulant 42 and the lower surface 41 of solder mask 39, which depends in substantial part upon the thickness of the substrate 12, the thickness of the sensor chip 30, and the thickness of the layer of clear encapsulant 42 overlying the sensor chip 30, is generally less than 60 mil, and typically, is between about 40-60 mil. In an exemplary package 10, the substrate 12 has a thickness of between 0.36-0.56 mm, the sensor chip 30 has a thickness of about 400-500 mm, preferably about 430 mm, and the layer of clear encapsulant 42 over the sensor chip 30 has a preferred thickness of about 0.3 mm. Since the package 10 is nearly the same size as the chip 30, the package is particularly advantageous in applications where limited space is available for the sensor chip package, such as in hand held digital cameras, optical scanners, palmtop computers, and the like.

Figure 2 A is an enlarged top plan view of a substrate 13 in accordance with the present invention. A plurality of vertical and horizontal lines 56 and 58, respectively, are included in Fig. 2A and in the subsequent figures to define one or more chip-mounting stations 12 on the substrate 13 at which each individual package is formed in accordance with the method described in detail below. For clarity, two stations 12 are labeled in Fig. 2 A. However, it should be understood that from one to several of such stations 12 can be defined on the substrate 13, depending on the particular task at hand. As shown in Fig. 2A, the periphery of each station 12 is defined by the virtual lines 56, 58. However, in an alternative embodiment, instead of the virtual lines 56, 58, actual alignment marks, such as inked or scribed lines 56, 58, may be provided on the substrate 13 for aligning the substrate 13 in subsequent processing steps, such as those described below. The substrate 13 is prefera- bly a square or a rectangular substrate, for example, a 2.0 in. x 2.0 in. (5.1 cm x 5.1 cm), a 3.0 in. x 3.0 in. (7.6 cm x 7.6 cm) or a 4.0 in. x 4.0 in. (10.2 cm x 10.2 cm) square substrate.

Figure 3 A is a cross-sectional view of the substrate 13, and in particular, of one of the stations 12, as taken along the line IIIA-IIIA in Fig. 2A, in accordance with one embodiment of the present invention. Figure 3B is a top plan view of a region 50 of the substrate 13 shown in Fig. 2 A, and in particular, of one of the stations 12. Figure 3C is a bottom plan view of the region 50 of the substrate 13.

Figures 3 to 6 illustrate various stages in the formation of the sensor package 10 of the present invention. Although the formation of a single package is described for clarity, it should be understood that, advantageously, a plurality of packages may be formed simultaneously from a single substrate 13, one at each station 12 of the substrate 13.

Figures 4A and 4B are cross-sectional and top plan views, respectively, of the package 10 at the chip-attachment stage of its processing. As shown in Fig. 4B, the sensor chip 30 is mounted to its respective station 12 in a location central to the metallizations 22, and importantly, with the sensor array 35 on the light-sensitive second surface 36 of the chip 30 facing upward and parallel to the upper surface 18 of the substrate 12. In one typical embodiment, the distance between the edges 44 of the chip 30 and the metallizations 22 is approximately 10 mils. As shown in

Fig. 4 A, the first surface 32 of the sensor chip 30 opposite to its second, light- sensitive surface 36 is mounted to the upper surface 18 of the substrate 13 by a layer of adhesive 34. Importantly, the adhesive 34 used to attach the chip 30 to the substrate 13 must be one that is compatible with, i.e., one that does not contami- nate, the optically clear encapsulating material, e.g., by the "bleeding" of an opaque constituent, when the encapsulant is later formed over the chip. One such non-contaminating chip-attachment adhesive is Polyset APS-A-100-OlA.

Figures 5 A and 5B are cross-sectional and top plan views, respectively, of the package 10 further along in the fabrication process. As shown in Figs. 5 A and 5B, the bonding pads 38 are electrically connected to corresponding contacts 23 in the station by conductive bond wires 40, made of, for example, gold or aluminum, using conventional wire bonding techniques. Examples of such techniques include gold ultrasonic, aluminum ultrasonic and gold thermocompression bonding techniques. However, in an alternative embodiment, the contacts 23 are not formed on the substrate 13, and the bond wires 40 are directly bonded to corresponding metallizations 22, or in yet another embodiment (not illustrated), to the upper, upset ends, or heads, of through-pins that extend through the thickness of the substrate 12. As shown in Figs. 2A and 2B, in the preferred encapsulation method of this invention, a continuous dam 59 is formed on the upper surface 18 of the substrate 13 around the perimeter of the substrate 13 to define an open-topped "pocket" containing the entire upper surface of the substrate. The dam 59 encloses the chip- mounting stations 12, yet does not extend into any one of them. In an alternative embodiment, the dam 59 can be formed to include a plurality of individual open- topped pockets, one containing each of the stations 12, as shown by the dotted lines in Figs. 2 A and 2B.

Figure 2B is a cross-sectional view of the substrate 13 taken along the line IIB-IIB in Fig. 2 A. In Fig. 2B, the metallizations, conductive through-holes and other substrate features have been omitted for clarity. As shown in Fig. 2B, the dam 59 extends upward from the first surface 18 of the substrate 13 to a predetermined height above the first surface 18, as indicated by the dashed line 68, thereby defining a pocket which can be filled with a volume of clear, liquid encapsulating material, as described in more detail below.

With one important exception, the dam 59 can be almost any material suitable for retaining the uncured liquid encapsulating material within the pocket and preventing it from flowing off of the substrate 13 until it has been hardened, or solidified, by curing. As in the case of the chip-attachment adhesive material 34 and the flip-chip underfill material 37 described above, the material of the dam 59 must be one that is compatible with, i.e., one that does not contaminate, the optical properties of the clear, chip-encapsulating material used to fill the pocket(s) defined by the dam 59. In one embodiment, the dam 59 is formed by "writing" it, i.e., dispensing it from the tip of an automatically controlled, programmably movable nozzle, in the form of a continuous bead of a relatively stiff, or paste-like, encapsulant, such as Polyset APS-D 100-01 A, or an equivalent resin. If the dam material is fairly stiff, or viscous, when it is written onto the substrate, then it will not slump appreciably, and may have adequate strength to retain the liquid encapsulating material 42 in the pocket without curing. On the other hand, if the dam material is not sufficiently stiff, or there is to be some delay and/or moderate handling of the substrate 13 before the liquid encapsulating material 42 is poured into the pocket(s), then it is preferable to cure the material of the dam 59, at least partially, after it has been applied, by heating the assembly in an oven. In an alternative embodiment, it may be desirable to prefabricate the dam

59 in the form of a rigid, appropriately sized plastic or resin "picture frame," and then simply adhere it to the surface of the substrate 13 with an appropriate (i.e., non-contaminating) adhesive to define the encapsulation pocket(s) thereon.

Figure 6 A is a cross-sectional view of the package 10 at a later stage in its processing. As shown in Fig. 6 A, after the sensor chip 30 has been attached to its respective station 12 (Fig. 4A), and electrically interconnected to the substrate 13 (Fig. 5A), the pocket around the chip defined by the dam 59 is filled with a volume of a thin, optically clear, liquid encapsulant material 42 to a depth sufficient to form a layer of encapsulant 42 over the entire assembly on the first, upper surface 18 of the substrate 13, or alternatively, over each chip 30 contained by an individual pocket. In particular, the layer of encapsulant 42 covers the chip 30, including the sensor array 35, the bonding pads 38, the bond wires 40, the contacts 23, the metallizations 22 and the remaining exposed first surface 18 of the station 12 on the substrate 13. The preferred thickness C of the layer of encapsulant 42 over the upward- facing, light-sensitive upper surface 36 of chip 30 is from about 0.125 mm to about 0.5 mm, and is controlled by carefully controlling the amount of liquid encapsulant 42 introduced into the pocket(s).

The dam 59 forms a seal with the upper surface 18 of the substrate 13 and prevents the encapsulant 42 from leaking out of the pocket(s) and flowing off of the substrate 13. The dam 59 has a height, indicated by the dashed line 68 (see Fig. 2B), above the upper surface 18 of the substrate 13 that is greater than or equal to the height of the upper surface 48 of the layer of encapsulant 42 above it (see Fig. 6A). The layer of encapsulant 42 is formed of a transparent, electrically insulating encapsulant, preferably Polyset APS-F 100-01 A, or Ciba Nagese CB-103 clear encapsulant. These materials are preferred because they are optically clear, and because they retain that clarity over time and after exposure to air and light, particularly ultra-violet light, without discoloring ("yellowing") or becoming opaque. Referring back to Figs. 2A and 2B, and in particular, to Fig. 2B, the layer of encapsulant 42 is formed by filling the pocket(s) defined by the dam 59 with the liquid encapsulant 42, preferably by means of a programmable, automatically controlled dispensing unit that has a solid-displacement, or "airless," pumping action, i.e., one that entrains no air into the encapsulant while it is being dispensed. The liquid encapsulant 42 preferably has a viscosity about the same as that of water at room temperature when it is dispensed, so that it flows freely within the pocket to reach a uniform level in the pocket and immerses the components therein without entrapment of voids, and importantly, such that it forms an upper surface 48 that is, except for a slight meniscus formed around the inside periphery of the dam 59 where it is wetted by the liquid encapsulant 42, both substantially flat, or planar, and parallel to the upper surface 18 of the substrate 13, and hence, parallel to the photo-sensitive upper surface 36 of the sensor chip 30.

Controlling the flatness of the upper surface 48 of the encapsulant 42 and its parallelism with the surface 36 of the sensor array 35 is important because, if it is not made flat and/or parallel to the sensor array, image light incident upon the surface 48 will be refracted by the surface at an angle relative to, rather than parallel with, the vertical "optical axis" of the sensor array 35, and thereby degrade the image sensed by the array. Of course, it is possible to lap-polish the upper surface 48 of the package 10 to obtain any degree of flatness and parallelism desired.

However, this additional step adds an undesirable cost to the finished package, and is generally unnecessary, provided only that: i) the substrate 13 material is, at least in the region of the individual stations 12, flat, or substantially planar, within the ordinary manufacturing tolerances for typical substrate materials; ii) the chip 30 is mounted to the upper surface 18 of each station 12 such that its upper, light- sensitive surface 36 is parallel to the upper surface 18 of the station 12 within standard manufacturing tolerances, as described above; and, iii) the upper surface 48 of the liquid encapsulant 42 is maintained parallel to the upper surface 18 of the substrate 13 while it is being cured, as described in more detail below. Although it is generally unnecessary, it is possible to subject the liquid encapsulant 42 in the open-topped pockets to a vacuum environment after it has been dispensed into the pockets, either for a short duration, or for the length of the cure period of the encapsulant, to ensure that any entrapped air bubbles or out- gassed pockets generated during dispensing of the encapsulant or its polymeriza- tion during curing are extracted from the volume of encapsulant. A similar result can achieved by subjecting the substrate assembly to ultrasonic vibrations, provided the upper surface 48 of the encapsulant 42 is not displaced appreciably during cure. When the layer of liquid encapsulating material 42 has been dispensed into the pocket(s) as described above, it is cured to harden, or solidify it. Persons skilled in the art will recognize that many encapsulating materials are cured by irradiating them with ultraviolet light. However, this method of curing is not indicated in many optical sensor applications, or at least not those incorporating CMOS photo- receptors, because the wavelength of ultraviolet light used for such curing can permanently damage such receptors. Accordingly, the generally preferred method of curing the encapsulating material 42 is by heating the assembly in an oven at the temperature and for the length of time indicated by the particular encapsulant 42 involved. In this regard, it is important that the upper surface 18 of the substrate 13, and hence, the upper surface 48 of the liquid encapsulant 42, be maintained completely level, or horizontal, during the entire cure period, so that the upper surface 48 of the encapsulant is substantially planar and parallel to the photo-sensitive surface 36 of the underlying sensor chip 30, for the reasons discussed above. This is readily achieved by ensuring that the shelf or tray in the curing oven upon which the substrate 13 is placed is carefully adjusted to be level with the earth, so that the upper surface 48 of the liquid encapsulant 42 is constrained by gravity to lie in a substantially horizontal plane.

Figures 6A and 6B are cross-sectional and bottom plan views, respectively, of the package 10 after encapsulation. In Fig. 6B, the optional solder mask 39 is omitted for purposes of clarity. As shown in Figs. 6A and 6B, in a BGA package 10, interconnection balls 28, typically eutectic (i.e., 63% tin and 37% lead) solder balls, are attached to the contacts 27 using conventional attachment techniques, e.g., re-flow soldering. In Fig. 6B, the interconnection balls 28 are shown arranged in a rectangular array. Other interconnections, such as the contact pads 27 or the through-pins described above, may be used. Further, the interconnection balls or pads can be arranged in a linear arrangement around only the perimeter of the station 12, i.e., near the lines 56, 58, rather than in the aπay fashion as shown in Fig. 6B. Referring to Fig. 6A, after the encapsulant 42 has been cured, the substrate

13 and the layer of encapsulant 42 are cut through, typically by sawing, along the lines 56, 58 (shown dotted in Fig. 6A) to form the finished package 10 (see Fig. 1). For this purpose, a blue wafer mounting tape (available from Nitto Denko Corp. of Japan, for example) that is conventionally used to hold a semiconductor wafer while it is being cut into individual dies, or chips, can be used to hold the substrate

13 while it and the layer of encapsulant 42 are being simultaneously cut to form the packages 10, as those persons having skill in the art will readily understand. The substrate 13 and the layer of encapsulant 42 are both sawn through down to, but not through, the blue mounting tape, such that the individual packages 10 remain attached to the mounting tape in their respective original positions after cutting.

Cutting the substrate 13 simultaneously with the layer of encapsulant 42 results in a package 10 in which the edges 43 of the layer of encapsulant 42 are coincident with the edges 46 of the substrate 12 (see Fig. 1). It should be understood that, in this embodiment, the substrate 12 (Fig. 1) in each of the plurality of packages 10 coπesponds to a station 12 of the original, larger substrate 13 (Fig. 2A).

After the substrate 13 and the layer of encapsulant 42 have been cut, yet while the individual packages 10 are still mounted on the blue wafer-mounting tape, each package 10 is tested and packages that are bad are so marked. (The substrate 13 is preferably mounted on the blue wafer-mounting tape with the layer of encapsulant 42 facing down onto the blue wafer-mounting tape and with the interconnection balls 28 facing up.) Testing involves contacting the interconnection balls 28 (which are conveniently facing upwards) with test probes or contacts, in a manner known to those skilled in the art. Testing the plurality of packages together, while the packages are still mounted on the blue wafer-mounting tape, is faster and advantageously reduces testing cost as compared to placing each package into a tester individually and testing them one at a time.

Referring again to Fig. 2 A, fabricating a plurality of packages simultane- ously from a single substrate 13, in contrast to individually, also advantageously reduces handling costs, thereby further reducing package fabrication costs. Also, by fabricating a plurality of packages simultaneously from a single substrate 13, waste or trimming of the substrate 13 is reduced or essentially eliminated, thereby further reducing packaging costs. (In contrast, when integrated circuit packages are individually fabricated, the substrate is made slightly oversized to enable handling of the substrate, and the excess substrate is trimmed and scrapped in subsequent fabrication steps.)

Although the present invention has been described with reference to certain preferred embodiments, persons skilled in the art will recognize that various modi- fications can be made in terms of its materials and processes without departing from the spirit and scope of the invention.

For example, it may be desirable in some applications to coat the upper surface 48 of the package 10 with an anti-reflective coating of the same type as used on the lenses of some cameras to reduce the amount of light reflected from that surface back toward the image producing device.

As another example, it is possible to eschew the "open-mold" casting process described above in favor of the more conventional closed-mold, transfer- molding, or "overmolding," process to form the clear layer of encapsulant 42 over the chips 30. In such a case, a suitable mold set must be provided, and a suitable clear transfer molding compound, such as Nitto 309H, for example, should be substituted for the clear liquid encapsulant materials 42 described above.

Thus, the embodiments of the invention illustrated and described herein should be taken as exemplary in nature only, and not by way of any limitation on the scope of this invention, which is defined by that of the claims appended hereafter.

Claims

WHAT IS CLAIMED IS:

1. A chip-sized optical sensor package, comprising: an insulative substrate; an optical sensor chip mounted on an upper surface of the substrate such that a light-sensitive surface on the chip faces upward; and, a layer of optically clear encapsulant covering the upper surface of the substrate and the chip, the layer of encapsulant having edges coincident with edges of the substrate.

2. The sensor package of Claim 1, wherein the light-sensitive surface of the chip is planar.

3. The sensor package of Claim 2, wherein the light-sensitive surface of the chip is parallel to the upper surface of the substrate.

4. The sensor package of Claim 2, wherein the layer of encapsulant has a planar upper surface that is parallel to the light-sensitive surface of the chip.

5. The sensor package of Claim 1, further comprising means for electrically connecting the chip to a circuit below a lower surface of the substrate.

6. A method for making a chip-sized optical sensor package, comprising: providing an insulative substrate having a chip-mounting station on an upper surface thereof; attaching an optical sensor chip to the station such that a light-sensitive surface on the chip faces upward; and, forming a layer of optically clear encapsulant over the upper surface of the substrate and the chip such that edges of the layer of encapsulant are coincident with edges of the substrate.

7. The method of Claim 6, wherein the light-sensitive surface of the chip is planar, and wherein mounting the chip to the station comprises mounting the light- sensitive surface of the chip parallel to the upper surface of the substrate.

8. The method of Claim 6, wherein forming the layer of encapsulant further comprises forming the layer to have an upper surface that is planar.

9. The method of Claim 8, wherein forming the layer of encapsulant further comprises forming the upper surface of the encapsulant parallel to the upper surface of the substrate.

10. The method of Claim 7, wherein forming the layer of encapsulant further comprises forming the upper surface of the encapsulant to have an upper surface that is planar and parallel to the light-sensitive surface of the chip.

11. The method of Claim 6, wherein forming the layer of encapsulant further comprises writing a dam on the upper surface of the substrate to define an open-topped pocket containing the station, and filling the pocket to a predetermined height with a liquid encapsulant.

12. The method of Claim 6, wherein forming the layer of encapsulant further comprises mounting a pre-formed dam on the upper surface of the substrate to define an open-topped pocket containing the station, and filling the pocket to a predetermined height with a liquid encapsulant.

13. The method of Claim 11 further comprising curing the dam to solidify it.

14. The method of Claim 6, further comprising cutting the layer of encap- sulant and the substrate around a perimeter of the station such that the edges of the layer of encapsulant are coincident with the edges of the substrate.

15. The method of Claim 14, wherein cutting the layer of encapsulant and the substrate around a perimeter of the station comprises sawing the encapsulant and the substrate.

16. The method of Claim 15, further comprising attaching an upper surface of the layer of encapsulant to an adhesive tape and sawing through the substrate and the layer of encapsulant around a perimeter of the station down to, but not through, the adhesive tape.

17. The method of Claim 16, further comprising applying a test probe to a lower surface of the substrate.

18. The method of Claim 7, further comprising lap-polishing an upper surface of the layer of encapsulant to be planar and parallel to the light-sensitive surface of the chip.

19. The method of Claim 6, further comprising forming an optical coating on an upper surface of the layer of encapsulant.

20. The method of Claim 6, further comprising electrically connecting the chip to a lower surface of the substrate.