WO2001015217A2 - Method for producing a semiconductor chip with an electrical property that can be adjusted after the silicon process - Google Patents

Method for producing a semiconductor chip with an electrical property that can be adjusted after the silicon process Download PDF

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Publication number
WO2001015217A2
WO2001015217A2 PCT/DE2000/002899 DE0002899W WO0115217A2 WO 2001015217 A2 WO2001015217 A2 WO 2001015217A2 DE 0002899 W DE0002899 W DE 0002899W WO 0115217 A2 WO0115217 A2 WO 0115217A2
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circuit
electrically conductive
wafer
capacitance
conductive layer
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PCT/DE2000/002899
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German (de)
French (fr)
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WO2001015217A3 (en
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Frank PÜSCHNER
Martin Häring
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Infineon Technologies Ag
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the invention relates to a method for producing a semiconductor chip, in which a multiplicity of integrated circuits of the same type are produced on a silicon afer (silicon process), which are subsequently tested for their functionality and properties, and in which the silicon afer m Chips with an integrated circuit is divided.
  • the structures produced on a silicon wafer using the methods of semiconductor technology are known to form electronic components, the cooperation of which determines the functionality of the semiconductor chip.
  • the structures themselves are usually applied to the older layer on the semiconductor chip using phototechnology using masks.
  • the intended function of the semiconductor chip can be impaired due to errors in the chip design or due to influences of process parameters during the manufacturing process or can fluctuate over several lots in the manufacturing process. If semiconductor chips manufactured lie outside the desired functional window due to the causes mentioned, a partial redesign of the semiconductor chip is usually sought in order to ensure the function in future lots.
  • a redesign for example, which aims to change the electrical properties of finished chips on a large scale, that is to say in batch or lot sizes, causes high costs due to the changes required in the silicon process and also causes significant delays in terms of market launch.
  • the aforementioned receiving capacity of the chip therefore decides on the efficiency, especially in the case of contactless chip cards, i.e. about the usability of the entire product family for the customer.
  • the chips for contactless smart cards require a much narrower range of values with regard to the input capacitance, for example 17.3 pF ⁇ 3%. Since the capacity strongly depends on the layout of the integrated circuit and also the process parameters during manufacture, with regard to this electrical property, there is currently only the choice to be satisfied with a low yield, or to try - without absolute certainty of results - with a complex redesign to achieve the desired one To achieve value.
  • WO 95/05678 specifies a method for producing thin-film inductors which can be integrated on a semiconductor chip together with other passive and active components. Resistors and capacitors are specified as passive components, which are integrated on the substrate of the chip as electrical conductors.
  • No. 5,872,040 describes a method for producing a thin-film capacitor which can be formed on a substrate made of a polymer or a ceramic and can be trimmed to an exact value by reworking one of the metal layers provided as capacitor plates.
  • FIG. 8 of this document describes an arrangement in which a chip with an integrated circuit is inserted in a recess in a substrate made of aluminum or plastic and is connected to an electrical resistor which is precisely adjusted according to the specified method and which is located on the top of the Substrate is applied.
  • WO 97/21118 describes a contactless transponder with a printed coil antenna, in which a conductor structure is applied as a capacitor for tuning the resonance frequency. It is pointed out that a change in the frequency can be made simply by changing the structure or thickness of the conductor track and thus a fast manufacturing process is possible.
  • JP 08-107040 A describes an electronic component as a bandpass filter, in which there is a capacitor formed by two printed circuit boards and the frequency is tuned by trimming a capacitor electrode.
  • US Pat. No. 4,560,445 describes a method for producing metallic structures on a thin film substrate, in which a structured copper layer is produced on an electrically conductive structure by means of electrodeposition.
  • the aim of the present invention is to provide a method of the type mentioned at the outset with which the electrical properties, in particular the input capacitance, of semiconductor chips can be influenced on a large scale and inexpensively without redesign.
  • this aim is achieved in a method of the type mentioned at the outset in that an individually dimensioned, external conductive layer is applied to the integrated circuits, so that the values of a certain initially inadmissibly varying within the large number of integrated circuits after the silicon process electrical properties of the circuits are set to a desired, essentially uniform value, the individual dimensioning of the external layer of each integrated circuit taking place as a function of the individual deviation of the measured value from the desired value of the electrical property determined during testing.
  • the invention is based on the idea of subsequently adjusting the chip properties, that is to say after the silicon process and test, not by means of redesign, but in the case of the semiconductor modules already present, by applying a conductive layer for each chip.
  • the application of the conductive layers for example of copper, is preferably carried out chemically additively to the individual circuits of the wafer.
  • This variant in which the layer is structured (exposed) individually, but the circuits are coated in a common deposition bath, i.e. simultaneously, is particularly economical. In principle, however, the application can also be carried out individually on the finished semiconductor chips obtained by sawing the wafer.
  • physical deposition processes such as sputtering are also generally suitable. You can also have several Layers are arranged one above the other, which together, or together with the respective circuit, give the desired electrical value.
  • the layers are insulated from one another and from the semiconductor chip by non-conductive layers.
  • the external layer can thus be applied inexpensively and quickly after the silicon process. This makes it easy to change the electrical properties of the finished circuit.
  • the capacity of the integrated circuit can thus be applied inexpensively and quickly after the silicon process. This makes it easy to change the electrical properties of the finished circuit.
  • Circuit in particular the input capacitance of a semiconductor chip for a contactless chip card, can be adapted to a desired value according to the invention after the silicon process.
  • the determination of the deviation of the individual values of the circuits does not require any special effort, since the database for this, that is to say the measurement of the actual individual values of the circuits, is anyway determined in the course of the tests customary in production.
  • the invention opens up the possibility of linking the production of the additional adjustment layer with the provision of additional functions or passive and reactive components on the chip. This outsourcing of passive or reactive components to external ones
  • Layers also save space on the semiconductor material required for active structures.
  • the structures required for the additional functions can be formed from the conductive layers by chemical etching.
  • the invention is particularly suitable for the production of capacitances for stabilizing the internal voltage supply of integrated semiconductor circuits. Also for the adjustment of circuit input capacities required by external capacitors. Special functions, such as electromagnetic shielding or protection against spying on the circuit or data, or additional components, such as coils, ca Capacities or resistances can be implemented in a separate electrically highly conductive layer.
  • a varnish which is surface-activated in a certain length range of the light at the points of the exposure, whereby preferably copper can be chemically deposited at these points.
  • the structuring is carried out, for example, using photo plot masks (CAD / CAM photo mask plotters) that can be created quickly and inexpensively, or without a mask using direct exposure via an NC / CNC (numerically) controlled laser / UV light exposure.
  • the dimensioning of the external metal layer that is, primarily its size and thickness, can be mapped online individually on the surface of the IC or the wafer in accordance with the IC characteristic found in the electrical measurement.
  • the metal layer thicknesses can be varied on the basis of the deposition quantity, preferably in a chemical Cu bath or galvanically individually.
  • a further process variant consists in the application of an electrically conductive ink, which by means of a
  • NC / CNC-controlled ink-jet heads can be deposited on the surface of the IC's / wafer according to their structure and individually according to the electrical property to be adjusted later. The variations in the layer thicknesses also occur here via the amount of deposition.

Abstract

According to the invention, an individually dimensioned, external conductive layer is applied to the finished circuits, respectively, after testing. The values for a particular electrical characteristic of the circuits, which vary unreliably among the multiple circuits at first after the silicon process, can then be adjusted to a chosen, essentially uniform value. The external layer is dimensioned individually in accordance with the electrical test value established, respectively. This post-adjustment renders redesigning unnecessary.

Description

Beschreibungdescription
Verfahren zur Herstellung eines Halbleiterchips mit nach dem Siliciumprozess einstellbarer elektrischer EigenschaftMethod for producing a semiconductor chip with an electrical property that can be set using the silicon process
Die Erfindung betrifft ein Verfahren zur Herstellung eines Halbleiterchips, bei dem auf einem Silicium- afer eine Vielzahl von gleichartigen integrierten Schaltungen erzeugt wird (Siliciumprozess) , die anschließend auf ihre Funktionsfähig- keit und Eigenschaften getestet werden, und bei dem danach der Silicium- afer m Chips mit je einer integrierten Schaltung zerteilt wird.The invention relates to a method for producing a semiconductor chip, in which a multiplicity of integrated circuits of the same type are produced on a silicon afer (silicon process), which are subsequently tested for their functionality and properties, and in which the silicon afer m Chips with an integrated circuit is divided.
Die auf einem Silicium-Wafer mit den Methoden der Halbleiter- technologie hergestellten Strukturen bilden bekanntlich elektronische Bauelemente, deren Kooperation die Funktionalität des Halbleiterchips festlegt . Die Strukturen selbst werden üblicherweise unter Verwendung von Masken fototechnisch auf die jeweils ältere Schicht auf dem Halbleiterchip aufge- bracht. Die beabsichtigte Funktion des Halbleiterchips kann aufgrund von Fehlern im Chipdesign oder durch Einflüsse von Prozessparametern während des Herstellungsprozesses beeinträchtigt werden oder über mehrere Lose m der Fertigung schwanken. Liegen hergestellte Halbleiterchips aufgrund der genannten Ursachen außerhalb des gewünschten Funktionsfensters, wird meist ein Teilredesign des Halbleiterchips angestrebt, um bei zukünftigen Losen die Funktion sicherzustellen. Ein Redesign, das beispielsweise geänderte elektrische Eigenschaften fertiger Chips m großem Maßstab, also m a- fer- oder Losgröße, bezweckt, verursacht durch die erforderlichen Änderungen im Siliciumprozess jedoch zum einen hohe Kosten und bedingt außerdem deutliche Verzögerungen bezüglich der Markteinführung.The structures produced on a silicon wafer using the methods of semiconductor technology are known to form electronic components, the cooperation of which determines the functionality of the semiconductor chip. The structures themselves are usually applied to the older layer on the semiconductor chip using phototechnology using masks. The intended function of the semiconductor chip can be impaired due to errors in the chip design or due to influences of process parameters during the manufacturing process or can fluctuate over several lots in the manufacturing process. If semiconductor chips manufactured lie outside the desired functional window due to the causes mentioned, a partial redesign of the semiconductor chip is usually sought in order to ensure the function in future lots. A redesign, for example, which aims to change the electrical properties of finished chips on a large scale, that is to say in batch or lot sizes, causes high costs due to the changes required in the silicon process and also causes significant delays in terms of market launch.
Besonderes Gewicht erhält die genannte Problematik im Zusammenhang mit der Herstellung von Chips für kontaktlose Identifikationssysteme, z. B. Chipkarten mit induktiver Kopplung zwischen Karte und Lesegerät. Zur Übertragung der Betriebsenergie und der Daten wird ein hochfrequentes Magnetfeld verwendet, dessen Frequenz gemäß einer häufig verwendeten Norm bei 13,56 MHz liegt. In der praKtischen Ausführung wird dazu der Induktivität der Chipkartenspule zusätzlich eine Kapazität parallelgeschaltet, so daß ein Parallelschwingkreis entsteht, dessen Resonanzfrequenz der Sendefrequenz des Lesegerätes entspricht. Auf 13,56 MHz reicht hierzu m der Regel bereits die Eingangskapazität des Halbleiterchips selbst aus, während beispielsweise bei 135 kHz noch ein zusätzlicher diskreter Kondensator benötigt wird.The above-mentioned problem in connection with the production of chips for contactless identification systems, for. B. smart cards with inductive coupling between card and reader. A high-frequency magnetic field is used to transmit the operating energy and data, the frequency of which is 13.56 MHz according to a standard that is frequently used. In the practical version, a capacitance is additionally connected in parallel to the inductance of the chip card coil, so that a parallel resonant circuit is formed, the resonance frequency of which corresponds to the transmission frequency of the reading device. At 13.56 MHz, the input capacitance of the semiconductor chip itself is usually sufficient for this, while an additional discrete capacitor is required, for example, at 135 kHz.
Die genannte Emgangskapazitat des Chips entscheidet demnach speziell bei kontaktlosen Chipkarten über den Wirkungsgrad, d.h. über die Verwendbarkeit der gesamten Produktfamilie für den Kunden. Im Unterschied zu den bei den meisten übrigen Schaltungen zulässigen, relativ breiten Kapazitätsbereichen von beispielsweise 5 bis 10 pF benötigen die Chips für kontaktlose Chipkarten einen wesentlich engeren Wertebereich be- züglich der Eingangskapazität, beispielsweise 17,3 pF ±3%. Da die Kapazität stark vom Layout der integrierten Schaltung und auch den Prozessparametern bei der Herstellung abhängt, hat man bezüglich dieser elektrischen Eigenschaft derzeit nur die Wahl, sich mit einer geringen Ausbeute zufriedenzugeben, oder zu versuchen - ohne absolute Ergebnissicherheit - über ein aufwendiges Redesign den gewünschten Wert zu erzielen.The aforementioned receiving capacity of the chip therefore decides on the efficiency, especially in the case of contactless chip cards, i.e. about the usability of the entire product family for the customer. In contrast to the relatively broad capacitance ranges of, for example, 5 to 10 pF that are permissible in most other circuits, the chips for contactless smart cards require a much narrower range of values with regard to the input capacitance, for example 17.3 pF ± 3%. Since the capacity strongly depends on the layout of the integrated circuit and also the process parameters during manufacture, with regard to this electrical property, there is currently only the choice to be satisfied with a low yield, or to try - without absolute certainty of results - with a complex redesign to achieve the desired one To achieve value.
Es ist bekannt, z. B. aus der US 4 857 893, eine monolithische Transponderemheit , also einen Halbleiterchip mit einer auf dem Chip integrierten Antennenspule, herzustellen, indem nach dem Siliciumprozess, aber vor dem Zerteilen metallische Leiterbahnen beziehungsweise eine spulenförmig strukturierte Schicht mit konventionellen Methoden auf dem Wafer, gleichförmig für alle Schaltungen, abgeschieden werden. Diese be- kannten Maßnahmen werden in der genannten Schrift jedoch in keinen funktioneilen oder zeitlichen Zusammenhang mit gewünschten oder getesteten Werten gestellt. In der WO 95/05678 ist ein Verfahren zur Herstellung von Dünnfilminduktivitäten angegeben, die auf einem Halbleiterchip zusammen mit anderen passiven und aktiven Bauelementen integrierbar sind. Als passive Bauelemente sind Widerstände und Kondensatoren angegeben, die auf dem Substrat des Chips als elektrische Leiter integriert sind.It is known e.g. B. from US 4,857,893, to produce a monolithic transponder unit, that is to say a semiconductor chip with an antenna coil integrated on the chip, by using the silicon process, but before dicing, metallic conductor tracks or a coil-shaped layer with conventional methods on the wafer, uniformly for all circuits. However, these known measures are not put into a functional or temporal connection with desired or tested values in the cited document. WO 95/05678 specifies a method for producing thin-film inductors which can be integrated on a semiconductor chip together with other passive and active components. Resistors and capacitors are specified as passive components, which are integrated on the substrate of the chip as electrical conductors.
In der US 5,872,040 ist ein Verfahren zur Herstellung eines Dünnfilmkondensators angegeben, der auf einem Substrat aus einem Polymer oder einer Keramik ausgebildet und auf einen genauen Wert getrimmt werden kann, indem eine der als Kondensatorplatten vorgesehenen Metallschichten nachbearbeitet wird. In Figur 8 dieser Schrift ist eine Anordnung beschrieben, bei der ein Chip mit einer integrierten Schaltung in ei- ner Aussparung eines Substrates aus Aluminium oder Kunststoff eingesetzt ist und mit einem gemäß dem angegebenen Verfahren genau justierten elektrischen Widerstand verbunden ist, der an der Oberseite des Substrates aufgebracht ist.No. 5,872,040 describes a method for producing a thin-film capacitor which can be formed on a substrate made of a polymer or a ceramic and can be trimmed to an exact value by reworking one of the metal layers provided as capacitor plates. FIG. 8 of this document describes an arrangement in which a chip with an integrated circuit is inserted in a recess in a substrate made of aluminum or plastic and is connected to an electrical resistor which is precisely adjusted according to the specified method and which is located on the top of the Substrate is applied.
In der WO 97/21118 ist ein kontaktloser Transponder mit einer gedruckten Spulenantenne beschrieben, bei dem eine Leiterstruktur als Kondensator zum Abstimmen der Resonanzfrequenz aufgebracht ist. Es wird darauf hingewiesen, dass eine Änderung der Frequenz einfach durch eine Änderung der Struktur oder Dicke der Leiterbahn vorgenommen werden kann und damit ein schneller Fertigungsprozess möglich ist.WO 97/21118 describes a contactless transponder with a printed coil antenna, in which a conductor structure is applied as a capacitor for tuning the resonance frequency. It is pointed out that a change in the frequency can be made simply by changing the structure or thickness of the conductor track and thus a fast manufacturing process is possible.
In der JP 08-107040 A ist eine elektronische Komponente als Bandpassfilter beschrieben, bei der ein durch zwei Leiter- platten gebildeter Kondensator vorhanden ist und die Frequenz durch Trimmen einer Kondensatorelektrode abgestimmt wird.JP 08-107040 A describes an electronic component as a bandpass filter, in which there is a capacitor formed by two printed circuit boards and the frequency is tuned by trimming a capacitor electrode.
In der US 4,560,445 ist ein Verfahren zur Herstellung metallischer Strukturen auf einem Dünnfilmsubstrat beschrieben, bei dem eine strukturierte Kupferschicht mittels galvanischer Abscheidung auf eine elektrisch leitfähige Struktur hergestellt wird. Ziel der vorliegenden Erfindung ist es, ein Verfahren der eingangs genannten Art anzugeben, mit dem die elektrischen Eigenschaften, insbesondere die Eingangskapazität, von Halbleiterchips ohne Redesign in großem Maßstab und kostengünstig beeinflußbar sind.US Pat. No. 4,560,445 describes a method for producing metallic structures on a thin film substrate, in which a structured copper layer is produced on an electrically conductive structure by means of electrodeposition. The aim of the present invention is to provide a method of the type mentioned at the outset with which the electrical properties, in particular the input capacitance, of semiconductor chips can be influenced on a large scale and inexpensively without redesign.
Erfindungsgemäß wird dieses Ziel bei einem Verfahren der eingangs genannten Art dadurch erreicht, daß auf die integrierten Schaltungen jeweils eine indi- viduell dimensionierte, externe leitende Schicht aufgebracht wird, so daß die nach dem Siliciumprozess innerhalb der Vielzahl der integrierten Schaltungen zunächst unzulässig variierenden Werte einer bestimmten elektrischen Eigen- schaft der Schaltungen auf einen gewünschten, im wesentlichen einheitlichen Wert eingestellt werden, wobei die individuelle Dimensionierung der externen Schicht jeder integrierten Schaltung in Abhängigkeit von der beim Testen jeweils festgestellten individuellen Ab- weichung des gemessenen vom gewünschten Wert der elektrischen Eigenschaft erfolgt .According to the invention, this aim is achieved in a method of the type mentioned at the outset in that an individually dimensioned, external conductive layer is applied to the integrated circuits, so that the values of a certain initially inadmissibly varying within the large number of integrated circuits after the silicon process electrical properties of the circuits are set to a desired, essentially uniform value, the individual dimensioning of the external layer of each integrated circuit taking place as a function of the individual deviation of the measured value from the desired value of the electrical property determined during testing.
Der Erfindung liegt die Idee zugrunde, die Chipeigenschaften nachträglich, also nach Siliciumprozess und Test, nicht mit- tels Redesign, sondern bei den bereits vorliegenden Halbleiterbausteinen, durch Aufbringen einer leitenden Schicht für jeden Chip individuell zu justieren. Das Aufbringen der leitenden Schichten, beispielsweise aus Kupfer, erfolgt dabei bevorzugt chemisch additiv auf die einzelnen Schaltungen des Wafers . Diese Variante, bei der die Strukturierung (Belichtung) der Schicht individuell, die Beschichtung der Schaltungen aber in einem gemeinsamen Abscheidebad, also gleichzeitig, erfolgt, ist besonders wirtschaftlich. Prinzipiell kann das Aufbringen jedoch auch einzeln auf die fertigen, durch Sägen des Wafers erhaltenen Halbleiterchips erfolgen. Generell kommen außer chemischen auch physikalische Abscheideverfahren, wie Sputtern, in Frage. Es können auch mehrere Schichten übereinander angeordnet werden, die zusammen, bzw. zusammen mit der jeweiligen Schaltung, den gewünschten elektrischen Wert ergeben. Die Schichten werden untereinander und gegen den Halbleiterchip durch nichtleitende Schichten iso- liert.The invention is based on the idea of subsequently adjusting the chip properties, that is to say after the silicon process and test, not by means of redesign, but in the case of the semiconductor modules already present, by applying a conductive layer for each chip. The application of the conductive layers, for example of copper, is preferably carried out chemically additively to the individual circuits of the wafer. This variant, in which the layer is structured (exposed) individually, but the circuits are coated in a common deposition bath, i.e. simultaneously, is particularly economical. In principle, however, the application can also be carried out individually on the finished semiconductor chips obtained by sawing the wafer. In addition to chemical, physical deposition processes such as sputtering are also generally suitable. You can also have several Layers are arranged one above the other, which together, or together with the respective circuit, give the desired electrical value. The layers are insulated from one another and from the semiconductor chip by non-conductive layers.
Das Aufbringen der externen Schicht kann somit kostengünstig und schnell nach dem Siliciumprozess erfolgen. Eine Änderung der elektrischen Eigenschaften der fertigen Schaltung ist da- durch problemlos möglich. Die Kapazität der integriertenThe external layer can thus be applied inexpensively and quickly after the silicon process. This makes it easy to change the electrical properties of the finished circuit. The capacity of the integrated
Schaltung, insbesondere die Eingangskapazität eines Halbleiterchips für eine kontaktlose Chipkarte, kann erfindungsgemäß nach dem Siliciumprozess an einen gewünschten Wert angepasst werden .Circuit, in particular the input capacitance of a semiconductor chip for a contactless chip card, can be adapted to a desired value according to the invention after the silicon process.
Die Ermittlung der Abweichung der individuellen Werte der Schaltungen bedingt keinen besonderen Aufwand, da die Datenbasis hierzu, also die Messung der tatsächlichen individuellen Werte der Schaltungen, im Rahmen der fertigungsüblichen Tests ohnehin ermittelt wird. Die Erfindung eröffnet über die nachträgliche individuelle Anpassung hinaus die Möglichkeit, die Herstellung der zusätzlichen Justierschicht mit der Bereitstellung von zusätzlichen Funktionen bzw. passiven und reaktiven Bauelementen auf dem Chip zu verknüpfen. Dieses Auslagern passiver oder reaktiver Bauteile auf externeThe determination of the deviation of the individual values of the circuits does not require any special effort, since the database for this, that is to say the measurement of the actual individual values of the circuits, is anyway determined in the course of the tests customary in production. In addition to the subsequent individual adaptation, the invention opens up the possibility of linking the production of the additional adjustment layer with the provision of additional functions or passive and reactive components on the chip. This outsourcing of passive or reactive components to external ones
Schichten spart im übrigen Platz auf dem für aktive Strukturen benötigten Halbleitermaterial. Durch chemisches Ätzen können die für die Zusatzfunktionen erforderlichen Strukturen aus den leitfähigen Schichten ausgebildet werden.Layers also save space on the semiconductor material required for active structures. The structures required for the additional functions can be formed from the conductive layers by chemical etching.
Die Erfindung ist besonders geeignet für die Herstellung von Kapazitäten zur Stabilisierung der internen Spannungsversorgung integrierter Halbleiterschaltungen. Außerdem für den Abgleich erforderlicher Schaltungs-Eingangskapazitäten durch externe Kondensatoren. Spezielle Funktionen, wie elektromagnetische Schirmung oder Schutz gegen Ausspähen der Schaltung oder von Daten, oder zusätzliche Bauelemente, wie Spulen, Ka- pazitäten oder Widerstände können in einer eigenen elektrisch gut leitfähigen Schicht realisiert werden.The invention is particularly suitable for the production of capacitances for stabilizing the internal voltage supply of integrated semiconductor circuits. Also for the adjustment of circuit input capacities required by external capacitors. Special functions, such as electromagnetic shielding or protection against spying on the circuit or data, or additional components, such as coils, ca Capacities or resistances can be implemented in a separate electrically highly conductive layer.
Vorteilhafte Ausgestaltungen sind den Unteransprüchen zu ent- nehmen .Advantageous configurations can be found in the subclaims.
Im Folgenden werden Ausführungsbeispiele der Erfindung beschrieben.Exemplary embodiments of the invention are described below.
Vorteilhaft können folgende Verfahren zur Erzeugung der externen Schichten eingesetzt werden:The following methods can advantageously be used to produce the external layers:
Aufbringung eines Lackes (Dielektrikum) , welcher in einem bestimmten Längenbereich des Lichtes, an den Stellen der Be- lichtung oberflächenaktiviert wird, wodurch an diesen Stellen vorzugsweise Kupfer chemisch abgeschieden werden kann. Die Strukturierung erfolgt dabei beispielsweise über schnell- und kostengünstig erstellbare Fotoplotmasken (CAD/CAM Fotomasken- plotter) oder maskenlos über eine direkte Belichtung über ei- ne NC/CNC (numerisch) gesteuerte Laser/UV-Licht-Belichtung. Die Dimensionierung der externen Metallschicht, also primär ihrer Größe und Dicke, kann online individuell entsprechend der in der elektrischen Messung gefundenen IC-Charakteristik auf der Oberfläche des IC 's beziehungsweise des Wafers abge- bildet werden. Die Metallschichtdicken können anhand der Ab- scheidungsmenge vorzugsweise im chemischen Cu-Bad oder galvanisch individuell variiert werden.Application of a varnish (dielectric), which is surface-activated in a certain length range of the light at the points of the exposure, whereby preferably copper can be chemically deposited at these points. The structuring is carried out, for example, using photo plot masks (CAD / CAM photo mask plotters) that can be created quickly and inexpensively, or without a mask using direct exposure via an NC / CNC (numerically) controlled laser / UV light exposure. The dimensioning of the external metal layer, that is, primarily its size and thickness, can be mapped online individually on the surface of the IC or the wafer in accordance with the IC characteristic found in the electrical measurement. The metal layer thicknesses can be varied on the basis of the deposition quantity, preferably in a chemical Cu bath or galvanically individually.
Eine weitere Verfahrensvariante besteht in der Aufbringung einer elektrisch leitfähigen Tinte, welche mittels einesA further process variant consists in the application of an electrically conductive ink, which by means of a
NC/CNC gesteuerten Ink-Jet -Kopfes strukturgenau und individuell entsprechend der nachträglich zu justierenden elektrischen Eigenschaft auf der Oberfläche des IC's/Wafers abgeschieden werden kann. Die Variationen der Schichtdicken er- folgen auch hierbei über die Abscheidungsmenge . NC / CNC-controlled ink-jet heads can be deposited on the surface of the IC's / wafer according to their structure and individually according to the electrical property to be adjusted later. The variations in the layer thicknesses also occur here via the amount of deposition.

Claims

Patentansprüche claims
1. Verfahren zur Herstellung von Halbleiterchips mit einer integrierten Schaltung, bei dem eine Vielzahl von gleichartigen integrierten Schaltungen auf einem Wafer hergestellt wird und zu jeder Schaltung eine strukturierte, elektrisch leitende Schicht als elektrische Kapazität aufgebracht wird, d a d u r c h g e k e n n z e i c h n e t, dass zu jeder Schaltung ein Wert einer bestimmten Kapazität der Schaltung bestimmt wird und die elektrisch leitende Schicht jeweils so auf einem Halbleiterchip des Wafers hergestellt wird, dass der Wert dieser bestimmten Kapazität für alle Schaltungen des Wafers an einen vorgegebenen Wert angepasst wird.1. A method for producing semiconductor chips with an integrated circuit, in which a multiplicity of integrated circuits of the same type are produced on a wafer and a structured, electrically conductive layer is applied as an electrical capacitance to each circuit, characterized in that a value of one for each circuit determined capacity of the circuit is determined and the electrically conductive layer is in each case produced on a semiconductor chip of the wafer in such a way that the value of this specific capacitance is adapted to a predetermined value for all circuits of the wafer.
2. Verfahren nach Anspruch 1, bei dem2. The method according to claim 1, wherein
Strukturen der elektrisch leitenden Schichten für jede auf dem Wafer vorhandene Schaltung individuell festgelegt werden und die Schichten danach gemeinsam entsprechend den vorgesehenen Strukturen aufgebracht werden.Structures of the electrically conductive layers are individually defined for each circuit present on the wafer and the layers are then applied together in accordance with the structures provided.
3. Verfahren nach Anspruch 2 , bei dem zur Herstellung der elektrisch leitenden Schicht ein dielek- trischer Lack aufgebracht und durch Belichtung zu oberflächenaktivierten Bereichen strukturiert wird und eine Metall- schicht auf diese Bereiche abgeschieden wird.3. The method according to claim 2, in which a dielectric lacquer is applied to produce the electrically conductive layer and is structured by exposure to surface-activated areas, and a metal layer is deposited on these areas.
4. Verfahren nach Anspruch 3, bei dem die Strukturierung mittels Fotoplotmasken erfolgt.4. The method according to claim 3, wherein the structuring takes place by means of photoplot masks.
5. Verfahren nach Anspruch 3, bei dem die Strukturierung über eine direkte Belichtung mittels einer elektronisch gesteuerten Laser- oder UV-Lichtquelle erfolgt.5. The method according to claim 3, wherein the structuring is carried out via direct exposure by means of an electronically controlled laser or UV light source.
6. Verfahren nach Anspruch 2, bei dem zur Herstellung der elektrisch leitenden Schicht eine elek- trisch leitfähige Tinte mittels eines elektronisch gesteuerten Ink-Jet-Kopfes strukturgenau aufgebracht wird.6. The method according to claim 2, in which an elec- trically conductive ink is applied using an electronically controlled ink jet head.
7. Verfahren nach einem der Ansprüche 1 bis 6, bei dem die Eingangskapazität einer für eine kontaktlose Chipkarte vorgesehenen Schaltung als die bestimmte Kapazität an einen vorgegebenen Wert angepasst wird.7. The method according to any one of claims 1 to 6, wherein the input capacitance of a circuit provided for a contactless chip card is adapted as the determined capacitance to a predetermined value.
8. Verfahren nach einem der Ansprüche 1 bis 7, bei dem mit dem Aufbringen der elektrisch leitenden Schicht die Kapazität und gleichzeitig mindestens ein weiteres passives Bauelement ausgebildet werden. 8. The method according to any one of claims 1 to 7, in which, with the application of the electrically conductive layer, the capacitance and at the same time at least one further passive component are formed.
PCT/DE2000/002899 1999-08-26 2000-08-24 Method for producing a semiconductor chip with an electrical property that can be adjusted after the silicon process WO2001015217A2 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4666735A (en) * 1983-04-15 1987-05-19 Polyonics Corporation Process for producing product having patterned metal layer
WO1997021118A1 (en) * 1995-12-05 1997-06-12 Michel Bisson Contactless electronic transponder with printed loop antenna circuit
US5872040A (en) * 1994-12-05 1999-02-16 General Electric Company Method for fabricating a thin film capacitor

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4560445A (en) * 1984-12-24 1985-12-24 Polyonics Corporation Continuous process for fabricating metallic patterns on a thin film substrate
US4857893A (en) * 1986-07-18 1989-08-15 Bi Inc. Single chip transponder device
US5370766A (en) * 1993-08-16 1994-12-06 California Micro Devices Methods for fabrication of thin film inductors, inductor networks and integration with other passive and active devices
JP2950201B2 (en) * 1995-06-22 1999-09-20 株式会社村田製作所 Electronic component including parallel resonator of inductor and capacitor and frequency adjustment method thereof
DE19602316C1 (en) * 1996-01-23 1997-06-19 Siemens Ag Device for transmitting data or energy
JP3900593B2 (en) * 1997-05-27 2007-04-04 凸版印刷株式会社 IC card and IC module
JPH11353440A (en) * 1998-06-09 1999-12-24 Kyodo Printing Co Ltd Capacitor and noncontact type ic card
DE19846096A1 (en) * 1998-10-07 2000-04-13 Bayer Ag Preparation of suspensions of ternary oxides for printing inks

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4666735A (en) * 1983-04-15 1987-05-19 Polyonics Corporation Process for producing product having patterned metal layer
US5872040A (en) * 1994-12-05 1999-02-16 General Electric Company Method for fabricating a thin film capacitor
WO1997021118A1 (en) * 1995-12-05 1997-06-12 Michel Bisson Contactless electronic transponder with printed loop antenna circuit

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 03, 31. März 1999 (1999-03-31) -& JP 10 334203 A (TOPPAN PRINTING CO LTD), 18. Dezember 1998 (1998-12-18) *
PATENT ABSTRACTS OF JAPAN vol. 2000, no. 03, 30. März 2000 (2000-03-30) & JP 11 353440 A (KYODO PRINTING CO LTD), 24. Dezember 1999 (1999-12-24) *

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