WO2001013421A1 - Method of simultaneously growing oxide layers with different ticknesses on a semiconductor body using selective implantations of oxygen and nitrogen - Google Patents

Method of simultaneously growing oxide layers with different ticknesses on a semiconductor body using selective implantations of oxygen and nitrogen Download PDF

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Publication number
WO2001013421A1
WO2001013421A1 PCT/US2000/022191 US0022191W WO0113421A1 WO 2001013421 A1 WO2001013421 A1 WO 2001013421A1 US 0022191 W US0022191 W US 0022191W WO 0113421 A1 WO0113421 A1 WO 0113421A1
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Prior art keywords
dose
species
oxide layer
gate oxide
implanted
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PCT/US2000/022191
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French (fr)
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Chuan Lin
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Infineon Technologies North America Corp.
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Publication of WO2001013421A1 publication Critical patent/WO2001013421A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane

Definitions

  • This invention relates to integrated circuits, and more specifically, to MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices having different gate oxide thicknesses on a single semiconductive body (substrate, wafer) , and to methods of forming oxides having different thicknesses on a single wafer.
  • MOSFET Metal Oxide Semiconductor Field Effect Transistor
  • the gate oxide layers are formed by thermal growth on a major surface of the wafer in an oxygen ambient. Further flexibility in device performance or characteristics can be achieved by using triple gate oxide arrays instead of dual gate oxide arrays .
  • the nitrogen implant dose required to reduce the thermally grown oxide thickness from typically approximately 50A to typically approximately 30A is typically in the range equal to approximately lxE14 cm—2 (i.e., 1x10—14 cm—2 ) to 5xE14 cm—2 , depending upon the thermal growth processing parameters .
  • Such nitrogen doses for a dual gate oxide array can be undesirably high from a reliability (useful lifetime) standpoint for certain uses of finished MOSFET devices having certain gate oxide thicknesses. It is believed that such a relatively high dose of implanted nitrogen can significantly damage the substrate or can produce a significant non-uniformity of the distribution of ion dose in the substrate, or can do both.
  • the oxygen implant dose required to increase the grown oxide thickness for dual gate oxide arrays from typically approximately 30A to typically approximately 50A is undesirably high., typically in a range equal to approximately lxlOEl ⁇ cm—2 to 2xlOE16 cm—2.
  • Such a relatively high dose of implanted oxygen can significantly degrade the subsequently thermally grown gate oxide overlying the implanted surface portions and thereby cause gate oxide reliability problems in finished devices unless the processing windows are controlled and maintained within undesirably narrow limits, that limits that are significantly narrower than conventional limits.
  • the present invention provides a process of forming either dual or triple gate oxide MOSFET arrays using conventional tool sets and conventional processes — that is, with conventional processing windows — while maintaining desirable gate oxide reliability.
  • the invention also provides either dual or triple gate oxide MOSFET device arrays, which can be fabricated using conventional tool sets and conventional processes while maintaining desirable gate oxide reliability.
  • a relatively low dose essentially of nitrogen ions is implanted into a first set of surface portions of a major surface of a silicon wafer, and a relatively low dose essentially of oxygen ions is implanted into a second set of surface portions of the major surface of the wafer. All of the surface portions of both sets are mutually spaced apart.
  • the dosages of both the nitrogen and the oxygen ions are adjusted so as to be compatible with the two different gate oxide layer thicknesses that are desired in a subsequent thermal oxide growth step.
  • these oxide layers are thermally grown by simultaneously exposing all surface portions of both sets to an oxidizing ambient, such as an ambient that contains oxygen, whereby first gate oxide layers that grow overlying the first set of surface portions have a smaller thickness than second gate oxide layers that grow overlying the second set of surface portions.
  • an oxidizing ambient such as an ambient that contains oxygen
  • the process of this invention thus desirably magnifies the difference in thickness between the second and first oxide layers In this way, desirably lower implant doses can be used for both of the two species for a prescribed difference in oxide thickness between the first and second sets of oxide layers.
  • gate oxide layers are formed by exposing to the oxidizing ambient not only the first and second sets of surface portions but also a third set of surface portions of the wafer, the third set not having been subjected to any prior implantation of either oxygen or nitrogen species . All of the surface portions of all three sets are mutually spaced apart. Three distinct gate surface portions having mutually different oxide thicknesses result .
  • the use in this invention of both the relatively low dose oxygen and low dose nitrogen implants, while using a single thermal oxidation process to form the gate oxide layers for MOSFET devices provides a method of achieving a desirably wider processing windows for the formation of dual gate oxides for dual gate oxides arrays, or for improving the gate oxide reliability in such arrays, or for both achieving wider processing windows and improving the gate reliability in these arrays .
  • the present invention is directed to first, second, and third semiconductor structures that each comprise a semiconductive oxide layer on a major surface of a semiconductive body with each of the oxide layers having a different thickness and being located on first, second, and third portions of the major surface with the first surface portion containing a first dose of a first implanted species, the second surface portion containing a second dose of a second implanted species, and the third surface portion containing substantially none of the first or the second implanted species .
  • the present invention is directed to first and second semiconductor structures that each comprise a semiconductive oxide layer on a major surface of a semiconductive body with the oxide layers having a different thicknesses and being located on first and second portions of the major surface and with the first surface portion containing a first dose of a first implanted species and the second surface portion containing a second dose of a second implanted species which is different from the first implanted species .
  • the present invention is directed to a method of fabricating at least three oxide layers of different thicknesses on a surface of a semiconductive body.
  • the method comprises the steps of implanting a first species to a first dose into a first portion of the surface of the semiconductive body over which a first oxide layer is to be fabricated; implanting a second species to a second dose into a second portion of the surface of the semiconductive body over which a second oxide layer is to be fabricated; selecting a third portion of the major surface of the wafer not implanted with the first or the second species; and growing first, second, and third oxide layers on the first, second, and third surface portions, respectively, whereby the thicknesses of the first, second, and third oxide layers are mutually different.
  • the present invention is directed to a method of fabricating at least two oxide layers of different thicknesses on a surface of a semiconductive body.
  • the method comprises the steps of implanting a first species to a first dose into a first portion of the surface of the semiconductive body over which a first oxide layer is to be fabricated; implanting a second species to a second dose into a second portion of the surface of the semiconductive body over which a second oxide layer is to be fabricated; and growing first, second, and third oxide layers on the first, second, and third surface portions, respectively, whereby the thicknesses of the first and second oxide layers are different.
  • the FIGURE depicts a triple gate oxide array in cross section, according to a specific embodiment of the invention. Only for the sake of clarity, the FIGURE is not drawn to any scale .
  • three MOSFET devices are integrated in a semiconductive silicon body 5 at a major surface thereof within regions I, II, III.
  • the body 5 is of one conductivity type, for example p-type conductivity, and the drain regions 12a, 12b, 12c and the source regions 14a, 14b, 14c are all of the same, opposite conductivity type, for example, n-type conductivity type.
  • the areas at which these source and drain regions 14a, 14b, 14c and 12a, 12b, 12c, respectively, are formed are defined by various known masking techniques.
  • Gate oxides layers 16a, 16b, 16c are formed over silicon surface portions 26a, 26b, and 26c, respectively, located between the respective source and drain regions 14a, 14b, 14c, and 12a, 12b, 12c corresponding to regions I, II, III, respectively.
  • Gate conducting layers 18a, 18b, 18c are formed in the regions I, II, III, respectively, from a conductive material and are shown contacting a first set of conductive connections 20a, 20b, 20c, respectively.
  • the gate conducting layers 18a, 18b, 18c typically are made of polysilicon doped with phosphorus.
  • Conductive connections 22a, 22b, 22c and 24a, 24b, 24c of the regions I, II, III are shown contacting respective source and drain regions 14a, 14b, 14c and 12a, 12b, 12c to form source and drain contacts, respectively.
  • Surface portion 26a represents a nitrogen implanted area
  • surface portion 26b represents a non- implanted area
  • surface portion 26c represents an oxygen implanted area.
  • the gate oxide layer 16a has a smaller thickness than the gate oxide layer 16c. Workers in the art call the thickness of the gate oxide layer 16b, overlying the non-implanted area 26b, the "nominal thickness". This nominal thickness has an intermediate value between the gate oxide layers 16a and 16c.
  • FIGURE depicts only one set of regions I, II, III, together with only one set of three MOSFET device structures, it should be understood that the body 5 typically supports many more, similar regions each containing a similar set of three MOSFET device structures. Hence, typically many more, similar sets of three MOSFET devices are integrated in the body 5, to form an array of such structures.
  • Each of these MOSFET device structures can be formed using either a self-aligned process or a non-self-aligned process with respect to the gate. Structures using either of these processes can benefit from the improved method of forming the gate oxides in accordance with the present invention.
  • the present invention is directed to a method for controlling the gate oxide thicknesses either in the two regions I and III or in the three regions I, II, III, while improving device reliability.
  • the gate oxide thickness is typically equal to approximately 30A.
  • the gate oxide thickness is typically equal to approximately 5 ⁇ A.
  • Gate oxide thickness for the gate oxide layer 16b, if any, in the region II is typically equal to approximately 40A; that is to say, the nominal thickness is approximately equal to this 4 ⁇ A.
  • a relatively low dose of nitrogen ions is implanted into the surface portion 26a to produce a relatively low implanted nitrogen concentration equal to approximately lxlOE14 cm—2, and a relatively low dose of oxygen ions is implanted into the surface portion 26c to produce a relatively low implanted oxygen concentration equal to approximately 5xlOE15 cm—2.
  • the oxide layers 16a, 16b, 16c are grown simultaneously to their respectively different thicknesses by means of using a well known thermal oxidation process.
  • the respective oxide thicknesses are easily controlled by controlling the time and temperature of the process in an oxidizing ambient. In the absence of any implant of either nitrogen or oxygen, the thickness of the oxide layer is typically equal to approximately 4 ⁇ A.
  • the thickness of the oxide layer 2 ⁇ b (the nominal thickness) , if any is present in the finished integrated circuit, is typically equal to this 4 ⁇ A. It should be understood that in the case of the dual oxide structures, the oxide layer 26b together with its corresponding MOSFET can be absent from the integrated circuit . It should further be understood, however, that for such purposes as monitoring the growth of the oxide layers 26a and 26c the oxide layer 26b can be present in the finished integrated circuit even though no transistor having this nominal gate oxide thickness is present in the circuit.
  • the thicker oxide layer would be grown as the non- implanted, nominal oxide layer with a thickness equal to approximately 5 ⁇ A, and the nitrogen implant dose would have to be equal to approximately 5xlOE14 cm—2. This value of nitrogen implant dose is thus approximately five time more than the lxlOE14 cm—2 needed in this invention.
  • the thinner oxide layer would be grown as the non- implanted, nominal oxide layer with a thickness equal to approximately 30 A, and the oxygen implant dose would be have to be equal to approximately lxlOE16 cm—2.
  • This value of oxygen does is thus approximately five time more than the 5E15 cm—2 needed in this invention.
  • the invention provides for desirably smaller implant dose.
  • thickness control of the gate oxide layers having mutually different thicknesses is easily achieved because thickness control of the gate oxide layer 16b overlying the non-implanted surface portion 26b is attainable when using a known thermal oxidation step, and because thickness control of the gate oxide layers 16a and 16c overlying the implanted nitrogen and implanted oxide surface portions 26a and 26c, respectively, is attainable simultaneously with the growth of the oxide layer 16b overlying the non-implanted silicon located in the region II.
  • a useful approximate range of the nitrogen ion implant dose is lxE12 cm—2 to 2xE14 cm—2 ; a useful approximate range of the oxygen ion implant dose is lxE14 cm—2 to lxEl ⁇ cm—2.
  • a preferred approximate range of the nitrogen ion implant dose is 5xE12 cm—2 to lxE14 cm—2 ; a preferred approximate range of the oxygen ion implant dose is 5xE14 cm—2 to 5xEl5 cm—2.

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Abstract

A method for controlling gate oxide thicknesses in either dual or triple gate oxide arrays uses ion implantation of both relatively low doses of oxygen into some portions and relatively low doses of nitrogen into other portions of the surface of a silicon wafer. Gate oxide layers are all thermally grown simultaneously. For dual gate oxide arrays the method produces thick and thin gate oxide layers, respectively, during a single thermal growth step, with resulting wider processing windows and better device reliability. An intermediate oxide thickness, useful for triple gate oxide arrays, can be thermally grown in the non-implanted portions of the major surface simultaneously with the growth of all other oxide layers.

Description

METHOD OF SIMULTANEOUSLY GROWING OXIDE LAYERS WITH DIFFERENT TICKNESSES ON A SEMI¬ CONDUCTOR BODY USING SELECTIVE IMPLANTATIONS OF OXYGEN AND NITROGEN
Field of the Invention
This invention relates to integrated circuits, and more specifically, to MOSFET (Metal Oxide Semiconductor Field Effect Transistor) devices having different gate oxide thicknesses on a single semiconductive body (substrate, wafer) , and to methods of forming oxides having different thicknesses on a single wafer.
Background of the Invention
As technology progresses towards the fabrication of complex systems integrated on a single semiconductive silicon chip cut from a silicon wafer, circuit designers are looking for more flexibility in processing semiconductive silicon wafers, each wafer serving as a substrate for many such chips. Existing art includes MOSFET devices integrated on a single wafer. Some of the devices have one gate oxide layer thickness and some have another gate oxide layer thickness ("dual gate oxide MOSFET arrays") . In this way, the circuit designer obtains an array of transistor devices having a desired difference in transistor characteristics or performance of one set of the devices with respected to another set of the devices.
In these arrays, the gate oxide layers are formed by thermal growth on a major surface of the wafer in an oxygen ambient. Further flexibility in device performance or characteristics can be achieved by using triple gate oxide arrays instead of dual gate oxide arrays .
Traditionally, dual gate oxide MOSFET arrays have been fabricated by using the "etching back" method, which is costly because of the need for extra masks. Also, in fabricating the dual oxide array according to the traditional method, the gate oxide regions on the wafer corresponding to the thicker oxide are coated by a photoresist layer before a second gate oxide growth step. This fabrication procedure tends to degrade the gate oxide reliability because of the resulting need to clean the surfaces both of the oxide that had been coated with the resist during the etch-back step and of bare silicon which had been rendered bare by the etch-back step. In the triple oxide case, costs and reliability problems correspondingly multiply.
Also, in prior art for fabricating gate oxides for MOSFET devices, nitrogen implantation into selected regions of major surfaces of silicon wafers (selected "surface portions") has been used for dual gate oxide layer formation to overcome some of the disadvantages of the "etching back" method. More specifically, the nitrogen implantation decreases the thermal growth rate of overlying gate oxide layers. Consequently, the oxide layers grow more slowly in regions overlying nitrogen- implanted surface portions of the silicon wafer than they grow in regions overlying non- implanted surface portions. Hence the resulting grown oxide layers are thinner at areas overlying the nitrogen implanted surface portions than they are at areas overlying the non implanted surface portions.
It is known in the art, however, that the nitrogen implant dose required to reduce the thermally grown oxide thickness from typically approximately 50A to typically approximately 30A is typically in the range equal to approximately lxE14 cm—2 (i.e., 1x10—14 cm—2 ) to 5xE14 cm—2 , depending upon the thermal growth processing parameters . Such nitrogen doses for a dual gate oxide array can be undesirably high from a reliability (useful lifetime) standpoint for certain uses of finished MOSFET devices having certain gate oxide thicknesses. It is believed that such a relatively high dose of implanted nitrogen can significantly damage the substrate or can produce a significant non-uniformity of the distribution of ion dose in the substrate, or can do both. Hence such a relatively high dose of implanted nitrogen can significantly degrade the subsequently thermally grown gate oxide overlying the implanted surface portions, and thereby cause gate oxide reliability problems in finished products. Whatever the theory may be, the fact remains that the nitrogen ion dose required in prior art, to produce a specified dual gate oxide thickness difference between thicker and thinner gate oxide layers, results in a reliability of finished devices that can be less than desired. Conversely, for a specified reliability of finished devices, the processing window is undesirably narrow. Instead of nitrogen implants, oxygen implants have been used to increase the rate of oxide growth of dual gate oxides for MOSFET devices. In this case, the oxide growth is faster at the oxygen implanted surface portions than at the non- implanted surface portions. Hence resulting grown oxide is thicker at the oxygen-implanted surface portions than at the non implanted surface portions.
It is known in the art, however, that the oxygen implant dose required to increase the grown oxide thickness for dual gate oxide arrays from typically approximately 30A to typically approximately 50A is undesirably high., typically in a range equal to approximately lxlOElβ cm—2 to 2xlOE16 cm—2. Such a relatively high dose of implanted oxygen can significantly degrade the subsequently thermally grown gate oxide overlying the implanted surface portions and thereby cause gate oxide reliability problems in finished devices unless the processing windows are controlled and maintained within undesirably narrow limits, that limits that are significantly narrower than conventional limits.
Summary of the Invention
The present invention provides a process of forming either dual or triple gate oxide MOSFET arrays using conventional tool sets and conventional processes — that is, with conventional processing windows — while maintaining desirable gate oxide reliability. The invention also provides either dual or triple gate oxide MOSFET device arrays, which can be fabricated using conventional tool sets and conventional processes while maintaining desirable gate oxide reliability.
To this end, in one specific embodiment, for fabricating dual gate oxide arrays, a relatively low dose essentially of nitrogen ions is implanted into a first set of surface portions of a major surface of a silicon wafer, and a relatively low dose essentially of oxygen ions is implanted into a second set of surface portions of the major surface of the wafer. All of the surface portions of both sets are mutually spaced apart. The dosages of both the nitrogen and the oxygen ions are adjusted so as to be compatible with the two different gate oxide layer thicknesses that are desired in a subsequent thermal oxide growth step. Then these oxide layers are thermally grown by simultaneously exposing all surface portions of both sets to an oxidizing ambient, such as an ambient that contains oxygen, whereby first gate oxide layers that grow overlying the first set of surface portions have a smaller thickness than second gate oxide layers that grow overlying the second set of surface portions.
Since the nitrogen implant species decreases the oxide growth rate and the oxygen implant species increases the oxide growth rate, the process of this invention thus desirably magnifies the difference in thickness between the second and first oxide layers In this way, desirably lower implant doses can be used for both of the two species for a prescribed difference in oxide thickness between the first and second sets of oxide layers.
In another specific embodiment, for triple gate oxide arrays, gate oxide layers are formed by exposing to the oxidizing ambient not only the first and second sets of surface portions but also a third set of surface portions of the wafer, the third set not having been subjected to any prior implantation of either oxygen or nitrogen species . All of the surface portions of all three sets are mutually spaced apart. Three distinct gate surface portions having mutually different oxide thicknesses result .
The use in this invention of both the relatively low dose oxygen and low dose nitrogen implants, while using a single thermal oxidation process to form the gate oxide layers for MOSFET devices, provides a method of achieving a desirably wider processing windows for the formation of dual gate oxides for dual gate oxides arrays, or for improving the gate oxide reliability in such arrays, or for both achieving wider processing windows and improving the gate reliability in these arrays .
In brief, experimental evidence exists showing that implantation doses that are relatively high can result in subsequent gate oxide reliability problems, or in undesirably narrow processing windows, or in both such reliability problems and narrow processing windows. Structures fabricated in accordance with this invention employ relatively low implant doses of both nitrogen and oxygen species, thereby providing the desired thicknesses for the dual or triple gate oxides without resulting in significant gate oxide reliability problems, or in undesirably narrow processing windows, or in both such reliability problems and narrow processing windows.
Viewed from a first apparatus aspect, the present invention is directed to first, second, and third semiconductor structures that each comprise a semiconductive oxide layer on a major surface of a semiconductive body with each of the oxide layers having a different thickness and being located on first, second, and third portions of the major surface with the first surface portion containing a first dose of a first implanted species, the second surface portion containing a second dose of a second implanted species, and the third surface portion containing substantially none of the first or the second implanted species .
Viewed from a second apparatus aspect, the present invention is directed to first and second semiconductor structures that each comprise a semiconductive oxide layer on a major surface of a semiconductive body with the oxide layers having a different thicknesses and being located on first and second portions of the major surface and with the first surface portion containing a first dose of a first implanted species and the second surface portion containing a second dose of a second implanted species which is different from the first implanted species . Viewed from a first method aspect, the present invention is directed to a method of fabricating at least three oxide layers of different thicknesses on a surface of a semiconductive body. The method comprises the steps of implanting a first species to a first dose into a first portion of the surface of the semiconductive body over which a first oxide layer is to be fabricated; implanting a second species to a second dose into a second portion of the surface of the semiconductive body over which a second oxide layer is to be fabricated; selecting a third portion of the major surface of the wafer not implanted with the first or the second species; and growing first, second, and third oxide layers on the first, second, and third surface portions, respectively, whereby the thicknesses of the first, second, and third oxide layers are mutually different.
Viewed from a second method aspect, the present invention is directed to a method of fabricating at least two oxide layers of different thicknesses on a surface of a semiconductive body. The method comprises the steps of implanting a first species to a first dose into a first portion of the surface of the semiconductive body over which a first oxide layer is to be fabricated; implanting a second species to a second dose into a second portion of the surface of the semiconductive body over which a second oxide layer is to be fabricated; and growing first, second, and third oxide layers on the first, second, and third surface portions, respectively, whereby the thicknesses of the first and second oxide layers are different.
The invention may be more fully understood from the following detailed description, accompanying drawings, and claims .
Brief Description of the Drawing
The FIGURE depicts a triple gate oxide array in cross section, according to a specific embodiment of the invention. Only for the sake of clarity, the FIGURE is not drawn to any scale .
Detailed Description
As shown in the FIGURE, three MOSFET devices are integrated in a semiconductive silicon body 5 at a major surface thereof within regions I, II, III. The body 5 is of one conductivity type, for example p-type conductivity, and the drain regions 12a, 12b, 12c and the source regions 14a, 14b, 14c are all of the same, opposite conductivity type, for example, n-type conductivity type. The areas at which these source and drain regions 14a, 14b, 14c and 12a, 12b, 12c, respectively, are formed are defined by various known masking techniques. Gate oxides layers 16a, 16b, 16c are formed over silicon surface portions 26a, 26b, and 26c, respectively, located between the respective source and drain regions 14a, 14b, 14c, and 12a, 12b, 12c corresponding to regions I, II, III, respectively. Gate conducting layers 18a, 18b, 18c are formed in the regions I, II, III, respectively, from a conductive material and are shown contacting a first set of conductive connections 20a, 20b, 20c, respectively. The gate conducting layers 18a, 18b, 18c typically are made of polysilicon doped with phosphorus. Conductive connections 22a, 22b, 22c and 24a, 24b, 24c of the regions I, II, III are shown contacting respective source and drain regions 14a, 14b, 14c and 12a, 12b, 12c to form source and drain contacts, respectively. Surface portion 26a represents a nitrogen implanted area; surface portion 26b represents a non- implanted area, and surface portion 26c represents an oxygen implanted area. Thus the gate oxide layer 16a has a smaller thickness than the gate oxide layer 16c. Workers in the art call the thickness of the gate oxide layer 16b, overlying the non-implanted area 26b, the "nominal thickness". This nominal thickness has an intermediate value between the gate oxide layers 16a and 16c.
Although the FIGURE depicts only one set of regions I, II, III, together with only one set of three MOSFET device structures, it should be understood that the body 5 typically supports many more, similar regions each containing a similar set of three MOSFET device structures. Hence, typically many more, similar sets of three MOSFET devices are integrated in the body 5, to form an array of such structures.
Each of these MOSFET device structures can be formed using either a self-aligned process or a non-self-aligned process with respect to the gate. Structures using either of these processes can benefit from the improved method of forming the gate oxides in accordance with the present invention.
As noted above, the present invention is directed to a method for controlling the gate oxide thicknesses either in the two regions I and III or in the three regions I, II, III, while improving device reliability. For the gate oxide layer 16a, the gate oxide thickness is typically equal to approximately 30A. For the gate oxide lβc the gate oxide thickness is typically equal to approximately 5θA. Gate oxide thickness for the gate oxide layer 16b, if any, in the region II is typically equal to approximately 40A; that is to say, the nominal thickness is approximately equal to this 4θA.
Typically, to achieve these gate oxide thicknesses, a relatively low dose of nitrogen ions is implanted into the surface portion 26a to produce a relatively low implanted nitrogen concentration equal to approximately lxlOE14 cm—2, and a relatively low dose of oxygen ions is implanted into the surface portion 26c to produce a relatively low implanted oxygen concentration equal to approximately 5xlOE15 cm—2. Then the oxide layers 16a, 16b, 16c are grown simultaneously to their respectively different thicknesses by means of using a well known thermal oxidation process. The respective oxide thicknesses are easily controlled by controlling the time and temperature of the process in an oxidizing ambient. In the absence of any implant of either nitrogen or oxygen, the thickness of the oxide layer is typically equal to approximately 4θA. Thus the thickness of the oxide layer 2βb (the nominal thickness) , if any is present in the finished integrated circuit, is typically equal to this 4θA. It should be understood that in the case of the dual oxide structures, the oxide layer 26b together with its corresponding MOSFET can be absent from the integrated circuit . It should further be understood, however, that for such purposes as monitoring the growth of the oxide layers 26a and 26c the oxide layer 26b can be present in the finished integrated circuit even though no transistor having this nominal gate oxide thickness is present in the circuit.
By way of comparison, using only a single implant species of nitrogen as in prior art, to fabricate an array of the dual gate oxide layers 16a and 16c having the above-described thicknesses equal to approximately 3θA and approximately 5θA, respectively, the thicker oxide layer would be grown as the non- implanted, nominal oxide layer with a thickness equal to approximately 5θA, and the nitrogen implant dose would have to be equal to approximately 5xlOE14 cm—2. This value of nitrogen implant dose is thus approximately five time more than the lxlOE14 cm—2 needed in this invention. By way of further comparison, using only a single implant species of oxygen as in prior art, to fabricate an array of the dual gate oxide layers 16a and 16c having the above-described thicknesses equal to approximately 3θA and approximately 5θA, respectively, the thinner oxide layer would be grown as the non- implanted, nominal oxide layer with a thickness equal to approximately 30 A, and the oxygen implant dose would be have to be equal to approximately lxlOE16 cm—2. This value of oxygen does is thus approximately five time more than the 5E15 cm—2 needed in this invention. Thus in either case, the invention provides for desirably smaller implant dose.
In the practice of this invention, thickness control of the gate oxide layers having mutually different thicknesses is easily achieved because thickness control of the gate oxide layer 16b overlying the non-implanted surface portion 26b is attainable when using a known thermal oxidation step, and because thickness control of the gate oxide layers 16a and 16c overlying the implanted nitrogen and implanted oxide surface portions 26a and 26c, respectively, is attainable simultaneously with the growth of the oxide layer 16b overlying the non-implanted silicon located in the region II.
Although the invention has been described in detail with respect to specific embodiments, various modifications can be made without departing from the scope of the invention. For example, species of ions, atoms, or molecules other than of nitrogen or of oxygen may be used.
A useful approximate range of the nitrogen ion implant dose is lxE12 cm—2 to 2xE14 cm—2 ; a useful approximate range of the oxygen ion implant dose is lxE14 cm—2 to lxElβ cm—2. A preferred approximate range of the nitrogen ion implant dose is 5xE12 cm—2 to lxE14 cm—2 ; a preferred approximate range of the oxygen ion implant dose is 5xE14 cm—2 to 5xEl5 cm—2. It should be understood, of course, that the doses of the two implant species for each array depends upon the desired thickness of the nominal oxide layer and the desired thickness differences. Also, the order of sequence of implanting the two species can be reversed. Finally, anneals after the ion implant steps and after the thermal gate oxide growth steps can be performed for such purposes as improving device yield and device performance.

Claims

What is claimed is:
1. A method of fabricating an integrated circuit comprising the steps of:
(a) providing a semiconductive silicon wafer;
(b) implanting a first species to a first dose into a first surface portion of a major surface of the wafer;
(c) implanting a second species to a second dose into a second surface portion of the major surface of the wafer, the first and second surface portions being spaced apart from each other;
(d) selecting a third surface portion of the major surface of the wafer not implanted with the first or the second species, the third surface portion being spaced apart from both the first and the second surface portions; and
(e) simultaneously growing first, second, and third gate oxide layers on the first, second, and third surface portions, respectively, whereby the thicknesses of the first, second, and third gate oxide layers are mutually different.
2. The method of claim 1 in which the first species is essentially nitrogen and the second species is essentially oxygen, whereby the second oxide layer is thicker than the first oxide layer.
3. The method of claim 2 in which the first dose is in the approximate range of 1XE12 cm—2 to 2xE14 cm—2 and in which the second dose is in the approximate range of 1XE14 cm—2 to lxE16 cm-2.
4. The method of claim 2 in which the first dose is in the approximate range of 5xE12 cm—2 to lxE14 cm—2 and in which the second dose is in the approximate range of 5xE14 cm—2 to 5xE15 cm—2.
5. The method of claim 2 in which the first dose is approximately equal to lxE14 cm—2 and in which the second dose is approximately equal to 5xE15 cm—2.
6. First, second, and third MOSFET structures mutually spaced apart and integrated in a semiconductive silicon body at a major surface thereof in respective first, second, and third regions thereof, the first, second, and third regions including respective first, second, and third surface portions of the major surface, the first, second and third structures having first, second, and third gate oxide layers, respectively, that have respective different first, second, and third gate oxide layer thicknesses, overlying said first, second, and third surface portions, respectively, the first surface portion containing a first dose of a first implanted species, the second surface portion containing a second dose of a second implanted species and the third surface portion containing substantially none of the first or the second implanted species.
7. The MOSFET structures of claim 6 in which the first species is essentially nitrogen and the second species is essentially oxygen, whereby the second oxide layer is thicker than the first oxide layer.
8. The MOSFET structures of claim 7 in which the first dose is in the approximate range of lxE12 cm—2 to 2xE14 cm—2 and in which the second dose is in the approximate range of lxE14 cm-2 to lxElβ cm-2.
9. The MOSFET structures of claim 7 in which the first dose is in the approximate range of 5xE12 cm—2 to lxE14 cm—2 and in which the second dose is in the approximate range of 5xE14 cm-2 to 5xE15 cm-2.
10. The MOSFET structures of claim 7 in which the first dose is approximately equal to lxE14 cm—2 and in which the second dose is approximately equal to 5xE15 cm—2.
11. A method of fabricating an integrated circuit comprising the steps of:
(a) providing a semiconductive silicon wafer;
(b) implanting a first species to a first dose into a first surface portion of a major surface of the wafer;
(c) implanting a second species to a second dose into a second surface portion of the major surface of the wafer, the first and second surface portions being spaced apart from each other;
(d) simultaneously growing first and second gate oxide layers on the first and second surface portions, respectively, of the major surface of the wafer, whereby the thicknesses of the first and second gate oxide layers are different .
12. The method of claim 11 in which the first species is essentially nitrogen and the second species is essentially oxygen, whereby the second oxide layer is thicker than the first oxide layer.
13. The method of claim 12 in which the first dose in the approximate range of lxE12 cm—2 to 2xE14 cm—2 and in which the second dose is in the approximate range of lxE14 cm—2 to lxElβ cm-2.
14. The method of claim 12 in which the first dose is in the approximate range of 5xE12 cm—2 to lxE14 cm—2 and in which the second dose is in the approximate range of 5xE14 cm—2 to 5xE15 cm—2.
15. The method of claim 12 in which the first dose is approximately equal to lxE14 cm—2 and in which the second dose is approximately equal to 5xE15 cm—2.
16. First and second MOSFET structures spaced apart and integrated in a semiconductive silicon body at a major surface thereof in respective first and second regions thereof, the first and second regions including respective first and second surface portions of the major surface, the first and second structures having first and second gate oxide layers, respectively, that have respective different first and second gate oxide layer thicknesses, overlying said first and second surface portions, respectively, the first surface portion containing a first dose of a first implanted species and the second surface portion containing a second dose of a second implanted species.
17. The MOSFET structures of claim 16 in which the first implanted species is nitrogen and the second implanted species is oxygen, whereby the second oxide layer is thicker than the first oxide layer.
18. The MOSFET structures of claim 17 in which the first dose in the approximate range of lxE12 cm—2 to 2xE14 cm—2 and in which the second dose is in approximate range of lxE14 cm—2 to lxElβ cm—2.
19. The MOSFET structures of claim 17 in which the first dose is in the approximate range of 5xE12 cm—2 to lxE14 cm—2 and in which the second dose is in the approximate range of 5xE14 cm-2 to 5xEl5 cm-2.
20. The MOSFET structures of claim 17 in which the first dose is approximately equal to lxE14 cm—2 and in which the second dose is approximately equal to 5xEl5 cm—2.
21. First, second, and third semiconductor structures that each comprise a semiconductive oxide layer on a major surface of a semiconductive body with each of the oxide layers having a different thickness and being located on first, second, and third portions of the major surface with the first surface portion containing a first dose of a first implanted species, the second surface portion containing a second dose of a second implanted species, and the third surface portion containing substantially none of the first or the second implanted species .
22. First and second semiconductor structures that each comprise a semiconductive oxide layer on a major surface of a semiconductive body with the oxide layers having a different thicknesses and being located on first and second portions of the major surface and with the first surface portion containing a first dose of a first implanted species and the second surface portion containing a second dose of a second implanted species which is different from the first implanted species .
23. A method of fabricating at least three oxide layers of different thicknesses on a surface of a semiconductive body comprising the steps of: implanting a first species to a first dose into a first portion of the surface of the semiconductive body over which a first oxide layer is to be fabricated; implanting a second species to a second dose into a second portion of the surface of the semiconductive body over which a second oxide layer is to be fabricated; selecting a third portion of the major surface of the wafer not implanted with the first or the second species; and growing first, second, and third oxide layers on the first, second, and third surface portions, respectively, whereby the thicknesses of the first, second, and third oxide layers are mutually different.
24. A method of fabricating at least two oxide layers of different thicknesses on a surface of a semiconductive body comprising the steps of : implanting a first species to a first dose into a first portion of the surface of the semiconductive body over which a first oxide layer is to be fabricated; implanting a second species to a second dose into a second portion of the surface of the semiconductive body over which a second oxide layer is to be fabricated; and growing first, second, and third oxide layers on the first, second, and third surface portions, respectively, whereby the thicknesses of the first and second oxide layers are different .
PCT/US2000/022191 1999-08-18 2000-08-14 Method of simultaneously growing oxide layers with different ticknesses on a semiconductor body using selective implantations of oxygen and nitrogen WO2001013421A1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10213813A1 (en) * 2001-08-28 2003-10-23 Promos Technologies Inc Molecular nitrogen implantation dosage estimation method for integrated circuit manufacture, involves building relation between molecular nitrogen implantation dosage and suppression ratio of oxide layer after thermal process

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3032608A1 (en) * 1979-09-05 1981-03-12 Mitsubishi Denki K.K., Tokyo Semiconductor device prodn. by ion implantation and oxidn. - to give thick and thin oxide films simultaneously on defect and untreated zones
US4471373A (en) * 1980-02-27 1984-09-11 Hitachi, Ltd. Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS
JPH0794503A (en) * 1993-09-24 1995-04-07 Sumitomo Metal Ind Ltd Oxidizing method for silicon substrate
US5863819A (en) * 1995-10-25 1999-01-26 Micron Technology, Inc. Method of fabricating a DRAM access transistor with dual gate oxide technique

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3032608A1 (en) * 1979-09-05 1981-03-12 Mitsubishi Denki K.K., Tokyo Semiconductor device prodn. by ion implantation and oxidn. - to give thick and thin oxide films simultaneously on defect and untreated zones
US4471373A (en) * 1980-02-27 1984-09-11 Hitachi, Ltd. Semiconductor integrated circuit device with memory MISFETS and thin and thick gate insulator MISFETS
JPH0794503A (en) * 1993-09-24 1995-04-07 Sumitomo Metal Ind Ltd Oxidizing method for silicon substrate
US5863819A (en) * 1995-10-25 1999-01-26 Micron Technology, Inc. Method of fabricating a DRAM access transistor with dual gate oxide technique

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
CHEN Y Y ET AL: "PERFORMANCE AND RELIABILITY ASSESSMENT OF DUAL-GATE CMOS DEVICES WITH GATE OXIDE GROWN ON NITROGEN IMPLANTED SI SUBSTRATES", INTERNATIONAL ELECTRON DEVICES MEETING,US,NEW YORK, NY: IEEE, 7 December 1997 (1997-12-07), pages 639 - 642, XP000855877, ISBN: 0-7803-4101-5 *
KING Y -C ET AL: "SUB-5NM MULTIPLE-THICKNESS GATE OXIDE TECHNOLOGY USING OXYGEN IMPLANTATION", SAN FRANCISCO, CA, DEC. 6 - 9, 1998,NEW YORK, NY: IEEE,US, 6 December 1998 (1998-12-06), pages 585 - 588, XP000859441, ISBN: 0-7803-4775-7 *
PATENT ABSTRACTS OF JAPAN vol. 1995, no. 07 31 August 1995 (1995-08-31) *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10213813A1 (en) * 2001-08-28 2003-10-23 Promos Technologies Inc Molecular nitrogen implantation dosage estimation method for integrated circuit manufacture, involves building relation between molecular nitrogen implantation dosage and suppression ratio of oxide layer after thermal process
DE10213813B4 (en) * 2001-08-28 2004-03-18 Promos Technologies, Inc. Procedure for evaluating the stability of an ion implanter

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