WO2001011766A1 - Apparatus and method for phase and frequency digital modulation - Google Patents

Apparatus and method for phase and frequency digital modulation Download PDF

Info

Publication number
WO2001011766A1
WO2001011766A1 PCT/US2000/021016 US0021016W WO0111766A1 WO 2001011766 A1 WO2001011766 A1 WO 2001011766A1 US 0021016 W US0021016 W US 0021016W WO 0111766 A1 WO0111766 A1 WO 0111766A1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
phase
digital
output
generate
Prior art date
Application number
PCT/US2000/021016
Other languages
French (fr)
Inventor
Thad J. Genrich
Original Assignee
Raytheon Company
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Raytheon Company filed Critical Raytheon Company
Priority to AU65096/00A priority Critical patent/AU6509600A/en
Priority to IL14799100A priority patent/IL147991A0/en
Publication of WO2001011766A1 publication Critical patent/WO2001011766A1/en
Priority to NO20020541A priority patent/NO20020541D0/en

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03CMODULATION
    • H03C3/00Angle modulation
    • H03C3/02Details
    • H03C3/09Modifications of modulator for regulating the mean frequency
    • H03C3/0908Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0991Modifications of modulator for regulating the mean frequency using a phase locked loop including calibration means or calibration methods
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03CMODULATION
    • H03C3/00Angle modulation
    • H03C3/02Details
    • H03C3/09Modifications of modulator for regulating the mean frequency
    • H03C3/0908Modifications of modulator for regulating the mean frequency using a phase locked loop
    • H03C3/0966Modifications of modulator for regulating the mean frequency using a phase locked loop modulating the reference clock

Definitions

  • This invention is related in general to signal modulation, and more particularly, to apparatus and method for phase and frequency digital modulation.
  • the typical digital phase and frequency modulator suffers from one or more inherent performance and/or implementation limitations.
  • One conventional approach for digital phase and frequency modulation first generates a relatively low frequency modulated signal using a low to moderate sample rate digital to analog converter
  • DAC digital to analog converter
  • anti-aliasing filter an anti-aliasing filter
  • the resulting signal is then up-converted to the desired output frequency using one or more frequency translation circuits.
  • the disadvantages of this approach are the complexity of the frequency translation circuit implementation using mixers and filters, isolation and bandwidth limitations associated with frequency translation filtering, and the presence of mixing spurious signals at the final output.
  • Another similar conventional implementation generates quadrature low frequency modulated signals using two digital-to-analog converters and anti-aliasing filters with a low to moderate sample rate. These signals are used to control a quadrature modulator, which directly produces the modulated output centered at the frequency of its local oscillator input.
  • This approach provides lower complexity and wider output bandwidth capabilities than the up- conversion approach.
  • the major disadvantage of this approach is that it produces distortions due to amplitude and phase imbalances which are unacceptable in many applications.
  • a third conventional approach uses an undersampling (or bandpass sampling) technique with a digital-to-analog converter with a moderate to high sample rate.
  • the output signal is a sampling image which is a sum or difference of the fundamental digital-to-analog converter output frequency and a harmonic of the sampling frequency.
  • the image is selected from all of the other images present at the digital-to-analog converter output with a bandpass filter.
  • This approach has bandwidth limitations due to the output filtering, and dynamic range (signal-to-noise ratio) limitations of the digital-to-analog converter at output frequencies above its sample rate.
  • a fourth conventional implementation utilizes a very high speed digital-to-analog converter which oversamples the desired output frequency. This approach avoids the frequency conversion and filtering limitations of the other aforementioned implementations. However, spurious signals are present in the output of this implementation due to the limited resolution of the high speed digital-to-analog converter. The high levels of the spurious signals are unacceptable in many applications.
  • the circuitry required to generate the high speed digital-to-analog converter data inputs also generally has much higher complexity and power consumption than the other approaches.
  • apparatus for phase/frequency digital modulation includes a digital circuit receiving and processing a digital modulation input signal to generate a digital modulation control signal, a digital-to-analog converter coupled to the digital circuit operable to convert the digital modulation control signal into an analog modulation control signal, and an RF/analog circuit coupled to the digital-to-analog converter.
  • the RF/analog circuit includes a voltage controlled oscillator operable to generate a modulated output signal in response to the analog modulation control signal, and a quadrature tuner coupled to the voltage controlled oscillator operable to generate an in-phase tuner output and a quadrature tuner output in response to the modulated output signal.
  • An analog-to-digital converter is coupled to the quadrature tuner and operable to convert the in-phase and quadrature tuner outputs to digital in-phase and quadrature tuner outputs.
  • the digital in-phase and quadrature tuner outputs are fed back to the digital circuit to generate the digital modulation control signal.
  • apparatus for phase/frequency digital modulation includes a programmable logic digital circuit receiving a modulation input signal and operable to generate a modulation control signal therefrom, and an RF/analog circuit coupled to the programmable logic digital circuit and receiving the modulation control signal.
  • the RF/analog circuit includes a voltage controlled oscillator operable to generate a modulated output signal in response to the modulation control signal, and a quadrature tuner coupled to the voltage controlled oscillator operable to generate an in- phase tuner output and a quadrature tuner output in response to the modulation control signal.
  • the in-phase and quadrature tuner outputs are fed back to the programmable logic digital circuit to generate the modulation control signal.
  • a method for phase/frequency digital modulation includes the steps of receiving a modulation input signal and at least one feedback signal and generating a modulation control signal therefrom, using the modulation control signal to control a voltage controlled oscillator and generating a modulated output signal, generating an in-phase and a quadrature tuner outputs in response to the modulated output signal, and generating the at least one feedback signal from the in-phase and quadrature tuner outputs.
  • One technical advantage of the invention is that the use of the voltage controlled oscillator and quadrature feedback avoids the problems of frequency translation, digital-to-analog converter spurious and dynamic range, and high speed digital-to-analog converter drive circuitry complexity and power consumption.
  • Another technical advantage of the invention is that identical RF/analog circuits enables the implementation of the digital circuit with programmable logic devices that can be configured.
  • FIGURE 1 is a block diagram of an embodiment of a narrowband phase and frequency digital modulator constructed according to the teachings of the present invention
  • FIGURE 2 is a block diagram of an embodiment of a wideband phase digital modulator constructed according to the teachings of the present invention
  • FIGURE 3 is a block diagram of an embodiment of a wideband frequency digital modulator constructed according to the teachings of the present invention
  • FIGURE 4 is a block diagram of an embodiment of an automatic gain control circuit constructed according to the teachings of the present invention
  • FIGURE 5 is a block diagram of an embodiment of a deviation calibration circuit constructed according to the teachings of the present invention.
  • FIGURE 6 is a flowchart of an embodiment of a method for common phase and/or frequency digital modulation according to the teachings of the present invention
  • FIGURE 7 is a flowchart of an embodiment of a method for processing the modulation input signal for narrowband phase and frequency digital modulation according to the teachings of the present invention
  • FIGURE 8 is a flowchart of an embodiment of a method for processing the modulation input signal for wideband phase digital modulation according to the teachings of the present invention
  • FIGURE 9 is a flowchart of an embodiment of a method for processing the modulation input signal for wideband frequency digital modulation according to the teachings of the present invention
  • FIGURE 10 is a flowchart of an embodiment of a method for automatic gain control loop for phase and frequency digital modulation according to the teachings of the present invention.
  • FIGURE 11 is a flowchart of an embodiment of a method for generating a deviation control output signal for phase and frequency digital modulation according to the teachings of the present invention.
  • FIGURES 1-11 The preferred embodiments of the present invention are illustrated in FIGURES 1-11, where like reference numerals are used to refer to like and corresponding parts or portions of the invention.
  • narrowband phase and frequency modulator 10 (FIGURE 1), wideband phase modulator 70 (FIGURE 2), and wideband frequency modulator 130 (FIGURE 3) each has a digital circuit portion (66, 122, 182) and a common RF/analog circuit portion 68.
  • the common phase or frequency modulator process is shown in FIGURE 6, which begins in block 230.
  • the modulation input signal is first processed in some manner by the digital portion of the modulators, as shown in block 232. Thereafter, the processed signal is used to control a voltage controlled oscillator to generate a modulated output signal, as shown in block 238.
  • An automatic gain control loop or process is then used to generate an output to drive an automatic gain control amplifier receiving the modulated output signal, as shown in block 242.
  • in-phase tuner output and quadrature tuer output are generated from the output of the automatic gain control amplifier.
  • a feedback signal is then generated from the in-phase tuner output and/or the quadrature tuner outputs, as shown in block 246.
  • the process ends in block 248.
  • the process described above is relevant to each of the modulation methods described below.
  • FIGURE 1 A block diagram of an embodiment of a narrowband phase and frequency digital modulator 10 constructed according to the teachings of the present invention is shown in FIGURE 1.
  • FIGURE 7 A flowchart of the exemplary method for narrowband phase and frequency digital modulation, which begins in block 250.
  • a digital frequency modulation input word 12 is processed by supplying it to a phase accumulator 14, which converts input word 12 into a time varying phase representation (block 252) .
  • the output from phase accumulator 14 is summed, by a summer 17, with a digital phase modulation input word 16 to generate a phase reference signal 18 for a modulator phase-locked loop
  • Phase reference signal 18 along with a feedback signal in the form of a phase signal 22 are provided to and received by a summer 19.
  • Summer 19 subtracts phase signal 22 from phase reference signal 18 to form a phase error signal or a modulation control signal 24
  • Loop filter 26 filters modulation control signal 24 (block 257) .
  • the digital portion of the process ends in block 258.
  • the output of loop filter 26 is a filtered modulation control signal coupled to a digital-to-analog converter (DAC) 28 followed by an anti-aliasing or low pass filter 30.
  • the output from filter 30 drives a voltage controlled oscillator (VCO) 32 having a modulated intermediate frequency (IF) or radio frequency (RF) output 34 (FIGURE 6, block 238) .
  • VCO voltage controlled oscillator
  • IF intermediate frequency
  • RF radio frequency
  • modulated output 34 tracks the phase of phase reference signal 18, which is modulated by frequency and phase modulation input words 12 and 16.
  • An automatic gain control (AGC) amplifier 36 coupled to voltage controlled oscillator 32 receives modulated output 34 therefrom and generates an output with an IF/RF output power kept at a constant level (block 242) .
  • Automatic gain control amplifier 36 is driven by an output from a digital-to-analog converter 38 and low pass filter 40 combination that is connected to an output 42 of an automatic gain control loop 200 (block 238 and FIGURE 10) shown in FIGURE 4, which is described below.
  • Modulated IF/RF output 37 from amplifier 36 is fed back to a quadrature tuner 44 whose center frequency is controlled by an IF/RF phase-locked loop 46.
  • the in-phase (I) and quadrature (Q) outputs 48 and 50 of quadrature tuner 44 (block 244) are supplied to and filtered by low pass filters 52 and 54, respectively, to remove potential aliasing components.
  • the filtered outputs from low pass filters 52 and 54 are converted to digital signals by dual analog-to-digital converters 56 and 58, respectively.
  • the digital in-phase and quadrature signals are then provided to a coordinate transform 60, which converts the Cartesian (X, Y) in-phase and quadrature signals into polar (R, ⁇ ) amplitude and phase representations 22 and 64.
  • Amplitude information 64 is sent to automatic gain control loop 200 (FIGURE 4) for comparison with the desired level and filtering.
  • Phase information 22 is supplied as a feedback signal to summer 19 to be subtracted from phase reference signal 18 to generate modulation control signal 24 (block 246) .
  • FIGURE 10 is a flowchart of an exemplary method for automatic gain control loop.
  • Automatic gain control loop 200 includes a summer
  • summer 202 for subtracting amplitude information (AGC input) 64 received from coordinate transform 60 (FIGURE 1) from an automatic gain control reference signal.
  • summer 202 obtains a difference or a comparison of amplitude information 64 and the automatic gain control reference signal (block 312) to generate a result signal (block 314) .
  • the automatic gain control reference signal may be a predetermined fixed signal or one generated by a known method or process executed by a microprocessor, computer, or other computing platforms.
  • the output from summer 202 is supplied to an integrator 204.
  • the output of integrator 204 or automatic gain control loop 200 is coupled to digital-to-analog converter 38 (FIGURE 1) , having an output that is low pass filtered and used to control automatic gain control amplifier 36 (block 316) .
  • the process then returns to block 244 in FIGURE 6 (block 318) .
  • amplitude information 64 is used as a feedback signal for automatic gain control loop 200 and phase information 22 is used as a feedback signal for modulator phase-locked loop 20.
  • An advantage of the present invention is that modulation deviation is accurate, since it is directly controlled by a digital source.
  • FIGURE 2 a block diagram of an embodiment of a wideband phase modulator 70 is shown according to the present invention. Reference is also made to flowcharts shown in FIGURES 6, 8, 10, and 11. The process begins in the flowchart shown in FIGURE 6, with the flowchart shown in FIGURE 8 supplying details on an embodiment of wideband phase digital modulation signal processing (block 270) according to the present invention.
  • the flowcharts in FIGURES 10 and 11 supply details on automatic gain control and deviation signal generating processes, respectively.
  • the modulation input signal is received and processed (block 232) to remove noise and signals residing in certain frequencies, for example.
  • a digital phase modulation input word 72 is supplied to a bandpass filter 74 (FIGURE 8, block 272) having an input coupled to a multiplier 78.
  • Low input frequencies are rejected by bandpass filter 74 to prevent interference with the operation of modulator 70.
  • High frequencies which cannot be processed accurately by a finite impulse response (FIR) differentiator 76 coupled to the output of multiplier 78 are also rejected by bandpass filter 74.
  • the bandpass filter output is also routed to a deviation calibration loop 210 (FIGURE 5) or function 320 (FIGURE 11), to be described.
  • Deviation calibration loop 210 and function 320 essentially compare the filtered phase modulation input signal 72 and phase signal 118 generated by coordinate transform 116 (block 274) to generate a deviation control signal 80 (block 276) .
  • Deviation calibration multiplier 78 uses deviation control signal 80 to adjust the filtered phase modulation input signal to produce the required phase modulation peak deviation (block 278) .
  • the output of multiplier 78 is coupled to finite impulse response differentiator 76, which differentiates the multiplier output (block 280) .
  • the finite impulse response differentiator output is then summed with the output of a modulator loop filter 84 by a summer 85 (block 284) .
  • the input to modulator loop filter 84 is phase signal 118 from coordinate transform 116 (block 282) .
  • the process shown in FIGURE 8 ends in block 286.
  • the processed phase modulation input signal and a feedback signal consisting of the filtered phase signal from loop filter 84 are received at summer 85 (block 234) to generate a modulation control signal 86 (block 236) .
  • Modulation control signal 86 is then converted into analog form by a digital-to-analog converter 88 and then filtered (block 237), by a lowpass filter 90, for example.
  • the output from lowpass filter 90 is provided to a voltage controlled oscillator 92, which generates a modulated output signal (block 238) .
  • An automatic gain control amplifier 94 is coupled to voltage controlled oscillator 92 to keep the output power of the modulated output signal at a constant level.
  • Automatic gain control amplifier 94 is driven by an output from a digital-to-analog converter 96 and lowpass filter 98 that are coupled to an output 100 of an automatic gain control loop 200 (block 240) , an embodiment of which is shown in FIGURES 4 and 10 as described.
  • finite impulse response differentiator 76 produces a signal that is used to tune voltage controlled oscillator 92 to produce phase modulation. Finite impulse response differentiator 76 may also provide compensation to correct amplitude vs. frequency nonlinearities in digital-to-analog converter 88, lowpass filter 90, and/or voltage controlled oscillator 92.
  • IF/RF modulated output 102 from amplifier 94 is fed back to a quadrature tuner 104 whose center frequency is controlled by an IF/RF phase-locked loop 106 (block 244) .
  • the in-phase and quadrature outputs of quadrature tuner 104 are filtered to remove potential aliasing components by, for example, lowpass filters 108 and 110, respectively, and then converted to digital form by dual analog-to-digital converters 112 and 114, respectively (block 246) .
  • a coordinate transform 116 receives and converts the digital in-phase and quadrature signals into phase and amplitude representations 118 and 120 (block 246) .
  • Amplitude information 120 is provided to an automatic gain control loop (an embodiment 200 shown in FIGURE 4) for comparison with the desired reference level and filtering.
  • Phase information 118 from coordinate transform 116 is provided to modulator phase-lock loop filter 84, the output of which is summed with the feed- forward modulation signal from finite impulse response differentiator 76.
  • Phase information 118 is also provided to deviation calibration loop 210 (FIGURE 5) .
  • FIGURE 5 an embodiment of a deviation calibration loop 210 is shown, and to FIGURE 11, a flowchart of the process for generating a deviaiton output signal is shown.
  • Deviation calibration loop 210 includes a squarer 212 receiving measured phase information 118 from coordinate transform 116 and a squarer 214 receiving the filtered phase modulation input signal from bandpass filter 74 (blocks 322 and 324) .
  • the squared values are supplied to a summer 216, which subtracts the squared measured phase information 118 from the squared filtered phase modulation input (block 326) .
  • the output from summer 216 is coupled to an integrator 218 (block 328) , which generates a deviation control output (block 330) .
  • the process ends in block 332.
  • the mean square values of the measured phase information 118 and the filtered phase modulation input are compared.
  • the comparison output is filtered by integrator 218, which generates a deviation control signal 80 that is supplied to multiplier 78 (FIGURE 2) .
  • wideband PM modulator 70 may be divided into a digital portion 122 and the same RF/analog portion 68 as that of narrowband PM/FM modulator 10 shown in FIGURE 1.
  • FIGURE 3 A block diagram of an embodiment of a wideband frequency modulator 130 is shown in FIGURE 3. Flowcharts of processes of frequency modulation are shown in FIGURES 6, 9, 10 and 11. FIGURE 9, in particular, shows a flowchart of an embodiment of frequency modulation input signal processing 290.
  • a frequency modulation input word 132 is received and processed (block 232) by filtering with a highpass filter 134 to eliminate low input frequencies which may interfere with the operation of modulator loop (FIGURE 9, block 292) .
  • the highpass filter output is then routed to a requested deviation input of a deviation calibration loop 210, such as the one shown in FIGURE 5 and described above .
  • the deviation calibration process 320 is also shown in FIGURE 11 and basically compares the filtered frequency modulation input signal with the frequency signal derived from the phase signal output from a coordinate transform 174 (block 296) .
  • the deviation calibration loop and process generate a deviation control signal 138 (block 298) .
  • a deviation calibration multiplier 136 uses deviation control signal 138 to adjust the filtered frequency modulation input signal from highpass filter 134 to produce the required frequency modulation peak deviation (block 300) .
  • the multiplier output is then provided to a summer 137, which sums it with the output from a modulator loop filter 140 to generate a modulation control signal 142 (blocks 302 and 304) .
  • Process 290 ends in block 306.
  • Modulation control signal 142 is converted into analog form by a digital-to-analog converter 144 and then provided to a lowpass filter 146 (FIGURE 6, block 238) .
  • the lowpass filter output controls a voltage controlled oscillator 148, which generates a modulated output signal 150 (block 238) .
  • An automatic gain control amplifier 152 is coupled to the output of voltage controlled oscillator 148 to keep the output power of output signal 150 at a substantially constant level and generates a modulated output signal 154 therefrom.
  • Automatic gain control amplifier 152 is driven by a digital-to-analog converter 156 coupled in series with a lowpass filter 158, which are in turn coupled to an output 160 of an automatic gain control loop (block 240) , an embodiment is shown in FIGURE 4.
  • the automatic gain control process is also shown in FIGURE 10.
  • IF/RF modulated output signal 154 is fed back to a quadrature tuner 162 whose center frequency is controlled by an IF/RF phase-locked loop 164 (block 244) .
  • the in- phase and quadrature outputs of quadrature tuner 162 are filtered by lowpass filters 166 and 168, respectively, to remove potential aliasing components, then converted to digital form by dual analog-to-digital converters 170 and 172, respectively.
  • a coordinate transform 174 coupled to analog-to-digital converters 170 and 172 converts the digital in-phase and quadrature outputs into polar phase and amplitude representations 176 and 178 thereof (block 246) .
  • Amplitude information 178 is provided to the automatic gain control loop for comparison with the desired level and filtering (FIGURE 10, block 312).
  • Phase information 176 is provided to modulator phase- locked loop filter 140, the output of which is then summed with the feed- forward modulation signal from multiplier 136.
  • Phase information 176 is also provided to a backward difference circuit or input -previous circuit 180 to obtain frequency information.
  • Input-previous block provides a difference between the current phase information and a previous phase information.
  • the measured feedback frequency from backward difference circuit 180 is then provided to the deviation calibration loop, which compares the filtered frequency modulation input signal mean square value with the measured frequency deviation mean square value (FIGURE 9, block 296) .
  • the comparison output is then supplied to a integrator 218 (FIGURE 5 and FIGURE 11, block 328), which generates deviation control signal 138 (blocks 298 and 330) .
  • the deviation control signal is provided to multiplier 136 and is multiplied thereby with the filtered frequency modulation input signal (block 300) to generate the modulation control signal (FIGURE 6, block 236) .
  • wideband frequency modulator 130 may be divided into a digital portion 182 and the same RF/analog portion 68 as that of narrowband PM/FM modulator 10 shown in FIGURE 1 and wideband phase modulator 70 shown in FIGURE
  • FIGURES 1-11 use a voltage controlled oscillator and quadrature tuner feedback to address the problems of frequency translation, digital analog converter spurious and dynamic range, and high speed digital-to-analog converter drive circuitry complexity and power.
  • all three embodiments include an identical RF/analog section 68. Therefore, implementation of the digital portions 66 , 122, and 182 of these digital modulators with programmable logic devices would allow configuration of any of these modulators on a single platform.

Abstract

Apparatus for phase/frequency digital modulation includes a digital circuit receiving and processing a digital modulation input signal to generate a digital modulation control signal, a digital-to-analog converter coupled to the digital circuit converts the digital modulation control signal into an analog modulation control signal, and an RF/analog circuit is coupled to the digital-to-analog converter. The RF/analog circuit includes a voltage controlled oscillator to generate a modulated output signal in response to the analog modulation control signal, and a quadrature tuner coupled to the voltage controlled oscillator generates an in-phase tuner output and a quadrature tuner output in response to the modulated output signal. An analog-to-digital converter is coupled to the quadrature tuner and converts the in-phase tuner output and the quadrature tuner output to digital in-phase and quadrature tuner outputs. The digital in-phase tuner output and the quadrature tuner output are fed back to the digital circuit to generate the digital modulation control signal.

Description

APPARATUS AND METHOD FOR PHASE AND FREQUENCY DIGITAL MODULATION
TECHNICAL FIELD OF THE INVENTION
This invention is related in general to signal modulation, and more particularly, to apparatus and method for phase and frequency digital modulation.
BACKGROUND OF THE INVENTION
The typical digital phase and frequency modulator (PM/FM) suffers from one or more inherent performance and/or implementation limitations. One conventional approach for digital phase and frequency modulation first generates a relatively low frequency modulated signal using a low to moderate sample rate digital to analog converter
(DAC) and an anti-aliasing filter. The resulting signal is then up-converted to the desired output frequency using one or more frequency translation circuits. The disadvantages of this approach are the complexity of the frequency translation circuit implementation using mixers and filters, isolation and bandwidth limitations associated with frequency translation filtering, and the presence of mixing spurious signals at the final output.
Another similar conventional implementation generates quadrature low frequency modulated signals using two digital-to-analog converters and anti-aliasing filters with a low to moderate sample rate. These signals are used to control a quadrature modulator, which directly produces the modulated output centered at the frequency of its local oscillator input. This approach provides lower complexity and wider output bandwidth capabilities than the up- conversion approach. However, the major disadvantage of this approach is that it produces distortions due to amplitude and phase imbalances which are unacceptable in many applications.
A third conventional approach uses an undersampling (or bandpass sampling) technique with a digital-to-analog converter with a moderate to high sample rate. The output signal is a sampling image which is a sum or difference of the fundamental digital-to-analog converter output frequency and a harmonic of the sampling frequency. The image is selected from all of the other images present at the digital-to-analog converter output with a bandpass filter. This approach has bandwidth limitations due to the output filtering, and dynamic range (signal-to-noise ratio) limitations of the digital-to-analog converter at output frequencies above its sample rate.
A fourth conventional implementation utilizes a very high speed digital-to-analog converter which oversamples the desired output frequency. This approach avoids the frequency conversion and filtering limitations of the other aforementioned implementations. However, spurious signals are present in the output of this implementation due to the limited resolution of the high speed digital-to-analog converter. The high levels of the spurious signals are unacceptable in many applications. The circuitry required to generate the high speed digital-to-analog converter data inputs also generally has much higher complexity and power consumption than the other approaches. SUMMARY OF THE INVENTION
It has been recognized that it is desirable to provide apparatus and method for phase and frequency digital modulation which avoids the problems and disadvantages of conventional circuits.
In one embodiment of the invention, apparatus for phase/frequency digital modulation includes a digital circuit receiving and processing a digital modulation input signal to generate a digital modulation control signal, a digital-to-analog converter coupled to the digital circuit operable to convert the digital modulation control signal into an analog modulation control signal, and an RF/analog circuit coupled to the digital-to-analog converter. The RF/analog circuit includes a voltage controlled oscillator operable to generate a modulated output signal in response to the analog modulation control signal, and a quadrature tuner coupled to the voltage controlled oscillator operable to generate an in-phase tuner output and a quadrature tuner output in response to the modulated output signal. An analog-to-digital converter is coupled to the quadrature tuner and operable to convert the in-phase and quadrature tuner outputs to digital in-phase and quadrature tuner outputs. The digital in-phase and quadrature tuner outputs are fed back to the digital circuit to generate the digital modulation control signal.
In another embodiment of the invention, apparatus for phase/frequency digital modulation includes a programmable logic digital circuit receiving a modulation input signal and operable to generate a modulation control signal therefrom, and an RF/analog circuit coupled to the programmable logic digital circuit and receiving the modulation control signal. The RF/analog circuit includes a voltage controlled oscillator operable to generate a modulated output signal in response to the modulation control signal, and a quadrature tuner coupled to the voltage controlled oscillator operable to generate an in- phase tuner output and a quadrature tuner output in response to the modulation control signal. The in-phase and quadrature tuner outputs are fed back to the programmable logic digital circuit to generate the modulation control signal. In yet another embodiment of the invention, a method for phase/frequency digital modulation includes the steps of receiving a modulation input signal and at least one feedback signal and generating a modulation control signal therefrom, using the modulation control signal to control a voltage controlled oscillator and generating a modulated output signal, generating an in-phase and a quadrature tuner outputs in response to the modulated output signal, and generating the at least one feedback signal from the in-phase and quadrature tuner outputs. One technical advantage of the invention is that the use of the voltage controlled oscillator and quadrature feedback avoids the problems of frequency translation, digital-to-analog converter spurious and dynamic range, and high speed digital-to-analog converter drive circuitry complexity and power consumption. Another technical advantage of the invention is that identical RF/analog circuits enables the implementation of the digital circuit with programmable logic devices that can be configured. BRIEF DESCRIPTION OF THE DRAWINGS
For a better understanding of the present invention, reference may be made to the accompanying drawings, in which: FIGURE 1 is a block diagram of an embodiment of a narrowband phase and frequency digital modulator constructed according to the teachings of the present invention;
FIGURE 2 is a block diagram of an embodiment of a wideband phase digital modulator constructed according to the teachings of the present invention;
FIGURE 3 is a block diagram of an embodiment of a wideband frequency digital modulator constructed according to the teachings of the present invention; FIGURE 4 is a block diagram of an embodiment of an automatic gain control circuit constructed according to the teachings of the present invention;
FIGURE 5 is a block diagram of an embodiment of a deviation calibration circuit constructed according to the teachings of the present invention;
FIGURE 6 is a flowchart of an embodiment of a method for common phase and/or frequency digital modulation according to the teachings of the present invention;
FIGURE 7 is a flowchart of an embodiment of a method for processing the modulation input signal for narrowband phase and frequency digital modulation according to the teachings of the present invention;
FIGURE 8 is a flowchart of an embodiment of a method for processing the modulation input signal for wideband phase digital modulation according to the teachings of the present invention; FIGURE 9 is a flowchart of an embodiment of a method for processing the modulation input signal for wideband frequency digital modulation according to the teachings of the present invention; FIGURE 10 is a flowchart of an embodiment of a method for automatic gain control loop for phase and frequency digital modulation according to the teachings of the present invention; and
FIGURE 11 is a flowchart of an embodiment of a method for generating a deviation control output signal for phase and frequency digital modulation according to the teachings of the present invention.
DETAILED DESCRIPTION OF THE INVENTION The preferred embodiments of the present invention are illustrated in FIGURES 1-11, where like reference numerals are used to refer to like and corresponding parts or portions of the invention.
It is important to note that certain circuit components, circuit blocks, and devices forming portions of the digital modulators of the present invention described below are well known in the art of digital signal processing. Therefore, a detailed description of the well known circuit components, circuit blocks, and devices is not required. It may also be worthwhile to note that the digital modulators of the present invention are described in the context of both algorithms and functional circuit blocks for implementing the algorithms. Therefore, the present invention anticipates any circuit designs that implement the algorithms shown in the figures and described below. Referring to block diagrams shown in FIGURES 1-3, it may be seen that narrowband phase and frequency modulator 10 (FIGURE 1), wideband phase modulator 70 (FIGURE 2), and wideband frequency modulator 130 (FIGURE 3) each has a digital circuit portion (66, 122, 182) and a common RF/analog circuit portion 68. In general, the common phase or frequency modulator process is shown in FIGURE 6, which begins in block 230. The modulation input signal is first processed in some manner by the digital portion of the modulators, as shown in block 232. Thereafter, the processed signal is used to control a voltage controlled oscillator to generate a modulated output signal, as shown in block 238. An automatic gain control loop or process is then used to generate an output to drive an automatic gain control amplifier receiving the modulated output signal, as shown in block 242. In block 244, in-phase tuner output and quadrature tuer output are generated from the output of the automatic gain control amplifier. A feedback signal is then generated from the in-phase tuner output and/or the quadrature tuner outputs, as shown in block 246. The process ends in block 248. The process described above is relevant to each of the modulation methods described below.
A block diagram of an embodiment of a narrowband phase and frequency digital modulator 10 constructed according to the teachings of the present invention is shown in FIGURE 1. Referring also to FIGURE 7 for a flowchart of the exemplary method for narrowband phase and frequency digital modulation, which begins in block 250. A digital frequency modulation input word 12 is processed by supplying it to a phase accumulator 14, which converts input word 12 into a time varying phase representation (block 252) . The output from phase accumulator 14 is summed, by a summer 17, with a digital phase modulation input word 16 to generate a phase reference signal 18 for a modulator phase-locked loop
(PLL) 20 (block 254) . Phase reference signal 18 along with a feedback signal in the form of a phase signal 22 are provided to and received by a summer 19. Summer 19 subtracts phase signal 22 from phase reference signal 18 to form a phase error signal or a modulation control signal 24
(block 256) that is provided as an input to a loop filter
26. Loop filter 26 filters modulation control signal 24 (block 257) . The digital portion of the process ends in block 258.
The output of loop filter 26 is a filtered modulation control signal coupled to a digital-to-analog converter (DAC) 28 followed by an anti-aliasing or low pass filter 30. The output from filter 30 drives a voltage controlled oscillator (VCO) 32 having a modulated intermediate frequency (IF) or radio frequency (RF) output 34 (FIGURE 6, block 238) . When phase-locked loop 20 is locked, modulated output 34 tracks the phase of phase reference signal 18, which is modulated by frequency and phase modulation input words 12 and 16. An automatic gain control (AGC) amplifier 36 coupled to voltage controlled oscillator 32 receives modulated output 34 therefrom and generates an output with an IF/RF output power kept at a constant level (block 242) . Automatic gain control amplifier 36 is driven by an output from a digital-to-analog converter 38 and low pass filter 40 combination that is connected to an output 42 of an automatic gain control loop 200 (block 238 and FIGURE 10) shown in FIGURE 4, which is described below. Modulated IF/RF output 37 from amplifier 36 is fed back to a quadrature tuner 44 whose center frequency is controlled by an IF/RF phase-locked loop 46. The in-phase (I) and quadrature (Q) outputs 48 and 50 of quadrature tuner 44 (block 244) are supplied to and filtered by low pass filters 52 and 54, respectively, to remove potential aliasing components. The filtered outputs from low pass filters 52 and 54 are converted to digital signals by dual analog-to-digital converters 56 and 58, respectively. The digital in-phase and quadrature signals are then provided to a coordinate transform 60, which converts the Cartesian (X, Y) in-phase and quadrature signals into polar (R, θ) amplitude and phase representations 22 and 64. Amplitude information 64 is sent to automatic gain control loop 200 (FIGURE 4) for comparison with the desired level and filtering. Phase information 22 is supplied as a feedback signal to summer 19 to be subtracted from phase reference signal 18 to generate modulation control signal 24 (block 246) .
Referring to FIGURE 4, an exemplary embodiment of an automatic gain control loop 200 is shown. FIGURE 10 is a flowchart of an exemplary method for automatic gain control loop. Automatic gain control loop 200 includes a summer
202 for subtracting amplitude information (AGC input) 64 received from coordinate transform 60 (FIGURE 1) from an automatic gain control reference signal. In effect, summer 202 obtains a difference or a comparison of amplitude information 64 and the automatic gain control reference signal (block 312) to generate a result signal (block 314) . The automatic gain control reference signal may be a predetermined fixed signal or one generated by a known method or process executed by a microprocessor, computer, or other computing platforms. The output from summer 202 is supplied to an integrator 204. The output of integrator 204 or automatic gain control loop 200 is coupled to digital-to-analog converter 38 (FIGURE 1) , having an output that is low pass filtered and used to control automatic gain control amplifier 36 (block 316) . The process then returns to block 244 in FIGURE 6 (block 318) . In this manner, amplitude information 64 is used as a feedback signal for automatic gain control loop 200 and phase information 22 is used as a feedback signal for modulator phase-locked loop 20.
An advantage of the present invention is that modulation deviation is accurate, since it is directly controlled by a digital source.
Referring to FIGURE 2, a block diagram of an embodiment of a wideband phase modulator 70 is shown according to the present invention. Reference is also made to flowcharts shown in FIGURES 6, 8, 10, and 11. The process begins in the flowchart shown in FIGURE 6, with the flowchart shown in FIGURE 8 supplying details on an embodiment of wideband phase digital modulation signal processing (block 270) according to the present invention. The flowcharts in FIGURES 10 and 11 supply details on automatic gain control and deviation signal generating processes, respectively.
Referring first to FIGURE 6, the modulation input signal is received and processed (block 232) to remove noise and signals residing in certain frequencies, for example. A digital phase modulation input word 72 is supplied to a bandpass filter 74 (FIGURE 8, block 272) having an input coupled to a multiplier 78. Low input frequencies are rejected by bandpass filter 74 to prevent interference with the operation of modulator 70. High frequencies which cannot be processed accurately by a finite impulse response (FIR) differentiator 76 coupled to the output of multiplier 78 are also rejected by bandpass filter 74. The bandpass filter output is also routed to a deviation calibration loop 210 (FIGURE 5) or function 320 (FIGURE 11), to be described. Deviation calibration loop 210 and function 320 essentially compare the filtered phase modulation input signal 72 and phase signal 118 generated by coordinate transform 116 (block 274) to generate a deviation control signal 80 (block 276) . Deviation calibration multiplier 78 uses deviation control signal 80 to adjust the filtered phase modulation input signal to produce the required phase modulation peak deviation (block 278) . The output of multiplier 78 is coupled to finite impulse response differentiator 76, which differentiates the multiplier output (block 280) . The finite impulse response differentiator output is then summed with the output of a modulator loop filter 84 by a summer 85 (block 284) . The input to modulator loop filter 84 is phase signal 118 from coordinate transform 116 (block 282) . The process shown in FIGURE 8 ends in block 286. The processed phase modulation input signal and a feedback signal consisting of the filtered phase signal from loop filter 84 are received at summer 85 (block 234) to generate a modulation control signal 86 (block 236) . Modulation control signal 86 is then converted into analog form by a digital-to-analog converter 88 and then filtered (block 237), by a lowpass filter 90, for example. The output from lowpass filter 90 is provided to a voltage controlled oscillator 92, which generates a modulated output signal (block 238) . An automatic gain control amplifier 94 is coupled to voltage controlled oscillator 92 to keep the output power of the modulated output signal at a constant level. Automatic gain control amplifier 94 is driven by an output from a digital-to-analog converter 96 and lowpass filter 98 that are coupled to an output 100 of an automatic gain control loop 200 (block 240) , an embodiment of which is shown in FIGURES 4 and 10 as described.
It may be seen that in operation, finite impulse response differentiator 76 produces a signal that is used to tune voltage controlled oscillator 92 to produce phase modulation. Finite impulse response differentiator 76 may also provide compensation to correct amplitude vs. frequency nonlinearities in digital-to-analog converter 88, lowpass filter 90, and/or voltage controlled oscillator 92.
IF/RF modulated output 102 from amplifier 94 is fed back to a quadrature tuner 104 whose center frequency is controlled by an IF/RF phase-locked loop 106 (block 244) . The in-phase and quadrature outputs of quadrature tuner 104 are filtered to remove potential aliasing components by, for example, lowpass filters 108 and 110, respectively, and then converted to digital form by dual analog-to-digital converters 112 and 114, respectively (block 246) . A coordinate transform 116 receives and converts the digital in-phase and quadrature signals into phase and amplitude representations 118 and 120 (block 246) . Amplitude information 120 is provided to an automatic gain control loop (an embodiment 200 shown in FIGURE 4) for comparison with the desired reference level and filtering.
Phase information 118 from coordinate transform 116 is provided to modulator phase-lock loop filter 84, the output of which is summed with the feed- forward modulation signal from finite impulse response differentiator 76. Phase information 118 is also provided to deviation calibration loop 210 (FIGURE 5) . Referring to FIGURE 5, an embodiment of a deviation calibration loop 210 is shown, and to FIGURE 11, a flowchart of the process for generating a deviaiton output signal is shown. Deviation calibration loop 210 includes a squarer 212 receiving measured phase information 118 from coordinate transform 116 and a squarer 214 receiving the filtered phase modulation input signal from bandpass filter 74 (blocks 322 and 324) . The squared values are supplied to a summer 216, which subtracts the squared measured phase information 118 from the squared filtered phase modulation input (block 326) . The output from summer 216 is coupled to an integrator 218 (block 328) , which generates a deviation control output (block 330) . The process ends in block 332. In operation, the mean square values of the measured phase information 118 and the filtered phase modulation input are compared. The comparison output is filtered by integrator 218, which generates a deviation control signal 80 that is supplied to multiplier 78 (FIGURE 2) . Note that wideband PM modulator 70 may be divided into a digital portion 122 and the same RF/analog portion 68 as that of narrowband PM/FM modulator 10 shown in FIGURE 1. Further, it may be noted that the RF/analog portions of modulators 10 and 70 are the same. A block diagram of an embodiment of a wideband frequency modulator 130 is shown in FIGURE 3. Flowcharts of processes of frequency modulation are shown in FIGURES 6, 9, 10 and 11. FIGURE 9, in particular, shows a flowchart of an embodiment of frequency modulation input signal processing 290. Referring to FIGURE 3 and 6, a frequency modulation input word 132 is received and processed (block 232) by filtering with a highpass filter 134 to eliminate low input frequencies which may interfere with the operation of modulator loop (FIGURE 9, block 292) . The highpass filter output is then routed to a requested deviation input of a deviation calibration loop 210, such as the one shown in FIGURE 5 and described above . The deviation calibration process 320 is also shown in FIGURE 11 and basically compares the filtered frequency modulation input signal with the frequency signal derived from the phase signal output from a coordinate transform 174 (block 296) . The deviation calibration loop and process generate a deviation control signal 138 (block 298) . A deviation calibration multiplier 136 uses deviation control signal 138 to adjust the filtered frequency modulation input signal from highpass filter 134 to produce the required frequency modulation peak deviation (block 300) . The multiplier output is then provided to a summer 137, which sums it with the output from a modulator loop filter 140 to generate a modulation control signal 142 (blocks 302 and 304) . Process 290 ends in block 306. Modulation control signal 142 is converted into analog form by a digital-to-analog converter 144 and then provided to a lowpass filter 146 (FIGURE 6, block 238) . The lowpass filter output controls a voltage controlled oscillator 148, which generates a modulated output signal 150 (block 238) . An automatic gain control amplifier 152 is coupled to the output of voltage controlled oscillator 148 to keep the output power of output signal 150 at a substantially constant level and generates a modulated output signal 154 therefrom. Automatic gain control amplifier 152 is driven by a digital-to-analog converter 156 coupled in series with a lowpass filter 158, which are in turn coupled to an output 160 of an automatic gain control loop (block 240) , an embodiment is shown in FIGURE 4. The automatic gain control process is also shown in FIGURE 10.
IF/RF modulated output signal 154 is fed back to a quadrature tuner 162 whose center frequency is controlled by an IF/RF phase-locked loop 164 (block 244) . The in- phase and quadrature outputs of quadrature tuner 162 are filtered by lowpass filters 166 and 168, respectively, to remove potential aliasing components, then converted to digital form by dual analog-to-digital converters 170 and 172, respectively. A coordinate transform 174 coupled to analog-to-digital converters 170 and 172 converts the digital in-phase and quadrature outputs into polar phase and amplitude representations 176 and 178 thereof (block 246) . Amplitude information 178 is provided to the automatic gain control loop for comparison with the desired level and filtering (FIGURE 10, block 312).
Phase information 176 is provided to modulator phase- locked loop filter 140, the output of which is then summed with the feed- forward modulation signal from multiplier 136. Phase information 176 is also provided to a backward difference circuit or input -previous circuit 180 to obtain frequency information. Input-previous block provides a difference between the current phase information and a previous phase information. The measured feedback frequency from backward difference circuit 180 is then provided to the deviation calibration loop, which compares the filtered frequency modulation input signal mean square value with the measured frequency deviation mean square value (FIGURE 9, block 296) . The comparison output is then supplied to a integrator 218 (FIGURE 5 and FIGURE 11, block 328), which generates deviation control signal 138 (blocks 298 and 330) . The deviation control signal is provided to multiplier 136 and is multiplied thereby with the filtered frequency modulation input signal (block 300) to generate the modulation control signal (FIGURE 6, block 236) .
Note that wideband frequency modulator 130 may be divided into a digital portion 182 and the same RF/analog portion 68 as that of narrowband PM/FM modulator 10 shown in FIGURE 1 and wideband phase modulator 70 shown in FIGURE
2.
The embodiments of the present invention shown in FIGURES 1-11 use a voltage controlled oscillator and quadrature tuner feedback to address the problems of frequency translation, digital analog converter spurious and dynamic range, and high speed digital-to-analog converter drive circuitry complexity and power. In addition, all three embodiments include an identical RF/analog section 68. Therefore, implementation of the digital portions 66 , 122, and 182 of these digital modulators with programmable logic devices would allow configuration of any of these modulators on a single platform.
Although several embodiments of the present invention and its advantages have been described in detail, it should be understood that mutations, changes, substitutions, transformations, modifications, variations, and alterations can be made therein without departing from the teachings of the present invention, the spirit and scope of the invention being set forth by the appended claims.

Claims

WHAT IS CLAIMED IS:
1. Apparatus for phase/ frequency digital modulation, comprising : a digital circuit receiving and processing a digital modulation input signal to generate a digital modulation control signal; a digital-to-analog converter coupled to the digital circuit for converting the digital modulation control signal into an analog modulation control signal; and an RF/analog circuit coupled to the digital-to-analog converter, the RF/analog circuit comprising: a voltage controlled oscillator generating a modulated output signal in response to the analog modulation control signal; a quadrature tuner coupled to the voltage controlled oscillator generates an in-phase tuner output and a quadrature tuner output in response to the modulated output signal; and two analog-to-digital converters coupled to the quadrature tuner convert the in-phase and quadrature tuner outputs to digital in-phase and quadrature tuner outputs, the digital in-phase and quadrature tuner outputs being fed back to the digital circuit to generate the digital modulation control signal.
2. The apparatus, as set forth in claim 1, wherein the RF/analog circuit further comprises two filters coupled to the quadrature tuner to filter aliasing components from the in-phase and quadrature tuner outputs.
3. The apparatus, as set forth in claim 1, wherein the RF/analog circuit further comprises an automatic gain control amplifier coupled to the voltage controlled oscillator to maintain the power of the modulated output signal substantially at a predetermined level .
4. The apparatus, as set forth in claim 1, wherein the RF/analog circuit further comprises a lowpass filter coupled to the digital-to-analog converter for filtering aliasing components from the analog modulation control signal to generate a filtered analog modulation control signal provided to the voltage controlled oscillator.
5. The apparatus, as set forth in claim 1, wherein the digital circuit comprises a coordinate transformer coupled to the analog-to-digital converter for converting the in-phase and quadrature tuner outputs to phase and amplitude signals.
6. The apparatus, as set forth in claim 5, wherein the digital circuit comprises: a phase accumulator receiving a digital frequency modulation input signal and converting the digital frequency modulation signal into a time varying phase signal ; a first summer coupled to the phase accumulator for summing the time varying phase signal and a digital phase modulation input signal to generate a phase reference signal; and a second summer coupled to the first summer and the coordinate transformer and to subtract the phase signal from the phase reference signal; and a filter coupled to the second summer generating the digital modulation control signal supplied to the digital- to-analog converter.
7. The apparatus, as set forth in claim 5, further comprising : an automatic gain control amplifier coupled to the voltage controlled oscillator to maintain the power level of the modulated output signal substantially constant; an automatic gain control loop coupled to the coordinate transformer to compare the amplitude signal therefrom with a reference signal and generate a result signal to drive the automatic gain control amplifier.
8. The apparatus, as set forth in claim 5, wherein the digital circuit comprises: a deviation calibration loop receiving a digital phase modulation input signal and the phase signal from the coordinate transformer to compare the digital phase modulation input signal and the phase signal to generate a deviation control output; a multiplier coupled to the deviation calibration loop to multiply the digital phase modulation input signal by the deviation control output to generate a multiplier output ; and a summer coupled to the multiplier and the coordinate transformer to receive and sum the multiplier output and the phase signal to generate the digital modulation control signal supplied to the digital-to-analog converter.
9. The apparatus, as set forth in claim 8, wherein the digital circuit further comprises a bandpass filter receiving the digital phase modulation input signal and generating a filtered digital phase modulation input signal supplied to the deviation calibration loop and the multiplier.
10. The apparatus, as set forth in claim 8, wherein the digital circuit further comprises a finite impulse response differentiator coupled to the output of the multiplier to generate a differentiated multiplier output supplied to the summer.
11. The apparatus, as set forth in claim 8, wherein the digital circuit further comprises a filter coupled to the coordinate transform to receive the phase signal therefrom and generate a filtered phase signal supplied to the summer .
12. The apparatus, as set forth in claim 11, wherein the deviation calibration loop comprises: a first squarer receiving the filtered digital phase modulation input signal from the bandpass filter and generating a squared phase modulation input signal; a second squarer receiving the phase signal from the coordinate transform to generate a squared phase signal; a second summer coupled to the first and second squarers to receive and compare the squared phase signal and the squared phase modulation input signal to generate a comparison signal; and a deviation loop filter coupled to the second summer to generate the deviation control output.
13. The apparatus, as set forth in claim 5, wherein the digital circuit comprises: a backward difference circuit coupled to the coordinate transformer and generating a frequency signal from the phase signal therefrom; a deviation calibration loop receiving and comparing a digital frequency modulation input signal and the frequency signal to generate a deviation output in response thereto; a multiplier coupled to the deviation calibration loop to multiply the digital frequency modulation input signal by the deviation output to generate a multiplier output; and a summer coupled to the multiplier and the coordinate transformer to receive and sum the multiplier output and the phase signal to generate the digital modulation control signal provided to the digital-to-analog converter.
14. The apparatus, as set forth in claim 13, wherein the digital circuit further comprises a highpass filter receiving the digital frequency modulation input signal to generate a filtered digital frequency modulation input signal supplied to the deviation calibration loop.
15. The apparatus, as set forth in claim 13, wherein the digital circuit further comprises a filter coupled to the coordinate transformer to receive the phase signal therefrom and generate a filtered phase signal supplied to the summer .
16. The apparatus, as set forth in claim 14, wherein the deviation calibration loop comprises: a first squarer receiving the filtered digital frequency modulation input signal from the highpass filter and generating a squared frequency modulation input signal; a second squarer receiving the frequency signal from the backward difference circuit to generate a squared frequency signal; a second summer coupled to the first and second squarers to receive and compare the squared frequency signal and the squared frequency modulation input signal to generate a comparison signal; and a filter coupled to the second summer to generate the deviation control output.
17. Apparatus for phase/frequency digital modulation, comprising: a programmable logic digital circuit receiving a modulation input signal and generating a modulation control signal; and an RF/analog circuit coupled to the programmable logic digital circuit and receiving the modulation control signal, the RF/analog circuit comprising: a voltage controlled oscillator generating a modulated output signal in response to the modulation control signal; and a quadrature tuner coupled to the voltage controlled oscillator to generate an in-phase tuner output and a quadrature tuner output in response to the modulation control signal, the in-phase and quadrature tuner outputs being fed back to the programmable logic digital circuit to generate the modulation control signal.
18. The apparatus, as set forth in claim 17, wherein the RF/analog circuit further comprises two filters coupled to the quadrature tuner to filter aliasing components from the in-phase and quadrature tuner outputs.
19. The apparatus, as set forth in claim 17, wherein the digital circuit comprises a coordinate transform coupled to the quadrature tuner to convert the in-phase and quadrature tuner outputs to phase and amplitude signals.
20. The apparatus, as set forth in claim 17, wherein the RF/analog circuit further comprises an automatic gain control amplifier coupled to the voltage controlled oscillator to maintain the power level of the modulated output signal substantially constant.
21. The apparatus, as set forth in claim 19, wherein the programmable logic digital circuit comprises: a phase accumulator receiving a frequency modulation input signal and converting the frequency modulation signal into a time varying phase signal; a first summer coupled to the phase accumulator to receive and sum the time varying phase signal and a phase modulation input signal to generate a phase reference signal; and a second summer coupled to the first summer and the coordinate transformer to subtract the phase signal from the phase reference signal; and a loop filter coupled to the second summer generating the modulation control signal supplied to the voltage controlled oscillator.
22. The apparatus, as set forth in claim 17, wherein the RF/analog circuit further comprises a lowpass filter coupled to the programmable logic digital circuit to filter aliasing components from the modulation control signal to generate a filtered modulation control signal provided to the voltage controlled oscillator.
23. The apparatus, as set forth in claim 17, further comprising: an automatic gain control amplifier coupled to the voltage controlled oscillator to maintain the power level of the modulated output signal substantially constant; and an automatic gain control loop coupled to the coordinate transform to compare the amplitude signal output with a reference signal and generate a result signal to drive the automatic gain control amplifier.
24. The apparatus, as set forth in claim 19, wherein the programmable logic digital circuit comprises: a deviation calibration loop receiving a phase modulation input signal and the phase signal from the coordinate transformer to compare the phase modulation input signal and the phase signal to generate a deviation control output; a multiplier coupled to the deviation calibration loop to multiply the phase modulation input signal by the deviation control output to generate a multiplier output; and a summer coupled to the multiplier and the coordinate transformer to receive and sum the multiplier output and the phase signal to generate the modulation control signal.
25. The apparatus, as set forth in claim 24, wherein the programmable logic digital circuit further comprises a bandpass filter receiving the phase modulation input signal and generating a filtered phase modulation input signal supplied to the deviation calibration loop and the multiplier .
26. The apparatus, as set forth in claim 24, wherein the programmable logic digital circuit further comprises a finite impulse response differentiator coupled to the output of the multiplier to generate a differentiated multiplier output supplied to the summer.
27. The apparatus, as set forth in claim 24, wherein the programmable logic digital circuit further comprises a filter coupled to the coordinate transformer to receive the phase signal and generate a filtered phase signal supplied to the summer.
28. The apparatus, as set forth in claim 25, wherein the deviation calibration loop comprises: a first squarer receiving the filtered phase modulation input signal from the bandpass filter to generate a squared phase modulation input signal; a second squarer receiving the phase signal from the coordinate transformer to generate a squared phase signal; a second summer coupled to the first and second squarers to receive and compare the squared phase signal and the squared phase modulation input signal to generate a comparison signal; and a deviation loop filter coupled to the second summer to generate the deviation output.
29. The apparatus, as set forth in claim 19, wherein the programmable logic digital circuit comprises: a backward difference circuit coupled to the coordinate transformer to generate a frequency signal from the phase signal therefrom; a deviation calibration loop receiving a digital frequency modulation input signal and the frequency signal to compare the digital frequency modulation input signal and the frequency signal to generate a deviation output; a multiplier coupled to the deviation calibration loop to multiply the frequency modulation input signal by the deviation output to generate a multiplier output; and a summer coupled to the multiplier and the coordinate transformer to receive and sum the multiplier output and the phase signal to generate the modulation control signal provided to the voltage controlled oscillator.
30. The apparatus, as set forth in claim 29, wherein the programmable logic digital circuit further comprises a highpass filter receiving the digital frequency modulation input signal to generate a filtered frequency modulation input signal supplied to the deviation calibration loop and the multiplier.
31. The apparatus, as set forth in claim 29, wherein the programmable logic digital circuit further comprises a filter coupled to the coordinate transformer to receive the phase signal and generate a filtered phase signal supplied to the summer .
32. The apparatus, as set forth in claim 30, wherein the deviation calibration loop comprises: a first squarer receiving the filtered frequency modulation input signal from the highpass filter and generating a squared frequency modulation input signal; a second squarer receiving the frequency signal from the backward difference circuit to generate a squared frequency signal; a second summer coupled to the first and second squarers to receive and compare the squared frequency signal and the squared frequency modulation input signal to generate a comparison signal; and a deviation loop filter coupled to the second summer to generate the deviation output.
33. A method for phase/frequency digital modulation, comprising : receiving a modulation input signal and at least one feedback signal and generating a modulation control signal; controlling a voltage controlled oscillator in response to the modulation control signal and generating a modulated output signal; generating an in-phase tuner output and a quadrature tuner output in response to the modulated output signal; and generating the at least one feedback signal from the in-phase tuner output and quadrature tuner output .
34. The method, as set forth in claim 33, further comprising filtering aliasing components from the in-phase tuner output and quadrature tuner output .
35. The method, as set forth in claim 33, further comprising transforming the coordinates of the in-phase tuner output and quadrature tuner output to a phase signal and an amplitude signal.
36. The method, as set forth in claim 33, further comprising maintaining the power level of the modulated output signal substantially constant.
37. The method, as set forth in claim 35, wherein receiving a modulation input signal further comprises: converting the frequency modulation input signal into a time varying phase signal; summing the time varying phase signal and a digital phase modulation input signal and generating a phase reference signal; and subtracting the phase signal from the phase reference signal and generating the modulation control signal.
38. The method, as set forth in claim 33, further comprising removing aliasing components from the modulation control signal and generating a filtered modulation control signal to generate the modulated output signal .
39. The method, as set forth in claim 33, further comprising : comparing an amplitude signal with a reference signal and generating a result signal; and controlling the power level of the modulated output signal substantially constant in response to the result signal .
40. The method, as set forth in claim 33, further comprising: comparing a phase modulation input signal and the phase signal and generating a deviation output; multiplying the phase modulation input signal by the deviation output and generating a multiplier output; differentiating the multiplier output and generating a differentiated multiplier output; and summing the differentiated multiplier output and the phase signal and generating the modulation control signal .
41. The method, as set forth in claim 40, further comprising : bandpass filtering the phase modulation input signal and generating a filtered phase modulation input signal; and generating the deviation output in response to the filtered phase modulation input signal .
42. The method, as set forth in claim 40, summing further comprising filtering the phase signal and generating a filtered phase signal to be summed with the differentiated multiplier output to generate the modulation control signal .
43. The method, as set forth in claim 41, further comprising: squaring the filtered phase modulation input signal and generating a squared phase modulation input signal; squaring the phase signal and generating a squared phase signal; summing the squared phase signal and the squared phase modulation input signal to generate a comparison signal; and filtering the comparison signal and generating the deviation output in response thereto.
44. The method, as set forth in claim 35, further comprising: generating a frequency signal from the phase signal; comparing a frequency modulation input signal and the frequency signal to generate a deviation output; multiplying the frequency modulation input signal by the deviation output to generate a multiplier output; and summing the multiplier output and the phase signal to generate the modulation control signal .
45. The method, as set forth in claim 44, further comprising highpass filtering the frequency modulation input signal and generating a filtered frequency modulation input signal .
46. The method, as set forth in claim 44, further comprising filtering the phase signal and generate a filtered phase signal to be summed with the multiplier output to generate the modulation control signal.
47. The method, as set forth in claim 44, further comprising : squaring the filtered frequency modulation input signal and generating a squared frequency modulation input signal; squaring the frequency signal and generating a squared frequency signal; summing the squared frequency signal and the squared frequency modulation input signal and generating a comparison signal thereof; and filtering the comparison signal and generating the deviation output.
PCT/US2000/021016 1999-08-05 2000-08-01 Apparatus and method for phase and frequency digital modulation WO2001011766A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU65096/00A AU6509600A (en) 1999-08-05 2000-08-01 Apparatus and method for phase and frequency digital modulation
IL14799100A IL147991A0 (en) 1999-08-05 2000-08-01 Apparatus and method for phase and frequency digital modulation
NO20020541A NO20020541D0 (en) 1999-08-05 2002-02-04 Device and method for digital phase and frequency modulation

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/369,484 US6298093B1 (en) 1999-08-05 1999-08-05 Apparatus and method for phase and frequency digital modulation
US09/369,484 1999-08-05

Publications (1)

Publication Number Publication Date
WO2001011766A1 true WO2001011766A1 (en) 2001-02-15

Family

ID=23455673

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/021016 WO2001011766A1 (en) 1999-08-05 2000-08-01 Apparatus and method for phase and frequency digital modulation

Country Status (5)

Country Link
US (1) US6298093B1 (en)
AU (1) AU6509600A (en)
IL (1) IL147991A0 (en)
NO (1) NO20020541D0 (en)
WO (1) WO2001011766A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1249929A1 (en) * 2001-04-09 2002-10-16 Texas Instruments Incorporated FM-PLL modulator

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6661852B1 (en) 1999-07-21 2003-12-09 Raytheon Company Apparatus and method for quadrature tuner error correction
US6640237B1 (en) 1999-07-27 2003-10-28 Raytheon Company Method and system for generating a trigonometric function
US6647075B1 (en) 2000-03-17 2003-11-11 Raytheon Company Digital tuner with optimized clock frequency and integrated parallel CIC filter and local oscillator
US6590948B1 (en) 2000-03-17 2003-07-08 Raytheon Company Parallel asynchronous sample rate reducer
US7171170B2 (en) 2001-07-23 2007-01-30 Sequoia Communications Envelope limiting for polar modulators
US6487398B1 (en) * 2001-08-14 2002-11-26 Motorola, Inc. Low noise architecture for a direct conversion transmitter
US6985703B2 (en) * 2001-10-04 2006-01-10 Sequoia Corporation Direct synthesis transmitter
US7489916B1 (en) 2002-06-04 2009-02-10 Sequoia Communications Direct down-conversion mixer architecture
DE10259356A1 (en) * 2002-12-18 2004-07-15 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. transmitting stage
US7496338B1 (en) 2003-12-29 2009-02-24 Sequoia Communications Multi-segment gain control system
US7609118B1 (en) 2003-12-29 2009-10-27 Sequoia Communications Phase-locked loop calibration system
US7522017B1 (en) 2004-04-21 2009-04-21 Sequoia Communications High-Q integrated RF filters
US7256731B2 (en) * 2004-05-27 2007-08-14 Northrop Grumman Corporation Power cycling for a global positioning system
US7672648B1 (en) 2004-06-26 2010-03-02 Quintics Holdings System for linear amplitude modulation
US7479815B1 (en) 2005-03-01 2009-01-20 Sequoia Communications PLL with dual edge sensitivity
US7548122B1 (en) 2005-03-01 2009-06-16 Sequoia Communications PLL with switched parameters
US7675379B1 (en) 2005-03-05 2010-03-09 Quintics Holdings Linear wideband phase modulation system
US7595626B1 (en) 2005-05-05 2009-09-29 Sequoia Communications System for matched and isolated references
US7974374B2 (en) 2006-05-16 2011-07-05 Quintic Holdings Multi-mode VCO for direct FM systems
US7522005B1 (en) 2006-07-28 2009-04-21 Sequoia Communications KFM frequency tracking system using an analog correlator
US7679468B1 (en) 2006-07-28 2010-03-16 Quintic Holdings KFM frequency tracking system using a digital correlator
US7894545B1 (en) 2006-08-14 2011-02-22 Quintic Holdings Time alignment of polar transmitter
US7920033B1 (en) 2006-09-28 2011-04-05 Groe John B Systems and methods for frequency modulation adjustment
US20090088105A1 (en) * 2007-09-28 2009-04-02 Ahmadreza Rofougaran Method and system for utilizing a programmable coplanar waveguide or microstrip bandpass filter for undersampling in a receiver
CN109787560B (en) * 2019-01-29 2023-01-10 石家庄市凯拓电子技术有限公司 Frequency scale multiplier
CN109883494B (en) * 2019-04-03 2024-02-02 淄博宇声计量科技有限公司 Digital signal modulation and driving circuit of ultrasonic transducer and working method thereof
CN111510119B (en) * 2020-04-30 2023-10-27 矽力杰半导体技术(杭州)有限公司 Frequency modulation circuit and transmitter using same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027087A (en) * 1990-02-02 1991-06-25 Motorola, Inc. Fast-switching frequency synthesizer
US5483203A (en) * 1994-11-01 1996-01-09 Motorola, Inc. Frequency synthesizer having modulation deviation correction via presteering stimulus
US5697068A (en) * 1995-06-15 1997-12-09 Motorola, Inc. System and method for providing a non-invasively tunable transceiver synthesizer
EP0889595A1 (en) * 1997-06-30 1999-01-07 Siemens Aktiengesellschaft High-frequency signal generator
US5894592A (en) * 1997-04-17 1999-04-13 Motorala, Inc. Wideband frequency synthesizer for direct conversion transceiver

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4787058A (en) 1985-09-13 1988-11-22 Rockwell International Corporation Synthetic quadrature generating apparatus
EP0343273B1 (en) 1988-05-27 1994-04-27 Deutsche ITT Industries GmbH Correction circuit for a pair of digital quadrature signals
DE3911486A1 (en) 1989-04-08 1990-10-11 Ant Nachrichtentech CIRCUIT ARRANGEMENT FOR COMPENSATING AN OFFSET VOLTAGE AND USE OF THIS CIRCUIT ARRANGEMENT
US5111162A (en) * 1991-05-03 1992-05-05 Motorola, Inc. Digital frequency synthesizer having AFC and modulation applied to frequency divider
US5249204A (en) 1991-08-12 1993-09-28 Motorola, Inc. Circuit and method for phase error correction in a digital receiver
US5315620A (en) 1992-05-01 1994-05-24 Grumman Aerospace Corporation Arrangement for correction of synchronous demodulator quadrature phase errors
CA2160045C (en) 1994-10-13 1999-04-27 Thad J. Genrich Parallel cascaded integrator-comb filter
FI98420C (en) * 1995-01-24 1997-06-10 Nokia Mobile Phones Ltd Method and connection to generate a modulated signal in a transmitter / receiver
US5790601A (en) * 1995-02-21 1998-08-04 Hughes Electronics Low cost very small aperture satellite terminal
DE19616368C1 (en) 1996-04-24 1997-12-11 Hagenuk Marinekommunikation Gm Demodulation method for single side band signal
CN1115787C (en) * 1997-12-09 2003-07-23 皇家菲利浦电子有限公司 Transmitter comprising VCO
US6028493A (en) * 1998-04-21 2000-02-22 National Semiconductor Corporation Elimination of bandpass filter after quadrature modulator in modulation synthesizer circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5027087A (en) * 1990-02-02 1991-06-25 Motorola, Inc. Fast-switching frequency synthesizer
US5483203A (en) * 1994-11-01 1996-01-09 Motorola, Inc. Frequency synthesizer having modulation deviation correction via presteering stimulus
US5697068A (en) * 1995-06-15 1997-12-09 Motorola, Inc. System and method for providing a non-invasively tunable transceiver synthesizer
US5894592A (en) * 1997-04-17 1999-04-13 Motorala, Inc. Wideband frequency synthesizer for direct conversion transceiver
EP0889595A1 (en) * 1997-06-30 1999-01-07 Siemens Aktiengesellschaft High-frequency signal generator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1249929A1 (en) * 2001-04-09 2002-10-16 Texas Instruments Incorporated FM-PLL modulator
US7136626B2 (en) 2001-04-09 2006-11-14 Texas Instruments Incorporated Radio frequency modulator

Also Published As

Publication number Publication date
NO20020541D0 (en) 2002-02-04
AU6509600A (en) 2001-03-05
IL147991A0 (en) 2002-09-12
US6298093B1 (en) 2001-10-02

Similar Documents

Publication Publication Date Title
US6298093B1 (en) Apparatus and method for phase and frequency digital modulation
US5162763A (en) Single sideband modulator for translating baseband signals to radio frequency in single stage
JP4041323B2 (en) Frequency modulation device, frequency modulation method, and radio circuit device
US5952895A (en) Direct digital synthesis of precise, stable angle modulated RF signal
US5313173A (en) Quadrature modulated phase-locked loop
US6535561B2 (en) Dual-mode modulation systems and methods including oversampling of narrow bandwidth signals and DC offset compensation
US8626082B2 (en) Polar feedback receiver for modulator
JP4246380B2 (en) Post-filter ΔΣ for phase-locked loop modulator control
JPH08307465A (en) Compensation method for reception equipment, reception equipment, and transmission/reception equipment
JP2000286915A (en) Signal modulation circuit and method
JPH04282937A (en) Vector modulation system, vector modulator, vector modulation device and i-q modulation method
JPH09505695A (en) Phase / frequency modulator
WO2006118056A1 (en) Two-point modulation type phase modulating apparatus, polar modulation transmitting apparatus, radio transmitting apparatus, and wireless communication apparatus
US6420940B1 (en) Transmitter with a phase modulator and a phase locked loop
US7706495B2 (en) Two-point frequency modulation apparatus
US6133804A (en) Transmitter with complex phase comparator
JP4416660B2 (en) System and method for converting the frequency of a signal
US6731917B1 (en) Method and apparatus for minimizing image power in the output of a receiver circuit
JP2000209291A (en) Orthogonal modulator
US6839016B2 (en) Pipeline ad converter
JP3532908B2 (en) Frequency control device
EP0508661A1 (en) An FM modulator circuit having separate modulation and channel signal paths
US20050070234A1 (en) Translational loop RF transmitter architecture for GSM radio
JP3984377B2 (en) Digital modulator
US7945219B2 (en) Frequency modulation circuit, transmitter, and communication apparatus

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AE AG AL AM AT AT AU AZ BA BB BG BR BY BZ CA CH CN CR CU CZ CZ DE DE DK DK DM DZ EE EE ES FI FI GB GD GE GH GM HR HU ID IL IN IS JP KE KG KP KR KR KZ LC LK LR LS LT LU LV MA MD MG MK MN MW MX MZ NO NZ PL PT RO RU SD SE SG SI SK SK SL TJ TM TR TT TZ UA UG UZ VN YU ZA ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW MZ SD SL SZ TZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
WWE Wipo information: entry into national phase

Ref document number: PA/A/2002/001190

Country of ref document: MX

WWE Wipo information: entry into national phase

Ref document number: 147991

Country of ref document: IL

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP