WO2001010034A1

WO2001010034A1 - Bandpass modulator

Info

Publication number: WO2001010034A1
Application number: PCT/US2000/040410
Authority: WO
Inventors: Richard Schreier; Paul F. Ferguson, Jr.; Hae-Seung Lee
Original assignee: Analog Devices, Inc.
Priority date: 1999-07-28
Filing date: 2000-07-18
Publication date: 2001-02-08
Also published as: WO2001010034A9

Abstract

A modulator (10) having a continuous-time filter (12) receives an analog input signal (14) and a negative feedback signal (26) from a digital-to-analog converter (18). A desired portion of the input analog signal (14) has a bandwidth centered at a nonzero frequency, FO. The filter has a high gain at the frequency, FS. A digitizer (16) is coupled to the filter (12) and operates at a sampling frequency fS, where the ratio fO/fS is greater than 0.5. With such an arrangement, because the modulator (10) has null frequencies above and below, FS/2, placement of the modulator (10) passband at one of the upper null frequencies enables undersampling, FS∫2FO. For example, with the modulator (16) passband at 3FS/4, instead of FS/4, the sampling rate may be reduced by a factor of 3. Thus, for an analog input signal having a frequency FO=225MHz, FS is now only 300 MHz.

Description

R ANΠ A SS riDTTT ATOP Rar.kgrnimd nf the Invention This invention relates generally to modulators and more particularly to sigma- delta (^Σ-^Δ) modulators adapted to convert an analog input signal having a bandwidth centered at a non-zero intermediate frequency into a digital signal representative of the input analog signal.

As is known in the art, one circuit used to convert an analog signal into a corresponding digital signal is a sigma-delta modulator. The sigma-delta modulator

(sometimes also referred to as a delta-sigma modulator), typically includes a feedback loop having a summing node. The output of the summing node is fed to an integrating amplifier. The summing node is fed by: (1) an input signal sampling and charge transfer circuit and a reference signal sampling and charge transfer circuit. The output of the amplifier is fed to an analog to digital converter (ADC). The ADC operates at a sampling rate fs to produce a series of digital words each having at least one binary bit. In a modulator producing one bit digital words, the ADC is typically a comparator. A controller produces switching signals for the input sampling and charge transfer circuit and the reference sampling and charge transfer circuit based on the sampling clock for the ADC. The polarity of the charge transferred to the summing node by the reference sampling and charge transfer circuit is determined by the series of bits produced by the comparator. The modulator is a charge balancing circuit because, when the output of the comparator is below a threshold voltage, the feedback circuit operates to have the charge in the reference sampling and charge transfer circuit subtracted from the charge produced by the input sampling and charge transfer circuit; whereas, when the output of the comparator exceeds a threshold voltage, the feedback circuit operates to have the charge in the reference sampling and charge transfer circuit added to the charge produced by the input sampling and charge transfer circuit charge. Thus, the output of the comparator is a series of digital output values, such series having an average value over time proportional to the input analog signal. The modulator may be used as an analog to digital converter to convert the input analog signal into corresponding digital words as when the series of output values is fed by the modulator to a decimation filter. As is also known in the art, such a sigma-delta modulator may be used with an input analog signal having a bandwidth about DC or with analog signals having a bandwidth centered about a non-zero intermediate frequency fo. The latter type of sigma-delta modulator is sometimes referred to as a bandpass sigma-delta modulator. That is, the bandpass sigma-delta modulator is very useful in converting a narrow-band analog signal into a corresponding digital signal.

One such bandpass sigma delta converter is shown in FIG. 1. Here, an input analog signal is fed to a bandpass sigma delta ADC having a discrete time loop filter which operates at a sampling frequency, fs. It is noted that the input analog signal has a desired portion and undesired portions. The desired portion is centered at a carrier frequency, fo, here equal to fs/4. The undesired portions are here centered at 3fs/4 and 5fs/4, as indicated. Operating the bandpass sigma delta ADC with discrete time loop filter at the sampling frequency, fs, has the undesirable effect of folding the desired and undesired portions of the input analog signal into a common band, as indicated. One technique used to prevent this undesired folding, is to place an anti-alias filter, here a low-pass filter in front of the bandpass sigma delta ADC with discrete time loop filter, as shown in FIG. 2. Such anti-alias filter passes only the desired portion of the input analog signal to the bandpass sigma delta ADC with discrete time loop filter.

As is also known in the art, one type of bandpass sigma-delta modulator uses a continuous-time loop filter, as shown in FIG. 3. Here, the continuous-time filter is a narrow band, high Q, filter, or resonant structure, typically having a high selectivity, or resonance, at the center frequency fo, is placed in the forward path of the loop, as shown in FIG. 3. When the continuous-time loop filter is used, the modulator typically has an anti-aliasing filtering function inherent in the signal transfer function (STF), where the STF (i.e., H(f), where f is frequency) is the transfer function to the digital output from the analog signal input. In this continuous-time modulator, the sampling operation effectively occurs at the input of the ADC. The quantized output of the ADC is converted into a corresponding analog signal through a digital to analog converter (DAC) operating at the sampling rate fs. Since the loop filter has a very high selectivity at ft, the DAC output cancels the analog input signal in the passband, hence the digital output is an accurate representation of the input analog signal in the passband. As is also known in the art, the sampling rate fs is commonly placed at four times the center frequency ft; i.e., the ratio, R = ft/fs is typically 1/4. This facilitates its use in a demodulation system where the analog input signal is translated to baseband using digital in- phase (I) and quadrature (Q) demodulation of the digital signal. The magnitude of the STF (i.e., H(f)), is shown in FIG. 4. In the passband, the magnitude of the STF is at, or near, its maximum, and typically flat across the band. At other frequencies, the magnitude falls off. A signal transfer function (STF) null is typically placed at 3fs/4 to prevent aliasing of unwanted signals at that frequency, ft, to the passband. The noise transfer function N(f), defined as the transfer function from the quantization noise error of the ADC to the digital output is shown in FIG. 5. It is noted that because of the high selectivity of the filter, the quantization noise has a null at the center frequency, ft, so that the noise is small in the passband but rises outside the passband. There is another null at 3fs/4 and other odd harmonics of fs/4 due to the sampled-data nature of the quantization noise error.

It is noted that with an analog input signal having a passband centered at a high frequency, such as 225 Mhz, with a ratio R of 1/4, the sampling frequency fs must be 900 Mhz, which is too high for present submicron CMOS technologies.

As is also known in the art, the center frequency ft can be placed at nfs/4 where n is an odd integer, here 3, in a bandpass modulator with a discrete-time loop filter. A bandpass anti-alias filter is required in front of the modulator to remove undesired signals at fs/4 and 5 fs/4 as shown in FIG. 5 A. Thus, for an analog input signal having a frequency ft = 225 Mhz, fs is now only 300 Mhz. However, the bandpass anti-alias filter adds power consumption, area and, noise.

Summary rtf the invention

In accordance with the present invention, a modulator is provided. The modulator has a continuous-time filter with one input adapted for coupling to an analog input signal. A desired portion of such analog input signal has a bandwidth centered at a non-zero frequency, ft. The filter has a high selectivity at the frequency, ft. A digitizer is coupled to the filter and operates at a sampling frequency fs, where ft/fs is greater than one-half. A digital to analog converter section is coupled to the digitizer for producing a corresponding analog signal, such produced analog signal being fed to a second input of the filter in a negative feedback arrangement. With such an arrangement, because the modulator has quantization noise nulls at frequencies above fs/2 as well as below fs/2, the passband of the modulator is placed at a frequency of one of the upper quantization noise null frequencies thereby enabling a use a sampling frequency fs , less than 2ft. More particularly, instead of placing the passband of the modulator at fs/4, the passband is placed at higher frequencies where there are quantization noise nulls in the quantization noise transfer function N(f). For example, with the passband of the modulator placed at 3fs/4, instead of at fs/4, the sampling rate of the digitizer may be reduced by a factor of 3. Thus, for an analog input signal having a frequency ft= 225 MHz, fs is now only 300 MHz. The anti-alias function inherent in the STF of the continuous time filter eliminates or reduces the requirement for the bandpass anti-alias filter of FIG. 5A.

In one embodiment, ft/fs = n/4, where n is an odd integer greater than one. Thus, the modulator passband may be placed at other higher quantization noise nulls.

In accordance with another embodiment of the invention, the modulator is used in a demodulation system. The system includes a demodulator fed by the modulator for translating the frequency of the signal produced by the modulator into a series of binary bits having a frequency spectrum centered about a second, for example, baseband frequency.

Thus, not only are the digitizer and digital to analog converter sections able to run at 3 times lower sampling rate, but also the digital complex (i.e., quadrature) demodulator which may follow the modulator.

Brief Description nf the Drawing These and other features of the invention, as well as the invention itself, will become more readily apparent from the following detailed description when read together with the following drawings, in which: FIG. 1 is a block diagram of a ^Σ-^Δ modulator having a discrete-time loop filter operating in accordance with the PRIOR ART;

FIG.2 is a block diagram of a ^Σ-^Δ modulator having a discrete-time loop filter with a bandpass filter prior to the modulator and operating in accordance with the PRIOR ART; FIG. 3 is a block diagram of a ^Σ-^Δ modulator having a continuous-time filter and operating in accordance with the PRIOR ART; FIG. 4 is a diagram of the frequency response of the signal transfer function (STF) (i.e., H(f)) of the modulator of FIG. 3 operating in accordance with the PRIOR ART;

FIG. 5 is a diagram of the frequency spectrum of the quantization noise transfer function (N(f)) of FIG. 3 operating in accordance with the PRIOR ART; FIG. 5 A is a block diagram of another ^Σ-^Δ modulator in accordance with the

PRIOR ART;

FIG. 6 is a block diagram of a modulator in accordance with the invention;

FIG. 7 is a diagram of the frequency spectrum of the signal transfer function (STF) (i.e., H(f)) of the modulator of FIG. 6; FIG. 8 is a block diagram of one embodiment of the modulator of FIG. 6;

FIG. 9 is a block diagram of a demodulation system in accordance with the invention; and

FIG. 10 is a block diagram of modulator of FIG. 6 together with frequency spectrum of the input analog signal, the signal transfer function (STF) of the modulator, and the frequency spectrum of the modulator output signal.

Deςr-.riptinn nf the Preferred Fmhnrliments

Referring now to FIGS. 6 and 10, a sigma-delta modulator 10 is shown having a continuous-time filter 12. The filter 12 has at least one input 14 adapted for coupling to an analog input signal. Here, the analog input signal has undesired portions and a desired portion, as indicated. The desired portion is a narrow band signal having a center frequency ft. Here, for example, the desired portion of the analog input signal has a center frequency ft of 225 MHz, and a bandwidth, BW of 2 MHz.

The filter 12 is, as noted above, a continuous time filter having a high selectivity at the center frequency ft. The filter 12 may be a high Q, resonant structure tuned to the center frequency ft, for example a circuit with a Q greater than 10.

The output of the filter 12 is fed to a digitizer 16, here a sampler-ADC. Here, the digitizer 16 is a comparator for providing one bit samples of the analog signal produced at the output of the filter 12. The sampling of the analog signal produced by the digitizer 16 is at a sampling frequency fs, where, for reasons to be discussed ft/fs is greater than 0.5. Here, for example, with ft = 225 MHz, fs is 300 MHz, i.e., ft/fs = 3/4. The output of the digitizer 16 is here coupled to a signal processor 17. The output of the signal processor 17, to be discussed in more detail in connection with FIG. 8, provides the output of the modulator 10 and such output is fed through a DAC section 18 to a second input 20 of the filter 12 in a negative feedback arrangement. It should be understood that the signal processor 17 need not be used in which case the output of the digitizer 16 provides the output of the modulator 10 and is fed to the DAC section 18. The DAC section 18 converts the digital samples produced by the digitizer 16 at the rate fs into corresponding analog signals at the rate fs. The DAC section 18 includes one, or more DACs, as will be discussed in more detail in connection with FIG. 8.

Because, inter alia, of the high selectivity at ft provided by the filter 12, the signal transfer function STF (i.e, H(f)) has signal passband around the center frequency, ft of the desired portion of the input analog signal, as shown in FIG. 7. As noted above, here ft = 3fs/4. As noted above in connection with FIG. 5, the modulator 10 will have a quantization noise null at fs/4 and in addition, a null at the frequency 3fs/4, which with modulator 10 is now ft. It is noted that here ft is at, or near, the maximum gain of H(f) (FIG. 7). It is noted that the modulator 10 thus operates with a sampling frequency fs which is 3 times slower than that used by the modulator described above in connection with FIG. 3 yet still has a quantization noise null at this frequency, ft=3fs/4.

Referring now to FIG. 8, the modulator 10 is shown in more detail with the same elements used in FIG. 6 being given the same numerical designation in FIG. 8. The continuous time filter 12 includes transconductance amplifiers Gl, G2 and capacitors Cl and C2 arranged as two serially connected integrators arranged to provide a first, high Q, resonant structure and transconductance amplifiers G4, G5 and capacitors C3 and C4 arranged as two serially connected integrators arranged to provide a second high Q, resonant structure. The two resonant structures are serially coupled via nodes X2 and X3 through transconductance amplifier G3, as indicated. Two transconductance amplifiers Gul and Gu2 are included to couple the input analog signal to the filter 12, as indicated. The output of the filter 12 appears at node X4, as indicated.

The output of the filter 12 is fed to digitizer 16 which, as described above operates at the sampling frequency fs. The output of the digitizer 16 is fed to a signal processor 17, here a one sampling period 1/fs, time delay, Z . The output of the signal processor 17 is fed to the DAC section 18, as indicated. The DAC section 18 includes, here four, DACs Gvl, Gv2, Gv3, and Gv4. Each one of the DACs GVl, GV2, GV3, and GV4 is fed by the output of signal processor 17, or if such signal processor is not used, to the digitizer 16. In either event, the output of the digitizer 16 is coupled to the DAC section 18 which includes at least one, here four DACs, GVl, GV2, GV3, and GV4 as indicated, the output of each one thereof being fed to a corresponding one of the nodes Xi, X2, X3, and X of the filter 12, as indicated. An example of such filter 12 uses the following parameters: Capacitance of:

Cl = C2 = C3 = C4 = l pf; Transconductance of:

Gul = 3.92962 x lθ^"6 mhos Gu2 = 6.83758 x lθ^"5 mhos Gl = -1.388384 x lθ^"3 mhos G2= 1.43951 l x lO^"4 mhos G3 = 1.301237 x lO^"4 mhos

G4 =-1.45363 l x lO^"3 mhos G5 =1.374899 x lθ^'3 mhos GVl = 1.57845 x lO^"4 mhos Gv2 = 1.604597 x lO^"4 mhos Gv3 = 1.771376 x lO^"4 mhos

Gv4 =-2.276632 x 10^"4 mhos Referring now to FIG. 9, a demodulation system 100 is shown. An analog signal is received on line 102. Here, the received analog signal has the spectrum as shown in FIG. 6. Thus, here again the input analog signal has undesired portions and a desired portion. The desired portion of the input analog signal thus has the same bandwidth BW as the desired analog signal on line 14 (FIG. 6); here, however, in this example the carrier, or center frequency of the received signal is fRF. The received analog signal is fed to a quadrature mixer 104 where it is mixed with in-phase and quadrature local oscillator signals produced by local oscillator 106, such local oscillator signals having a frequency fLo, here fLo = fRF- ft, where ft is the center frequency of the frequency translated signal. Thus, the center frequency of the received signal on line 102 has been translated down from fRF to the frequency ft in the two channels I and Q.

The signals in the I and Q channels thus both have the same frequency bandwidth as the input signal on line 14 in FIG. 6. The signals in the I and Q channels are fed to a quadrature, or complex, continuous-time filter 12', such filter 12' being equivalent to the filter 12 described above in connection with FIG. 6. Thus, the filter 12' produces corresponding, albeit filtered signals on lines 105ι and 105Q. The outputs on lines 105ι and 105Q are fed to digitizers 16' as shown, each operating at the sampling frequency fs, where ft/fs is greater than 0.5, here ft/fs is 3/4. The digitized signals produced by the digitizers 16' are fed to a digital signal processor (DSP) 109. The DSP 109 includes a quadrature demodulator 108. Here, the DSP 109 provides a demodulation signal for the I and Q channels. Here, the demodulation signal for the I channel is a sequence of binary bits 1, 0, -1, 0, ... signals, while the demodulation signal for the Q channel is a sequence of binary bits 0, 1, 0, -1, ... . It is noted that the two series of bits are effectively 90 degrees apart at ft thereby providing effective demodulation of the signals in the I and Q channels. The outputs of the demodulator 108 are fed to a decimation filter 110 to produce multi-bit digital words corresponding to the demodulated I and Q channel signals.

Other embodiments are within the spirit and scope of the appended claims. For example, the demodulator 108 need not be a quadrature demodulator in which case the continuous time filter 12' need not be a complex filter. Still further, other values of ft/fs than 0.5 which are greater than 0.5 may be used. What is claimed is:

Claims

1. A modulator, comprising: a continuous time filter having an input adapted for coupling to an analog input signal, a desired portion of such input analog signal having a bandwidth centered at a non-zero frequency, ft; a digitizer coupled to the filter, such digitizer being adapted to operate at a sampling frequency fs, where ft/fs is greater than 0.5; and, a digital to analog converter section coupled to the digitizer for producing a corresponding analog signal, such produced analog signal being fed to a second input of the filter in a negative feedback arrangement.

2. The modulator recited in claim 1 wherein ft/fs = n 4 and where n is an odd integer greater than one.

3. The modulator recited in claim 1 including a signal processor disposed between the digitizer and the digital to analog converter section.

4. The modulator recited in claim 3 wherein ft/fs = n/4 and where n is an odd integer greater than one.

5. The modulator recited in claim 1 wherein the digital to analog converter section includes at least one digital to analog converter.

6. The modulator recited in claim 5 including a signal processor disposed between the digitizer and the digital to analog converter section.

7. The modulator recited in claim 6 wherein ft/fs = n/4 and where n is an odd integer greater than one.

8. A demodulation system, comprising: (A) a continuous time filter having one input adapted for coupling to an analog input signal, a desired portion of such analog input signal having a bandwidth centered about a non-zero frequency, ft;

(B) a digitizer coupled to the filter, such digitizer being adapted to operate at a sampling frequency fs, where ft/fs is greater than 0.5; and,

(C) a digital to analog converter section coupled to the digitizer for producing a corresponding analog signal, such produced analog signal being fed to a second input of the filter in a negative feedback arrangement; and

(D) a digital processor section fed by the digitizer for digitally processing the signal produced by the digitizer.

9. The system recited in claim 8 wherein the digital processing section translates the frequency of the signal produced by the digitizer into a series of digital signals having a frequency spectrum centered about a second frequency.

10. The system recited in claim 9 wherein the second frequency is a baseband frequency.

11. The system recited in claim 8 wherein ft/fs = n/4 and where n is an odd integer greater than one.

12. The system recited in claim 8 where the digital signal processing section responds to a series of binary bits comprising a sequence 1, 0, -1, 0.

13. The system recited in claim 8 where the digital processing section includes a quadrature demodulator responsive to a series of binary bits comprising a sequence 1, 0, -1, 0 together with a series of binary bits comprising a sequence 0, 1, 0, -1.

14. The system recited in claim 8 wherein the digital signal processing section includes a signal processor disposed between the digitizer and the digital to analog converter section.

15. The system recited in claim 14 wherein ft/fs = n/4 and where n is an odd integer greater than one.

16. The system recited in claim 8 wherein the digital to analog converter section includes at least one digital to analog converter.

17. The system recited in claim 16 including a signal processor disposed between the digitizer and the digital to analog converter section.

18. The system recited in claim 17 wherein ft/fs = n/4 and where n is an odd integer greater than one.