WO2001008028A3 - Timing shell automation for hardware macro-cell modeling - Google Patents

Timing shell automation for hardware macro-cell modeling Download PDF

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Publication number
WO2001008028A3
WO2001008028A3 PCT/US2000/019868 US0019868W WO0108028A3 WO 2001008028 A3 WO2001008028 A3 WO 2001008028A3 US 0019868 W US0019868 W US 0019868W WO 0108028 A3 WO0108028 A3 WO 0108028A3
Authority
WO
WIPO (PCT)
Prior art keywords
macro
circuitry
operative
cell
processing circuitry
Prior art date
Application number
PCT/US2000/019868
Other languages
French (fr)
Other versions
WO2001008028A2 (en
Inventor
Luc Orion
Original Assignee
Koninkl Philips Electronics Nv
Philips Semiconductors Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Semiconductors Inc filed Critical Koninkl Philips Electronics Nv
Priority to EP00950497A priority Critical patent/EP1196861A2/en
Publication of WO2001008028A2 publication Critical patent/WO2001008028A2/en
Publication of WO2001008028A3 publication Critical patent/WO2001008028A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G06F30/3312—Timing analysis
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/08—Intellectual property [IP] blocks or IP cores

Abstract

An electronic design automation apparatus is provided. The apparatus includes processing circuitry, memory, a keyword symbol table, a macro-cell structural database, a timing shell generator, analysis circuitry, and an error and warning management unit. The memory is coupled with the processing circuitry. The keyword symbol table is stored in the memory. The macro-cell structural database includes timing constraints and I/O declarations of a macro-cell. The timing shell generator is implemented on the processing circuitry and is operative to generate a timing shell for a specific hardware macro-cell. The analysis circuitry includes a lexical analyzer operative to identify the placement of keywords, a syntactical analyzer operative to check syntax, and a semantic analyzer operative to verify meaning, wherein the analysis circuitry is implemented on the processing circuitry. The error and warning management unit is operative to detect and warn of circuitry errors detected during a test procedure. A method is also provided.
PCT/US2000/019868 1999-07-23 2000-07-19 Timing shell automation for hardware macro-cell modeling WO2001008028A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP00950497A EP1196861A2 (en) 1999-07-23 2000-07-19 Timing shell automation for hardware macro-cell modeling

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US35959499A 1999-07-23 1999-07-23
US09/359,594 1999-07-23

Publications (2)

Publication Number Publication Date
WO2001008028A2 WO2001008028A2 (en) 2001-02-01
WO2001008028A3 true WO2001008028A3 (en) 2002-02-14

Family

ID=23414495

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/019868 WO2001008028A2 (en) 1999-07-23 2000-07-19 Timing shell automation for hardware macro-cell modeling

Country Status (2)

Country Link
EP (1) EP1196861A2 (en)
WO (1) WO2001008028A2 (en)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1451731A2 (en) 2001-12-07 2004-09-01 Cadence Design Systems, Inc. Timing model extraction by timing graph reduction
WO2004077213A2 (en) * 2003-01-30 2004-09-10 Vaman Technologies (R & D) Limited System and method for parsing queries for objects irrespective of server functionality
WO2009010817A1 (en) 2007-07-19 2009-01-22 Renault Trucks Method and system for limiting vehicle noises
WO2015048437A1 (en) 2013-09-26 2015-04-02 Synopsys, Inc. Mapping intermediate material properties to target properties to screen materials
WO2015048509A1 (en) 2013-09-26 2015-04-02 Synopsys, Inc. First principles design automation tool
US10516725B2 (en) 2013-09-26 2019-12-24 Synopsys, Inc. Characterizing target material properties based on properties of similar materials
US9836563B2 (en) 2013-09-26 2017-12-05 Synopsys, Inc. Iterative simulation with DFT and non-DFT
US10489212B2 (en) 2013-09-26 2019-11-26 Synopsys, Inc. Adaptive parallelization for multi-scale simulation
US10417373B2 (en) 2013-09-26 2019-09-17 Synopsys, Inc. Estimation of effective channel length for FinFETs and nano-wires
US10078735B2 (en) 2015-10-30 2018-09-18 Synopsys, Inc. Atomic structure optimization
US10734097B2 (en) 2015-10-30 2020-08-04 Synopsys, Inc. Atomic structure optimization
US11682047B2 (en) 2018-08-28 2023-06-20 International Business Machines Corporation Cognitive elevator advertisements

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5517658A (en) * 1990-11-09 1996-05-14 Lsi Logic Corporation Method for testing design timing parameters using a timing shell generator
WO1996023263A1 (en) * 1995-01-25 1996-08-01 Lsi Logic Corporation Timing shell generation through netlist reduction

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5517658A (en) * 1990-11-09 1996-05-14 Lsi Logic Corporation Method for testing design timing parameters using a timing shell generator
WO1996023263A1 (en) * 1995-01-25 1996-08-01 Lsi Logic Corporation Timing shell generation through netlist reduction

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
MCKINNEY M D SR: "Implementing a timing shell for VHDL simulation using the proposed EIA-567 standard", PROCEEDINGS SIXTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, SIXTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT, ROCHESTER, NY, USA, 27 SEPT.-1 OCT. 1993, Sept. 1993, New York, NY, USA, IEEE, USA, pages 288 - 291, XP002177035, ISBN: 0-7803-1375-5 *
TOYODA T ET AL: "A fully integrated characterization and management system for ASIC libraries", PROCEEDINGS OF FIFTH ANNUAL IEEE INTERNATIONAL ASIC CONFERENCE AND EXHIBIT (CAT. NO.92TH0475-4), ROCHESTER, NY, USA, 21-25 SEPT. 1992, 1992, New York, NY, USA, IEEE, USA, pages 245 - 248, XP002177036, ISBN: 0-7803-0768-2 *

Also Published As

Publication number Publication date
WO2001008028A2 (en) 2001-02-01
EP1196861A2 (en) 2002-04-17

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