WO2001004956A1 - Semiconductor device and method of manufacturing same - Google Patents
Semiconductor device and method of manufacturing same Download PDFInfo
- Publication number
- WO2001004956A1 WO2001004956A1 PCT/EP2000/006242 EP0006242W WO0104956A1 WO 2001004956 A1 WO2001004956 A1 WO 2001004956A1 EP 0006242 W EP0006242 W EP 0006242W WO 0104956 A1 WO0104956 A1 WO 0104956A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- coil
- semiconductor body
- semiconductor
- carrier plate
- mesa
- Prior art date
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/645—Inductive arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02381—Side view
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0501—Shape
- H01L2224/05011—Shape comprising apertures or cavities
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05023—Disposition the whole internal layer protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Definitions
- the invention relates to a semiconductor device having a semiconductor body which comprises at least one semiconductor element with an active region and a coil, which coil is coupled to the semiconductor element and forms part of a transformer which includes a further coil, which semiconductor body is mounted onto a carrier plate which comprises an electrically insulating material and is provided with a conductor track.
- Such a device comprising, for example, a bipolar transistor as the semiconductor element, is used, inter alia, as an amplifier of electronic signals, in particular as a high-frequency power amplifier.
- Such a device is disclosed in united States patent specification 5,519,582, published on 21 May 1996.
- a description is given of a semiconductor device comprising a semiconductor body wherein an active semiconductor element is situated on the upper side, and the lower side of said semiconductor body is provided with a trench filled with a conductor, which trench forms a coil and is coupled to the semiconductor element.
- the semiconductor body is mounted on a carrier plate provided with a conductor track.
- the coil may form part of a transformer. An intended application of such a device is as a stable power supply.
- a drawback of the known device resides in that the manufacture thereof is relatively complex because the semiconductor body must be subjected to many process steps on both sides.
- the integration of a transformer, and hence a further coil, in the semiconductor body renders the manufacture even more complicated and, in addition, a comparatively strong capacitive coupling between both coils occurs because the coils must be intertwined.
- a device of the type mentioned in the opening paragraph is characterized in accordance with the invention in that said further coil is situated on the carrier plate, forms part of the conductor track and is electrically separated from the coil.
- said further coil is situated on the carrier plate, forms part of the conductor track and is electrically separated from the coil.
- a device in accordance with the invention has an important additional advantage, partly as a result of the fact that both coils are electrically separated, the additional advantage being that the signal transfer from the external world to the semiconductor body now can take place in a contact- free manner, namely via the magnetic coupling of both coils instead of, for example, via electric connection wires.
- the coil is situated on the same side of the semiconductor body as the active region of the semiconductor element.
- both the coil and the semiconductor element can be manufactured (for the most part) during the same process steps.
- the conductor necessary to form the coil can also be used as the connection conductor for the semiconductor element.
- the active region of the semiconductor element and the coil are situated on one side of the semiconductor body which is secured with the other side to the carrier plate.
- the diameter of the coils must be larger than the distance between the two coils. This distance is equal to the thickness of the semiconductor body and amounts to, for example, 500 ⁇ m in practice, while the diameter of the coil often amounts to, for example, 600 ⁇ m in practice.
- the semiconductor body is embodied so as to be thinner or interrupted at the location of the coil. This results in a particularly low parasitic capacitance and a good magnetic coupling because the magnetic lines extend through the semiconductor material, for example silicon.
- a very attractive modification of a device in accordance with the invention, wherein the semiconductor element comprises a bipolar transistor having, a base, an emitter, and a collector, is characterized in that the semiconductor body is secured, on one side, to an insulating substrate by means of an adhesive layer, which semiconductor body comprises at least three mesa-shaped parts which include, respectively, the active region of the transistor and a collector-connection region, a base-connection region and an emitter-connection region, and by means of which mesa-shaped parts the semiconductor body is secured, on the other side, to a further conductor track on the carrier plate.
- the thickness of the semiconductor body can be relatively small because the semiconductor body is secured to an insulating substrate.
- the coil can have a relatively small diameter, without the magnetic coupling being adversely affected.
- the device is also very compact.
- SMD Surface Mounted Device
- a method of manufacturing a semiconductor device comprising a semiconductor body wherein at least one semiconductor element with an active region is formed as well as a coil which is coupled to said semiconductor element, which coil forms part of a transformer which comprises a further coil, the semiconductor body being secured on a carrier plate which comprises an electrically insulating material and is provided with a conductor track, is characterized in accordance with the invention in that the further coil is provided on the carrier plate and formed in the conductor track and electrically separated from the coil. In this manner, a device in accordance with the invention is obtained in a simple manner.
- the active region of the semiconductor element and the coil are formed on the same side of the semiconductor body.
- the active region of the semiconductor element and the coil are formed on one side of the semiconductor body, and the semiconductor body is secured on the carrier plate on the other side.
- the semiconductor body is embodied so as to be thinner or interrupted at the location of the coil.
- a bipolar transistor having an emitter, a base and a collector is formed as the semiconductor element
- said semiconductor body is glued onto an insulating substrate on this side, whereafter, on the other side of the semiconductor body, at least three mesa-shaped parts are formed from said semiconductor body by locally removing the semiconductor material of the semiconductor body, one of said mesa-shaped parts comprising the active region of the transistor and a collector-connection region, another mesa-shaped part comprising a base-connection region, and a further mesa- shaped part comprising an emitter-connection region, whereafter the semiconductor body is secured to a further conductor track on the carrier plate by means of said mesa-shaped parts.
- Fig. 1 diagrammatically shows a plan view of an embodiment of a semiconductor device in accordance with the invention
- Fig. 2 is a diagrammatic, cross-sectional view, at right angles to the thickness direction and taken on the line II-II, of the device shown in Fig. 1, and Fig. 3 diagrammatically shows the electric circuit which corresponds to the device shown in Fig. 1.
- Fig. 1 is a diagrammatic, plan view of an embodiment of a semiconductor device 100 in accordance with the invention
- Fig. 2 is a diagrammatic, cross-sectional view at right angles to the thickness direction, taken on the line II-II, of the device shown in Fig. 1
- Fig. 3 diagrammatically shows the electric circuit of the device shown in Fig. 1.
- the device 100 comprises, (see for example Fig. 2), a semiconductor body 10 having three mesa- shaped semiconductor parts 11, 12, 13 of silicon.
- the first mesa-shaped part 11 comprises the active region A of a bipolar transistor H, in this case an NPN transistor, including a collector region 1, a base region 2 and an emitter region 3.
- the first mesa-shaped part 11 also includes a collector-connection region 7 which is connected to the collector region 1 by means of a first connection conductor 4, which is made, in this case, of doped silicon.
- a first connection conductor 4 which is made, in this case, of doped silicon.
- the second connection conductor 5 is connected to a coil which, viewed in projection, is situated next to the mesa-shaped parts 11, 13, and which forms part of a transformer F which comprises a further coil 21.
- the single turn of the coil 20 opens into a capacitor 22 which, (also see Fig. 3), serves as a decoupling capacitance 22, which is integrated in the semiconductor body 10 in this case.
- the second connection conductor 5 is connected, via a further connection conductor 26, to a portion 12B of the second mesa-shaped part 12, which serves as the base-connection region 12B.
- the emitter region 3 is connected to an emitter-connection region 9 which is situated in the mesa-shaped part 13.
- the third connection conductor 6 comprises two portions 6 A, 6B which are situated on either side of the second connection conductor 5 and form a transmission line L therewith.
- the semiconductor body 10 is connected, by means of an adhesive layer 50, to an insulating substrate 60, which is made of glass in this example. Both portions 12A, 12B of the second mesa-shaped part 12 stiffen the device 100 next to the coils 20, 21.
- the semiconductor body 10 is secured on a carrier plate 30, in this case a PCB carrier plate 30, which is provided with a conductor track 21.
- the further coil 21 is situated on the carrier plate 30, forms part of the conductor track 21 and is electrically separated from the coil 20.
- the manufacture of the device in accordance with the invention is simplified.
- the semiconductor body 10 now only has to be subjected to a large number of process steps on one side 40 where the semiconductor element H is situated.
- the further coil 21 use is made of a conductor track 21, which is already present on the carrier plate 30, resulting in a further simplification of the manufacturing process.
- the signal transfer from the device to the outside world, and conversely, can now take place in a contact-free manner, namely via magnetic coupling instead of electric connections, for example, in the form of bonding wires.
- the device in accordance with the invention can very suitably be used in (discrete) high- frequency power transistors H.
- the semiconductor body 10 is also interrupted at the location of the coil 20. This implies a very low parasitic capacitance between the coils 20, 21 because, on the one hand, the dielectric constant of air is much smaller than that of silicon and, on the other hand, because air, unlike silicon, does not conduct electric current.
- a further advantage of the device of this example is that it is easy to manufacture because the semiconductor body
- the thickness of the semiconductor body 10 can be relatively small, such as, in this case, 200 ⁇ m, which can be attributed to the fact that the semiconductor body 10 is secured to the insulating substrate 60.
- the diameter of the coil may be relatively small, resulting in a very compact device in accordance with the invention.
- the device exhibits a high amplification of, for example, 20 dB, which can be attributed to the use of the transmission line T.
- the impedance difference of the device 100 with respect to, for example, 50 ⁇ is relatively large, and a device in accordance with the invention then offers a very elegant adaptation of the impedance by virtue of the transformer F.
- the emitter region 3 and, at the location thereof, the third connection conductor 6 as well as the second connection conductor 5 have a comb structure. Both comb structures mesh together and extend perpendicularly to the longitudinal direction of the transmission line L.
- the measures in accordance with the invention enable the entire semiconductor body 10 to be manufactured by means of a single metal layer process.
- the coil 21, which in this case is spiral-shaped comprises two and a half turns.
- the carrier plate 30 is made by means of a multilayer metal process.
- One of the connections 24 of the coil 21 is situated in one of the (at least two) metal layers on the carrier plate 30, the other connection is situated in a further metal layer, not shown in Fig. 1 or 2, on the carrier plate 30.
- the coupling factor between the coils 20, 21 is 0.71 in this example.
- the thickness of the semiconductor body 10 is further reduced, for example to 50 ⁇ m, then said value may even increase to 0.8.
- the impedance transformation then becomes 3.0.
- the input impedance is approximately 1.5 ⁇ , which is increased to approximately 4.5 ⁇ by means of the transformer F.
- Such a "matching" by means of the transformer F implies that the matching circuit on the carrier plate 30 is simple. This has the additional advantage, with respect to an LC section, that the losses are lower at the same quality (Q-factor) of the coils 20, 21. This is very important if the transistor H is an output transistor.
- the device in this example has the following dimensions: the mesa-shaped parts 11, 13 are 200 ⁇ m wide, 500 ⁇ m long and 200 ⁇ m high and the interspace between them is 250 ⁇ m.
- the dimensions of the mesa-shaped portions 12A, 12B are 100x100x200 ⁇ m 3 .
- the width of the second connection conductor 5 is 75 ⁇ m, and said second connection conductor is situated at a distance of 50 ⁇ m from the adjacent sub-conductors 6 A, 6B which, in this case, are twice as wide as the second connection conductor 5.
- the coils 20, 21 have an (internal) diameter of 500 ⁇ m, a width of 50 ⁇ m and a thickness of 1 ⁇ m.
- the mesa-shaped parts 11, 12, 13 are secured to a further conductor track 23 on the carrier plate 20 by means of solder balls 27.
- This conductor track comprises the connection points 24, 25, 26 of the coil 20 and the transistor H.
- the device of this example is manufactured in the following manner, using a method in accordance with the invention.
- An n-type silicon substrate 4 is provided with an n- type epitaxial layer 1.
- the semiconductor body 10 thus formed is provided with a thermal oxide layer 15 wherein an opening is formed at the location of the mesa-shaped part 13 by means of photolithography and etching, through which opening the portion 9 A of the emitter- connection region 8, 9 is formed by means of an n-type diffusion which reaches as far as the substrate 4.
- a conducting layer 5, 6, such as a Ti/Pt/Au layer 5, 6 having a thickness of 1,1 ⁇ m is provided on the insulating layer 15 by means of, for example, sputtering.
- This layer 5, 6 is provided with the pattern shown in Fig. 1 by means of photolithography and etching, thereby providing the base region 2, or rather the above- mentioned base-contact region, with a connection conductor which is connected to the simultaneously formed coil 20.
- the emitter region 3 is connected to its connection regions 9 and the transmission line L is formed.
- the patterned metal layer 5, 6 is provided with a scratch-resistant layer of silicon nitride, which is not shown in the drawing.
- the conductor body 10 is provided with an UV-curable adhesive layer 30, which in this case comprises a hexanedioldiacrylate glue, and with an insulating substrate 40, which in this case is a 1 mm thick plate 40 of Pyrex glass through which the adhesive is cured by exposure to UV radiation.
- the substrate 4 is subsequently reduced in thickness, in this example, to 200 ⁇ m by means of, for example, a grinding process.
- the lower side of the semiconductor body 10 is covered with, for example, also a metal layer 7, 9C comprising, for example, Ti/Pt/Au on which, in this case, a PbSn/Cu/Au solder layer 27 is provided with a view to final assembly by means of soldering.
- This metal layer 7, 9C and the solder layer 27 are patterned by means of photolithography and etching, whereafter the semiconductor body 10 is locally removed by means of etching using a KOH- containing solution, in which process the mesa-shaped parts 11, 12, 13 are formed. In this process, also at the location of the coil 20, the silicon is entirely removed from the semiconductor body 10.
- a semiconductor body 10 is eventually obtained which is ready for final assembly by means of SMD (akkoord ?, delen Ned. Tekst weggevallen).
- the device 100 in accordance with the invention is finally obtained by securing the semiconductor body 10 on a PCB carrier plate 30 which is covered with the conductor tracks 21, 23.
- the conductor track 21 forms the secondary winding 21 of the transformer F and hence the connection between the base 2 of the transistor H and the outside world.
- the semiconductor body 10 is secured on the further conductor track 23 by means of soldering.
- the invention is not limited to the examples given herein, and, within the scope of the invention, many modifications and variations are possible to a person skilled in the art.
- different compositions and thicknesses can be used for the different (semiconductor) regions or layers.
- the invention is not limited to SMD or to discrete transistors. Application within CMOS or BICMOS technology is possible.
- the semiconductor body does not have to be locally interrupted (or thinned) nor does it have to be secured to an insulating substrate.
- the semiconductor body can also be used in a (purely) epitaxial transistor. Also in such a transistor, a part of the semiconductor body can be interrupted or thinned at the location of the coils by means of etching.
- the metal layer used to form the transmission line and the coil may alternatively be provided on a thick synthetic resin layer. If the semiconductor body is manufactured by means of a multilayer metal process, a capacitor, if any, may be manufactured by means of a thicker dielectric between the metal layers instead of LOCOS oxide. This results, however, in a substantial increase in the dimensions of the capacitor.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP00945867A EP1112592A1 (en) | 1999-07-10 | 2000-07-03 | Semiconductor device and method of manufacturing same |
JP2001509087A JP2003504876A (en) | 1999-07-10 | 2000-07-03 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP99202274 | 1999-07-10 | ||
EP99202274.9 | 1999-07-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2001004956A1 true WO2001004956A1 (en) | 2001-01-18 |
Family
ID=8240441
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2000/006242 WO2001004956A1 (en) | 1999-07-10 | 2000-07-03 | Semiconductor device and method of manufacturing same |
Country Status (4)
Country | Link |
---|---|
US (1) | US6437420B1 (en) |
EP (1) | EP1112592A1 (en) |
JP (1) | JP2003504876A (en) |
WO (1) | WO2001004956A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011025897A1 (en) * | 2009-08-26 | 2011-03-03 | Qualcomm Incorporated | Transformer signal coupling for flip-chip integration |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7570129B2 (en) * | 2005-09-02 | 2009-08-04 | Northrop Grumman Corporation | 3D MMIC balun and methods of making the same |
JP2007219869A (en) * | 2006-02-17 | 2007-08-30 | Nagoya Institute Of Technology | Virtual reality presentation device |
JP2009088161A (en) * | 2007-09-28 | 2009-04-23 | Fujitsu Media Device Kk | Electronic component |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1996003772A2 (en) * | 1994-07-26 | 1996-02-08 | Philips Electronics N.V. | Method of manufacturing a semiconductor device for surface mounting, and semiconductor device for surface mounting |
US5519582A (en) * | 1992-10-05 | 1996-05-21 | Fuji Electric Co., Ltd. | Magnetic induction coil for semiconductor devices |
EP0809289A2 (en) * | 1996-05-20 | 1997-11-26 | Harris Corporation | Lid air bridge for integrated circuit |
EP0887861A1 (en) * | 1997-06-27 | 1998-12-30 | STMicroelectronics S.A. | Semiconductor device having separated exchange means |
-
2000
- 2000-07-03 WO PCT/EP2000/006242 patent/WO2001004956A1/en not_active Application Discontinuation
- 2000-07-03 EP EP00945867A patent/EP1112592A1/en not_active Withdrawn
- 2000-07-03 JP JP2001509087A patent/JP2003504876A/en active Pending
- 2000-07-10 US US09/613,227 patent/US6437420B1/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5519582A (en) * | 1992-10-05 | 1996-05-21 | Fuji Electric Co., Ltd. | Magnetic induction coil for semiconductor devices |
WO1996003772A2 (en) * | 1994-07-26 | 1996-02-08 | Philips Electronics N.V. | Method of manufacturing a semiconductor device for surface mounting, and semiconductor device for surface mounting |
EP0809289A2 (en) * | 1996-05-20 | 1997-11-26 | Harris Corporation | Lid air bridge for integrated circuit |
EP0887861A1 (en) * | 1997-06-27 | 1998-12-30 | STMicroelectronics S.A. | Semiconductor device having separated exchange means |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2011025897A1 (en) * | 2009-08-26 | 2011-03-03 | Qualcomm Incorporated | Transformer signal coupling for flip-chip integration |
US8350639B2 (en) | 2009-08-26 | 2013-01-08 | Qualcomm Incorporated | Transformer signal coupling for flip-chip integration |
US8717118B2 (en) | 2009-08-26 | 2014-05-06 | Qualcomm Incorporated | Transformer signal coupling for flip-chip integration |
Also Published As
Publication number | Publication date |
---|---|
EP1112592A1 (en) | 2001-07-04 |
US6437420B1 (en) | 2002-08-20 |
JP2003504876A (en) | 2003-02-04 |
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