WO2001001489A1

WO2001001489A1 - Dram cell arrangement and method for the production thereof

Info

Publication number: WO2001001489A1
Application number: PCT/DE2000/001156
Authority: WO
Inventors: Till Schlösser; Franz Hofmann
Original assignee: Infineon Technologies Ag
Priority date: 1999-06-23
Filing date: 2000-04-13
Publication date: 2001-01-04
Also published as: TW473997B; DE19928781C1

Abstract

First trenches and second trenches (G2) which run perpendicular thereto and are divided into word line trenches and isolation trenches are provided in a substrate (1). The word line trenches are respectively filled with a word line (W) and a protective structure (S) arranged thereover. Transistor source/drain areas (S/D1, SD/2) are disposed in an adjacent position to a surface (F) of the substrate and protrude into the substrate (1) to a lesser degree than the word lines (W). A common source/drain area (SD1) which is connected to a bit line (B) is shared between two adjacent transistors. The remaining source/drain areas (S/D2) of the transistors are connected to capacitors (Ko).

Description

description

DR _A M cell arrangement and method for its production

The invention relates to a DRAM cell arrangement, i. H. a memory cell array with dynamic random access.

A so-called Em transistor memory cell, which comprises a transistor and a capacitor, is almost exclusively used as the memory cell of a DRAM cell arrangement. The information of the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor, so that when the transistor is driven via a local line, the charge of the capacitor can be read out via a bit line.

The general aim is to produce a DRAM cell arrangement that has a high packing density.

Such a DRAM cell arrangement is described, for example, in M. Aoki et al., "Fully Self-Aligned 6F ² Cell Technology for Low Cost 1 Gb DRAM", Symposium on VLSI Technology Digest of Technical Papers (1996), 22. Thermal oxidation produces stripe-shaped insulating structures in a substrate that define active areas of transistors. A surface of the substrate is covered with a gate dielectric. Word lines are then produced which run transversely to the insulating structures and are covered with silicon nitride. Source / drain regions of the transistors are produced between the word lines and the insulating structures. A first insulating layer is deposited in which contact holes are produced which sometimes extend to one of the source / drain regions. Subsequently, msitu doped polysilicon is deposited to such a thickness that the contact holes are not filled. A second insulating layer is deposited that fills the contact holes. Every third along an isolating _S tructure adjacent contact hole is opened again and filled with further situ doped polysilicon, are generated so that Kon ^¬ contacts. The second insulating layer, parts of the polysilicon, which are arranged over the word lines, and the first insulating layer are removed. Ov ^¬ rigbleibendes polysilicon in the contact hole punches, m which no contacts were generated form first capacitor electrodes of the capacitors of the memory cells. A capacitor dielectric and second capacitor electrodes arranged above it are generated and by a third insulating one

Layer covered. The third insulating layer creates depressions that expose the contacts. Then bit lines are generated which adjoin the contacts. Every third word line, which is arranged between two source / dra regions, which are "each connected to a capacitor, is connected to a potential such that no current can flow between these source / dram regions. These word lines act as isolations ,

German patent DE 44 08 764 C2 describes a DRAM cell arrangement in which first trenches, which run essentially parallel to one another, and second trenches running transversely thereto are provided in a substrate. A word line, which is separated from the substrate by a gate dielectric, is sometimes arranged in the lower parts of the second trench. The first trenches outside the word lines are filled with insulating material. Between the second trench and the first trench, source / dram regions of transistors are arranged in the substrate, which adjoin a surface of the substrate. The source / dram regions have the shape of an upturned U and adjoin the flanks of the second trench up to the lower regions of the second trench. Every third of the source / dram regions that are adjacent to one another along a first trench is connected to a bit line that runs parallel to the first trench. The remaining source / dram areas are covered with a capacitor dielectric over which a thin conductive one Layer, the upper areas of the word line ^{trenches ¬} and serves as a capacitor plate, arranged. The capacitor dielectric is likewise arranged in the upper regions of the word line trench and separates the source / dram regions which are not connected to the bit lines and act as capacitor electrodes from the capacitor plate. Those word lines that are between two of the source / dram regions, which act as capacitor electrodes, are connected to a fixed potential, so that no current flows between these source / dram regions. These word lines therefore serve to isolate adjacent memory cells.

The invention is based on the problem of specifying a DRAM cell arrangement which, compared to the prior art, has improved electrical properties with a high packing density at the same time. A method for producing such a DRAM cell arrangement is also to be specified.

The problem is solved by a DRAM cell arrangement in which first trenches, which run essentially parallel to one another, and second trenches, which run transverse to the first trenches and essentially parallel to one another, are provided in a substrate. The second trenches are subdivided into m word line trenches which are provided with a gate dielectric and m each of which a word line is arranged, and isolation trenches which are filled with insulating material. Insulating protective structures are arranged above the word lines in the word line trenches which, together with the word lines, fill the word line trenches. One of the word line trenches is adjacent to another of the word line trenches and to one of the isolation trenches. One of the isolation trenches is adjacent to two of the word line trenches. The first trenches are filled with insulating material outside the word line trenches. First source / dram regions of transistors are arranged in the substrate, _d ie to a surface of the substrate adjacent a sentlichen in we ^¬ homogeneous vertical thickness, ie, a thickness perpendicular ^¬ right to the surface of the substrate, comprise less deep m the substrate extend as the word lines are connected to lines with bit, and in each case tung dig two of the wordline ^¬ and adjacent to two of the first trench. In the sub dram regions are ^¬ strat second source / of the transistors being ^¬ arranged adjacent to the surface of the substrate have a substantially homogeneous vertical thickness less deep m the substrate extend as the word lines are connected to capacitors, and each of one of the word line trenches, adjoin one of the isolation trenches and two of the first trenches.

The bit lines run across the word lines.

The problem is also solved by a method for producing a DRAM cell arrangement, in which first trenches which run essentially parallel to one another and second trenches which run transversely to the first trenches and essentially parallel to one another are produced in a substrate become. Some of the second trenches, which are referred to as word line trenches, are provided with a gate dielectric and the remaining of the second trenches, which are referred to as isolation trenches, are filled with insulating material, one of the word line trenches being connected to another of the word line trenches and to one of the Isolation trench is adjacent, and one of the isolation trench is adjacent to two of the word line trenches. A word line and an insulating protective structure arranged above it are generated in the word line trenches, which together fill the corresponding word line trench. The first trenches are filled with insulating material outside the word line trenches. The first source / dram regions of transistors are produced in the substrate in such a way that they adjoin a surface of the substrate, have an essentially homogeneous vertical thickness, and extend less deep into the substrate tung dig as _d ie word line trenches and in each case two of the wordline ^¬ and adjacent to two of the first trench. There he joined generated ^¬ the bit lines and ebieten to the first source / dram _G. In the substrate dram regions of the transistors are second source / generated so that they at the SURFACE ^¬ surface of the substrate adjacent which have a substantially homogeneous vertical thickness less deeply extend into the substrate than the word line trenches and in each case to one of the word line trenches to one of the isolation trenches and adjoin two of the first trenches. Capacitors are generated and connected to the second source / dram regions.

A memory cell of the DRAM cell arrangement comprises one of the transistors and an associated capacitor. The isolation trenches separate adjacent memory cells from one another along a first trench. The first trenches separate adjacent memory cells from one another along a word line trench.

The vertical thickness of one of the source / dram regions can vary slightly locally. Such fluctuations are e.g. to be attributed to the not exactly defined implantation depth during the generation of the source / dram region or to statistical deviations during the diffusion of the dopant of the source / dram region.

Channel areas of the transistors are U-shaped. Despite the high packing density of the DRAM cell arrangement, i.e. small space requirement per memory cell, the channel length of the transistors can be increased via the depth of the word line trench, and short channel effects can thereby be avoided.

Since no word lines which are kept at a fixed potential are used to separate adjacent memory cells, capacitances which are caused by such word lines and adjacent conductive structures, such as, for. B. bit lines or source / dram areas are avoided. This leads to improved electrical properties of the DRAM cell arrangement. For example, switching ^¬ shorten times of the transistors. With such word lines, separate connections of these word lines via which these word lines are kept at the fixed potential are also eliminated, so that a periphery of the DRAM cell arrangement can have a particularly small space requirement.

The DRAM cell arrangement can be produced with a high packing density because, on the one hand, the source / dram regions of the

Transistors can be produced in a self-aligned manner with respect to the word line trench and the first trench, and contacts between the source / dram regions and the bit lines or the capacitors can be produced with a high adjustment tolerance.

For this purpose, after the transistors have been produced, an intermediate oxide can be deposited on the surface of the substrate by opening the contact hole to the source / dram regions. The adjustment tolerance of the contact holes is large because the

Protective structures cover the word lines, and the intermediate oxide can be selectively etched to the protective structures. Short circuits between the word lines and the contacts that are generated in the contact holes are thereby avoided.

To simplify the process, it is advantageous to produce the capacitors directly in the contact holes, so that corresponding contacts can be dispensed with. The second source / dram areas can also act as capacitor electrodes of the capacitors.

It is within the scope of the invention to generate the bit lines in such a way that they adjoin the first source / dram region, so that corresponding contacts can be dispensed with. In this case, a trench is etched in the intermediate oxide for each bit line and filled with conductive material. A particularly high packing density is achieved if the widths of the first trenches, the distances of the first trenches from one another, the widths of the second trenches and the distances of the second trenches from one another have the same value and are preferably equal to the minimum structural size F which can be produced using the technology used.

It is within the scope of the invention to see a larger distance between an isolation trench and an adjacent trench

To provide word line trenches. The capacitors can then be produced with a larger capacitance. For example, its horizontal cross section can be enlarged in this case. A depression can also be produced in the substrate, which cuts through the second source / dram region and in which the capacitor can be arranged.

For analog reasons, it can be advantageous if the distances between adjacent word lines are particularly large. The bit line can then be arranged in a further trench which cuts through the first source / dram region.

The isolation trenches and the word line trenches can be filled as follows: First, the second trenches are filled with insulating material. A strip-shaped mask is then produced, the strip of which covers every third of the second trenches, namely the isolation trenches. Using the mask, exposed insulating material is removed from the uncovered second trench, namely the word line trench. The gate dielectrics and the word lines are then produced in the second trench, from which the insulating material has been removed.

It is within the scope of the invention to first create the first trenches and fill them with the insulating material. An auxiliary layer is then applied and structured in the form of a strip. Between the stripes of the structured Auxiliary layer, which acts as a mask, the second digger is created. Preferably, the auxiliary layer additionally serves to strip-shaped mask as a mask during the removal of iso ^¬ lierenden material from the word line trench is removed. The auxiliary layer prevents the insulating material from remaining outside the word line trenches in the first trench. Since the first trenches are created first, they can be deeper than the second trenches, so that leakage currents between source / dram regions adjacent to one another along the word line can be prevented. In this case, the insulating material on the bottom of parts of the first trenches where the first trenches and the word line trenches cross is not removed.

Alternatively, the second trenches are first created. To

Generation of the word lines and the protective structures is selectively etched with the aid of a further strip-shaped mask, the strips of which run transversely to the second trench, so that the first trenches are produced, which, however, are not continuous due to the protective structures.

The substrate consists of semiconductor material, e.g. Silicon.

The word lines can be made of doped polysilicon or of another conductive material, such as. B. metal or metal silicide.

If the intermediate oxide consists of Si02, it is advantageous for selective etchability if the protective structures consist of silicon nitride.

An exemplary embodiment of the invention is explained in more detail below with reference to the figures: FIG. 1 shows a plan view of a substrate after the first trenches have been produced.

FIG. 2 shows a cross section through the substrate after an auxiliary layer, second trench and a mask have been produced.

FIG. 3a shows the cross section from FIG. 2, after gate dielectric, word lines, protective structures, source / dram regions of transistors, an intermediate oxide,

Contacts, capacitors and bit lines were created.

FIG. 3b shows the top view of FIG. 1 after the process steps from FIG. 3a, with the contacts that

Word lines, the first trench and the second trench are shown.

The figures are not to scale,

The starting material is a substrate 1, which contains p-doped silicon. With the aid of a first mask made of photoresist (not shown), approximately 400 nm deep first trenches G1 are produced in the substrate 1. The first trenches Gl are approximately 150 nm wide and are spaced approximately 150 nm apart. The first trenches G1 are filled with insulating material by depositing S1O2 in a thickness of approximately 90 nm and planarizing by chemical mechanical polishing until the substrate 1 is exposed (see FIG. 1).

To produce an auxiliary layer H, silicon nitride is deposited to a thickness of approximately 50 nm (see FIG. 2).

With the help of a second strip-shaped mask made of photoresist (not shown), the strips of which run transversely to the first trench G1, silicon nitride, S1O2 and silicon are etched, so that approx nm deep second trench G2 are generated. The second trenches G2 are approximately 150 nm wide and are spaced approximately 150 nm apart.

The second trenches G2 are filled with insulating material by depositing S1O2 in a thickness of approximately 90 nm and chemical-mechanically polishing until the auxiliary layer H is exposed.

With the aid of a third strip-shaped photoresist mask P, the strips of which run parallel to the second trench G2, are approximately 300 nm wide and covers every third of the second trench G2, S1O2 is selectively etched to silicon nitride. The insulating material is retained in the second trench G2, which are covered by the third photoresist mask P. These second trenches G2 are referred to below as isolation trenches. The insulating material is removed from the remaining second trenches G2, which are referred to below as word line trenches, until the bottom of the word line trenches are exposed (see FIG. 2).

The third photoresist mask P is removed.

Thermal oxidation produces an approximately 6 nm thick gate dielectric GD which covers the flanks and the bottom of the word line trenches (see FIG. 3a).

To produce word lines W m the word line trench, polysilicon is deposited in a thickness of approximately 30 nm and above it WSi m in a thickness of approximately 60 nm and planarized by chemical-mechanical polishing until the auxiliary layer H is exposed. Then WSi and polysilicon are etched back until an upper surface of the word lines W is approximately 50 nm below a surface F of the substrate 1 (see FIG. 3a).

The auxiliary layer H is z. B. hot H3PO4 removed. Subsequently, silicon nitride is deposited in a thickness of approx. 70 nm and planed by chemical-mechanical polishing until the surface F of the substrate 1 is exposed. As a result, the word lines W become insulating

Protective structures S are generated which, together with the word lines W, fill the word line trenches (see FIG. 3a).

By implantation with n-doping ions, first source / dram regions S / D1 and second source / dram regions S / D2 of transistors are produced between the first trench G1 and the second trench G2. The source / dram areas S / Dl, S / D2 are approximately 80 nm deep and have an essentially homogeneous vertical, ie. H. thickness running perpendicular to the surface F of the substrate 1. The source / dram regions S / Dl, S / D2 extend less deep into the substrate 1 than the word line trenches and thus as the word lines W, so that when the transistors are driven, a channel is produced which runs in a U-shape. A current consequently flows both on the flanks and on the bottom of the word line trenches. Two transistors are surrounded by two mutually adjacent first trenches Gl and two mutually adjacent isolation trenches. The first source / dram regions S / DL are each arranged between two word line trenches and each act as a common source / dram region of two of the transistors.

In order to produce an intermediate oxide Z, S1O2 is deposited with a thickness of approx. 1000 nm (see FIG. 3a).

With the help of a fourth mask made of photoresist (not shown), contact holes are produced which each expose one of the source / dram regions S / Dl, S / D2 of the transistors (see FIGS. 3a and 3b). The intermediate oxide Z is selectively etched to the protective structures S. Contacts KB to bit lines B are produced in the contact holes which expose the first source / dram regions S / DL (see FIGS. 3a and 3b). Contacts KS to capacitors Ko are produced in the contact holes which expose the second source / dram regions S / D2 (see FIGS. 3a and 3b).

Then, in a known manner, capacitors Ko (shown schematically in FIG. 3a) and bit lines B, which run transverse to the word lines W, are produced.

Many variations of the exemplary embodiment are conceivable, which are also within the scope of the invention. The dimensions of the layers, trenches, structures, contacts and areas can be adapted to the respective requirements. The same applies to the choice of materials.

Claims

claims

1. DRAM cell arrangement,

- In the in a substrate (1) arranged next to each other he ^{¬ first} trench (Gl), which run essentially parallel to each other, and next to each other second trench (G2), which run transversely to the first trench (Gl) and substantially parallel to each other , are provided, - in which the second trenches (G2) are divided into m word line trenches which are provided with a gate dielectric (GD) and which each have a word line (W), and m isolation trenches which are filled with insulating material , in which insulating structures (S) are arranged above the word lines (W) in the word line trenches and fill the word line trenches together with the word lines (W),

in which one of the word line trenches is adjacent to another of the word line trenches and to one of the isolation trenches,

in which one of the isolation trenches is adjacent to two of the word line trenches,

- in which the first trenches (Gl) outside the word line trenches are filled with insulating material,

- in which in the substrate (1) first source / dram regions (S / Dl) and second source / dram regions (S / D2) of transistors are arranged which adjoin a surface (F) of the substrate (1), have an essentially homogeneous vertical thickness and extend less deeply into the substrate (1) than the word lines (W),

in which the first source / dram regions (S / DL) are connected to bit lines (B) and in each case two of the transistors are assigned and adjoin two of the word line trenches and two of the first trenches (Gl),

in which the second source / dram regions (S / D2) are connected to capacitors (Ko) and are each connected to one of the word line trench, adjoin one of the isolation trenches and two of the first trenches (Gl).

2. Cell arrangement according to claim 1, wherein the capacitors (Ko) and the bit lines (B) are arranged over the substrate (1).

3. Cell arrangement according to claim 1 or 2,

- the widths of the first trenches (Gl) and widths of the second trenches (G2) match,

the distances between the first trenches (Gl) which are adjacent to one another are the same,

the distances between the word line trenches which are adjacent to one another and between which none of the isolation trenches are arranged are the same,

- In which contacts (KB) are arranged on the first source / dram areas (S / DL), whose cross sections parallel to the surface (F) with cross sections parallel to the surface (F) of the first source / dram areas (S / Dl) agree,

- In which the contacts (KB) are connected to the bit lines (B).

4. Cell arrangement according to claim 3, wherein the distances between the second trenches (G2) which are adjacent to one another are equal.

5. Method for producing a DRAM cell arrangement,

- In the m a substrate (1) side by side arranged first trench (Gl), which run essentially parallel to each other, and side by side arranged second trench (G2), which run transversely to the first trench (Gl) and essentially parallel to each other - in which some of the second trenches (G2), which are referred to as word line trenches, are provided with a gate dielectric (GD) and the rest of the second trenches (G2), which are referred to as the isolation trench to be filled with iso ^¬ lierendem material, one of said word line trench adjacent to another of the word line trench and one of the isolation trench, and the isolation trench to two of the word line trench adjacent

- At the m the word line trench one word line each

(W) and an insulating protective structure (S) arranged above it, which together fill the corresponding word line trench,

in which the first trenches (Gl) outside the word line trenches are filled with insulating material,

in which first source / Dra regions (S / Dl) of transistors are produced in the substrate (1) in such a way that they adjoin a surface (F) of the substrate (1) and have an essentially homogeneous vertical thickness, reach the substrate (1) less deeply than the word line trenches and each of which two of the transistors are assigned and adjoin two of the word line trenches and two of the first trenches (Gl),

in which bit lines (B) are generated and connected to the first source / dram regions (S / Dl),

in which second source / dram regions (S / D2) of the transistors are produced in the substrate (1) in such a way that they adjoin the surface (F) of the substrate (1) and have an essentially homogeneous vertical thickness, reach into the substrate (1) less deeply than the word line trenches and each adjoin one of the word line trenches, one of the isolation trenches and two of the first trenches (Gl), in which capacitors (Ko) are produced and connected to the second source / dram Areas (S / D2).

6. The method according to claim 5,

- in which the second trenches (G2) are filled with insulating material, in which a stripe-shaped mask (P) is produced, the stripe covering every third of the second trenches (G2),

in which exposed insulating material is removed into the second trench (G2) with the aid of the mask (P),

- In which the gate dielectric (GD) and the word lines (W) m the second trench (G2), from which the insulating material has been removed, are generated.

7. The method according to claim 5 or 6,

in which the first trenches (Gl) and the second trenches (G2) are produced in such a way that widths of the first trench (Gl) and widths of the second trench (G2) match one another,

in which the first trenches (Gl) are produced in such a way that distances between adjacent first trenches (Gl) are the same,

in which the word line trenches are produced in such a way that distances between adjacent word line trenches, between which no isolation trenches are arranged, are equal,

- With the intermediate oxide (Z) is applied to the substrate (1),

- In which, through masked etching of the intermediate oxide (Z) selectively to the protective structures (S), contact holes are produced up to the first source / dram areas (S / Dl), m contacts (KB) are generated, their cross sections, which are parallel to the surface (F) are parallel to the surface (F) parallel cross sections of the first source / dram areas (S / Dl), - in which the bit lines (B) are connected to the contacts (KB).

8. The method according to claim 7, wherein the bit lines (B) and the capacitors (Ko) are produced over the substrate (1).

9. The method according to any one of claims 6 to 8, - in which the first trenches (Gl) are first created and filled with the insulating material,

- in which an auxiliary layer (H) is applied and structured in the form of a strip,

in which the second trenches (G2) are produced between the strips of the structured auxiliary layer (H),

- in which the second trenches (G2) are filled with the insulating material, - in which the exposed insulating material in the second trenches (G2) is selectively removed from the auxiliary layer (H) with the aid of the mask (P).