WO2001001228A1

WO2001001228A1 - System lsi

Info

Publication number: WO2001001228A1
Application number: PCT/JP1999/003476
Authority: WO
Inventors: Takanori Shimura; Keiko Komatsu
Original assignee: Hitachi, Ltd.
Priority date: 1999-06-29
Filing date: 1999-06-29
Publication date: 2001-01-04
Also published as: TW455758B; AU4290999A

Abstract

A semiconductor device including a plurality of function units connected mutually by internal buses comprise operation mode output means provided in each of the function units and adapted to produce a request for a change from a mode of operation speed to another mode depending on data being processed; and power processing speed control means for controlling the clock frequency signal for each of the function units and the bus occupation time depending on the request for a change of operation mode so that the sum of the power consumption of the active ones of the function units may not exceed the maximum power consumption allocated to the semiconductor device. The semiconductor device can comprise a large number of function units without employing a package with high cooling efficiency or forced cooling.

Description

Description System LSI Technical Field

The present invention relates to a system-on-a-chip technology for integrating a circuit having a system function on a single chip. In particular, the present invention includes a plurality of function units, and performs a plurality of types of data processing using those function units. Semiconductor device. Background art

The system LSI (Large Scale Integrated circu) is equipped with multiple function units and performs various data processing by connecting them with a bus (common line). Such a system LSI generally has a large integration scale, and generally consumes a large amount of power. Therefore, the power consumption limit determined by the package and cooling conditions is set for the chip. For example, in a normal plastic package, the upper limit is about 1.5 watts. Beyond this, the operating temperature of the chip rises and LSI malfunctions. For this reason, conventionally, the sum of the maximum possible power consumption of all the functional units is regarded as the power consumption of the system LSI, and the LSI has been designed so that this does not exceed the limit power consumption.

Designs have also been made to reduce the power consumption of powered-on system LSIs within the limit power consumption range. Since many system LSIs are composed of CMOS (Complementary Metal Oxide Semiconductor) circuits, lowering the clock frequency reduces the power consumption of CMOS circuits. Therefore, a functional unit that is not related to a specific operation, Control was performed to lower the frequency of the clock signal to the function unit or to stop the clock. Since each functional unit operates in response to a CPU instruction, such low power consumption control is performed on a functional unit that does not need to execute the instruction. For example, Japanese Unexamined Patent Publication No. Hei 8 (1995) -27,479 discloses that the clock frequency of a function unit that executes a CPU instruction is increased and the clock frequency of a function unit that does not need to execute a CPU instruction is decreased. To reduce power consumption.

In recent years, the progress in the multimedia field has been remarkable, and accordingly, there has been an increasing demand for a system LSI that integrates a microcomputer having both high performance and low power consumption and a dedicated function unit.

Also, with the advance of semiconductor manufacturing technology, the number of gates that can be integrated has exceeded 100,000 gates, and many functional units are being integrated on the same chip. For this reason, even if the power consumption of each functional unit is small, the power consumption increases if all the integrated functional units operate simultaneously, and the maximum sum of the power consumption of all the functional units is the limit of the LSI. It is becoming increasingly difficult to design LSIs that do not exceed power consumption.

For this reason, in order to increase marginal power consumption, it is unavoidable to adopt an expensive package with a heat dissipation effect or forced cooling such as air cooling or water cooling, and lower costs such as inexpensive packages and use in no wind conditions. It is becoming impossible to use the means. Disclosure of the invention

It is an object of the present invention to provide a semiconductor device capable of mounting a large number of functional units without using a package having a high heat radiation effect or forced cooling. A plurality of functional units mounted on a system LSI usually include a functional unit that can execute an instruction from a CPU at a lower operating speed than other functional units. For example, in system LSIs used for digital TVs and game consoles in the multimedia field, various types of functional units such as graphics, image processing, audio processing, and peripheral interfaces are integrated. Of these, graphics and peripheral interfaces are often allowed to slow down. On the other hand, real-time processing is often performed for image processing and audio processing, and it is often not allowed to change the set operation speed.

Furthermore, the operation speed of the function unit is set according to the content of the data processing. For example, in image processing, different operation speeds are set according to the resolution of an image to be processed and the degree of image compression.

In the following, a state in which operation is performed at a certain speed is referred to as an operation mode at that speed. For example, if the speed is high, medium, or low, and the functional unit is operating at medium speed, the functional unit is in medium operating mode.

The present inventor has determined that even if the sum of the maximum possible power consumption of all the function units exceeds the limit power consumption, the sum of the instantaneous power consumption of the operating function units (hereinafter, this sum is referred to as `` peak power consumption '') It was found that such peak power consumption could be set by controlling the operating speed for each functional unit that executes processing. At that time, priorities shall be set according to the possibility of changing the operation speed according to the processing content. That is, when the operation speed cannot be changed, the priority becomes higher, and when the operation speed can be changed, the priority becomes lower.

The present invention has been made from the above viewpoints. That is, the purpose is achieved In order to achieve this, the semiconductor device of the present invention provides an operation mode provided in each of a plurality of function units, which outputs a request for changing from an operation mode of an operating speed to another operation mode according to data processing contents. The output unit and the function unit for executing the processing so that the total power consumption of the function unit for executing the processing in the plurality of function units does not exceed the limit power consumption given to the semiconductor device. And a power processing speed control means for controlling the frequency of the clock signal and the bus occupation time used by the CPU according to the operation mode change request.

If such means are adopted, the function unit operates in the operation mode according to the processing content such as real-time processing, so that many function units can be operated with lower power consumption than their maximum power consumption. This makes it possible to realize a semiconductor device capable of mounting a large number of functional units without using a package having a high heat radiation effect or forced cooling.

The power processing speed control means includes, for example, means for storing information on power consumption, individual bus occupation time, and data processing priority for each operation mode of a plurality of functional units, and using the information, Power consumption and individual bus occupation time are allocated to the function blocks that execute processing in the order of the function blocks with the highest data processing priority, and the frequency of the click signal is set according to the allocated power consumption. In addition, the assigned individual bus occupation time is set as the bus occupancy time, and the clock control signal for operating at the set frequency of the clock signal and the bus occupancy time control signal for using the set bus occupancy time are described above. It can be constituted by means for supplying a function unit for executing processing.

Further, the means for storing information is constituted by a power processing speed control table for storing the information, and the means for supplying a clock control signal and a bus occupation time control signal to a function unit for executing the processing is provided by: clock It can be constituted by a quick control circuit and a bus control circuit which generate and output a control signal and a bus occupation time control signal.

Each function unit includes, in addition to the operation mode output means, for example, a clock switching means for receiving a quick control signal and selecting a clock signal of a corresponding frequency from a plurality of clock signals. It can be configured using data processing means that operates with the clock signal obtained and sets the transfer rate of data transmitted to the bus in accordance with the bus occupation time control signal.

In the above description, the storage means of the power processing speed control means collectively stores the information of each functional unit. However, separately from this, the information of each functional unit is stored in a storage device (external to the semiconductor device). The power processing speed control means reads the information stored in the external storage device at the time of initialization, stores the information in the storage means, and uses the stored information to execute the clock of the processing execution function unit. It is possible to control the frequency and the bus occupation time. That is, the power processing speed control means uses the information stored in the storage means to allocate and allocate the power consumption and the individual bus occupation time to the processing execution function blocks in order of the function blocks having the highest data processing priority. The frequency of the clock signal is set according to the power consumption, and the allocated individual bus occupancy time is set as the bus occupancy time. The clock control signal for operating at the set clock signal frequency and the set bus occupancy are set. A bus occupancy time control signal for using the time is supplied to the processing execution function unit.

Further, each of the functional units has a sub-storage unit, and stores its own information in the sub-storage unit, and the power processing speed control unit stores the information in the sub-storage unit at initialization. The information of the processing execution unit is read using the stored information and stored in the storage unit. It is possible to control the frequency and the bus occupation time.

That is, the power processing speed control means uses the information stored in the storage means to allocate the power consumption and the individual bus occupation time to the processing execution function blocks in order of the function blocks having the highest priority of the data processing, A clock control signal for setting the frequency of the click signal in accordance with the allocated power consumption, setting the allocated individual bus occupation time as the bus occupation time, and operating at the set clock signal frequency. In addition, a bus occupancy time control signal for using the set bus occupancy time is supplied to the processing execution function unit. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a block diagram of a system LSI for explaining a first embodiment of a semiconductor device according to the present invention, and FIG. 2 is a block diagram of a clock switching circuit used in the first embodiment. FIG. 3 is a diagram for explaining information stored in a power processing speed control table used in the first embodiment. FIG. 4 is a diagram illustrating power consumption in the first embodiment. FIG. 5 is a flowchart for explaining a sequence of bus occupancy time control, FIG. 5 is a flowchart for explaining power consumption control in the first embodiment, and FIG. FIG. 7 is a flowchart for explaining bus occupation time control in the embodiment; FIG. 7 is a block diagram for explaining a bus control circuit used in the first embodiment; FIG. Circuit diagram for explaining the voltage detection circuit used in the first embodiment FIG. 9 is a block diagram of a system LSI for explaining a second embodiment of the present invention, and FIG. 10 is a block diagram of a system LSI for explaining a third embodiment of the present invention. FIG. 11 is a block diagram, and FIG. 11 is a diagram for explaining information stored in a power processing speed storage circuit of the functional unit used in the third embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, a semiconductor device according to the present invention will be described in more detail with reference to some embodiments shown in the drawings. The same symbols in FIGS. 1 to 11 indicate the same or similar objects.

(Example 1)

FIG. 1 is a block diagram of a system LSI showing a first embodiment of the present invention. The system LSI includes a clock generation circuit 101, functional units 104 to 107, a power processing speed control circuit 109, and a voltage detection circuit 110. Specifically, the function unit 104 is a micro computer (hereinafter referred to as “microcomputer”), the function unit 105 is an image processing circuit, the function unit 106 is an audio processing circuit, and the function unit 1 07 is a peripheral input / output circuit. The function units 104 to 107, the power processing speed control circuit 109 and the voltage detection circuit 110 are interconnected by an internal bus 10.

The clock generation circuit 101 is composed of a clock oscillator 102 and a frequency divider 103. The output signal of the clock oscillator 102 is divided by a frequency divider 103 into high-speed to low-speed clocks. The signal is frequency-converted to 115a to 115c and distributed to the function unit 104 to 107. There are three types of clock speeds used in this embodiment: high speed, medium speed and low speed.

The function unit 104 to 107 is a clock switching circuit 211 to 217, a data processing circuit 222 to 227, and an operation mode output circuit 304 to 300. It is composed of 7 and.

The clock switching circuit 2 14 to 2 17 receives a predetermined number of input clocks 1 15 a to 1 15 c in accordance with the clock control signal 4 14 to 4 17 from the power processing speed control circuit 109. Select a clock. The data processing circuits 224 to 227 perform necessary arithmetic processing and data processing in the functional unit. The processing speed at this time depends on the clock frequency selected by the clock switching circuits 211 to 217. It operates at high speed when a high-speed clock is selected, and operates at low speed when a low-speed clock is selected.

The operation mode output circuit 304 to 307 performs power processing when the operation mode at the speed specified by the clock control signal 414 to 417 does not match the operation mode required according to the processing content. In response to the speed control circuit 109, an operation mode change request signal that requests the function unit 104 to 107 to operate in which operation mode (high speed, medium speed, or low speed) is output to the operation mode output signal. Output as 4 4 4 to 4 4 7.

The power processing speed control circuit 109 is composed of a power processing speed control table 404 as a storage means, a clock control circuit 401, and a bus control circuit 402, and is output from each function unit. The operating clock frequency and bus occupancy time are controlled according to the operation mode change request signal 444 to 449. The power processing speed control table 404 stores information on power consumption, individual bus occupation time, and processing priority in accordance with the operation mode of each functional unit.

The clock control circuit 410 refers to the operation mode change request signals 4444 to 447 output from each function unit, and the power consumption and processing priority in the power processing speed control table 4404. However, the operation unit of each function unit is allowed to consume a large amount of power for the function unit having a high priority of processing and to consume less power for the function unit having a low priority. Controls the mouth frequency.

The bus control circuit 402 determines the individual bus occupation time and the processing priority of the power processing speed control table 400, By referring to the operating clock frequency (operating mode) of the functional unit, more bus occupation time is given to the unit with higher processing priority, and the bus occupation time is given to the functional unit with lower priority. The bus occupancy time is controlled so as to be shorter, and the bus transfer speed is controlled accordingly.

The voltage detection circuit 110 is a circuit that compares a reference voltage Vref supplied from outside the LSI with a power supply voltage of the LSI to calculate an actual operating voltage of the LSI. Hereinafter, the operation of each circuit will be described.

In the initial state of operation, the functional units 104 to 107 operate with a low-speed clock with low power consumption, that is, are in a low-speed operation mode. When there are the following factors, each function unit changes the operation mode according to the factors and responds to the processing request. Factors that change the operation mode in each function unit include the following.

In the case of the microcomputer 104, the operation mode changes to an operation mode that requires high-speed processing in response to an external interrupt request (640) from the keyboard or peripheral device. Also, when the microcomputer 104 executes a processing program requiring high-speed or medium-speed processing, the operation mode is changed to an operation mode requiring high-speed or medium-speed processing.

The operation mode of the image processing circuit 105 changes when parameters of image processing, such as image quality, pixel size, number of frames, and encoding method, are set by the microcomputer 104. When processing high-quality images, high-speed processing is required. In addition, when performing processing by thinning out frames or fields or performing processing that reduces the image quality, image processing can be performed at a relatively low speed.

In the case of the audio processing circuit 106, the processing speed differs depending on the sound quality and the encoding method. When encoding and decoding high-quality speech, the operation mode changes to a high-speed operation mode. Also, in the case of audio processing, real-time processing is sometimes necessary. Yes, in order to realize real-time processing, it is necessary to raise the processing priority and perform processing in priority to other function units.

In the case of the peripheral input / output circuit 107, the operation mode changes depending on the data transfer request (607) from the peripheral device network and the amount of data transmitted per unit time. If the amount of data is large, high-speed processing is required. If the amount of data is small or the network is slow, low-speed processing is sufficient.

When the function units 104 to 107 receive these request signals internally, the function units 104 to 407 transmit the operation mode change requests from the operation mode output circuits 304 to 307 to the power processing speed. Output to control circuit 109.

The power processing speed control circuit 109 responds to the operation mode change request from each function unit 444 to 447, and follows the priority of the processing of each function unit, and Make changes so that the operating clock frequency is increased and the bus occupation time is allocated longer.

In addition, when the power processing speed control circuit 109 once enters the high-speed operation mode and subsequently sends a request to change to a mode in which each function unit operates at a low speed, the power processing speed control circuit 109 operates the function unit. Make changes so that the clock frequency is reduced and the bus occupation time allocation is shortened.

FIG. 2 shows the configuration of the clock switching circuit 2 14. The figure also shows the waveforms of the three types of clock signals 115a to 115c. The frequency of the high-speed clock signal 115a is 2 fc, twice that of the clock frequency fc of the medium-speed clock signal 115b, and the frequency of the low-speed clock signal 115a is 1/2 times fc / 2. The clock switching circuit 214 includes a clock selection circuit 234, and switches among three types of clocks 115a to 115c using a clock control signal 414.

The clock switching control signal 4 14 is a 2-bit signal, and the 2 bits The speed is set as follows.

(0, 0): Medium speed clock (1 15 b)

(0, 1): Low-speed clock (1 15 c)

(1, 0): High-speed clock (1 15 a)

(1, 1): Prohibited (no clock signal selected)

In this example, the magnification is set to double and 1/2 times, but the clock ratio is not specified to this.

Further, in the present embodiment, the explanation has been made such that the clock frequency dividing circuit 103 is arranged in the clock generating circuit 101. However, the clock frequency dividing circuit 103 is connected to each of the clock switching circuits 214-2. It is also possible to switch the clock by arranging it in 17.

Next, the power processing speed control circuit 109 will be described. First, a description will be given of a process of setting in the power processing speed control table 404. FIG. 3 shows an example of data stored in the power processing speed control table 404. There are three operation modes: high-speed clock mode (200 MHz), medium-speed clock mode (100 MHz), and low-speed clock mode (50 MHz). Power consumption in each mode is 451 a, The bus occupation time 45 1 b and the processing priority 45 1 c are stored. In this example, the high-speed clock mode is 200 MHz, the medium-speed clock mode is 100 MHz, and the low-speed clock mode is 50 MHz.

Power consumption 451a shows the maximum power consumption in each operation clock mode.

For the bus occupation time 45 1 b, the time used in the unit time for managing the bus is registered in%. For example, if the unit time is 10 microseconds, 20% means that every 10 microseconds uses 2 microseconds It is shown that.

In this example, the processing priorities 4 5 1 c are indicated by 10 levels from 1 to 10. 1 is the highest priority, and 10 is the lowest setting. When an operation mode change request is output from a plurality of function units at the same time, power consumption and bus occupation time are allocated in order from the function unit having the highest priority in this processing.

Lower-priority function units were used by higher-priority function units based on the total power consumption minus the power consumption used by higher-priority function units, and overall bus occupation time. The power consumption and the bus occupation time are assigned to the remaining bus occupation time after subtracting the bus occupation time, and the operation mode (low operation clock frequency) operates within the power consumption and the bus occupation time. become.

Next, a method of prioritizing processing will be described. Priorities are set higher for those that require real-time processing. Necessary conditions for executing the real-time processing include the processing speed and the bus transfer speed (here, the occupied time of the bus is assigned to each functional unit). Both are considered when executing real-time processing.

For example, in image processing, it is necessary to set both the operation speed and the bus transfer speed. Network control does not require calculation speed, but often requires data transfer speed. For audio processing, real-time data transfer without delay is required.

In the present embodiment, the processing priority is different for each operation mode. Therefore, for example, when both the microcomputer 104 and the image processing circuit 105 operate in the high-speed operation mode (200 MHz), the priority of the image processing circuit 105 becomes higher, Microcomputer 104 is in high-speed operation mode (200

MHz) and the image processing circuit 105 is in the medium speed operation mode (100 MHz). , Microcomputer 104 has higher priority. In this way, it is also possible to control by inverting the priority according to the operation mode.

In the present embodiment, the priority of the processing is described with 10 levels, but the method of setting the priority is not specified. For example, the priority may be assigned by eight bits, and in this case, the priority can be selected from 256.

Next, FIG. 4 illustrates a sequence of the power consumption control and the bus occupation time control executed in the present embodiment. The operation mode output signals 4444 to 447 of this embodiment are 2-bit signals, and the requested contents are set as follows.

(0, 0): Medium speed operation mode request

(0, 1): Low-speed operation mode request

(1, 0): High-speed operation mode request

(1, 1): Prohibited

In FIG. 4, at time TO, the microcomputer 104, the image processing circuit 105, and the peripheral input / output circuit 107 operate in the low-speed operation mode, and the audio processing circuit 106 operates in the high-speed operation mode. It is assumed that

At time T1, it is assumed that a data transfer request 607 is input from the peripheral bus to the peripheral input / output circuit 10 #. In response to this request, the peripheral input / output circuit 107 outputs a request for changing from the low-speed operation mode to the high-speed operation mode 447 to the power processing speed control circuit 109.

The power processing speed control circuit 109 receives the operation mode change request 447. The clock control circuit 401 has a circuit for detecting the reception of the operation mode change request 4444 to 47, and upon detecting the reception, immediately starts the operation for generating the clock control signal. Upon receiving the operation mode change request 447, the clock control circuit 410 receives the operation mode change request 447, and stores the power processing speed control table 4404 (see Fig. 3) in the low-speed operation mode of the microcomputer 104. Power consumption (0.15 W) and processing priority (10), and image processing circuit 105 power consumption in low-speed operation mode (0.15W) and processing priority (8) , The power consumption (0.4 W) of the audio processing circuit 106 in the high-speed operation mode, the processing priority (1), and the power consumption of the peripheral output circuit 107 in the high-speed operation mode (0. 2 W) and the processing priority (3) are read out, and the power consumption to be allocated to each functional unit is calculated according to the flowchart in FIG. Details of the flowchart in Fig. 5 will be explained separately.

Here, since the total power consumption (0.9 W) of the four function units 104 to 107 does not exceed the limit power consumption (1.5 W), the operation of the peripheral input / output circuit 107 According to the mode change request, change the operation mode (clock frequency) of the peripheral I / O circuit 107 to the high-speed mode.

Next, in accordance with the operation mode determined by the clock control circuit 401, the bus control circuit 402 operates at the low speed of the microcomputer 104 stored in the power processing speed control table 404 (see FIG. 3). Bus occupation time in operation mode (5%) and processing priority (10), and bus occupation time in image processing circuit 105 in low-speed operation mode (12%) and processing priority (10%) 8), the bus occupation time (5%) of the audio processing circuit 106 in the high-speed operation mode, the processing priority (1), and the bus occupation time of the peripheral output circuit 107 in the high-speed operation mode (40%) and the processing priority (3) are read out, and the bus occupation time to be allocated to each function unit is calculated according to the flowchart in FIG. Details of the flowchart in FIG. 6 will be described separately. Here, the total bus occupation time (62%) of the four function units 104 to 107 does not exceed 100%, so the bus occupation time required for all function units It becomes possible to assign.

Then, at time T2 (Fig. 4), microcomputer 604 receives interrupt 604 It is assumed that the microcomputer 104 outputs a request 444 for changing from the low-speed operation mode to the high-speed operation mode. As in the case of time T1, the power processing speed control circuit 109 controls the microcomputer 104 and other function units based on the power consumption and processing priority corresponding to the operation mode of each function unit. Determines the operation mode (operation clock) of. Also, the bus occupancy time of the microcomputer 104 and other function units is determined from the bus occupancy time corresponding to the operation mode of each functional unit and the processing priority. In this case as well, at time T1, the total power consumption (1.35 W = 0.6 W + 0.15 W + 0.4 W + 0.2 W) is less than the limit power consumption and the bus occupation time Since the sum (77% = 20% + 12% + 5% + 40%) has not reached 100%, the microcomputer 104 transitions to the high-speed operation mode and consumes the microcomputer 104. The power is 0.6 W and the bus occupancy time is 20%.

At time T3, the microcomputer 104 specified that the image processing circuit 105 improve image quality, and the image processing circuit 105 output a request 445 to change from the low-speed operation mode to the high-speed operation mode. And As in the case of the time Tl and the time 時刻 2, the power processing speed control circuit 109 sets the image processing circuit 105 and the other circuits based on the power consumption corresponding to the operation mode of each functional unit and the priority of processing. Determine the operation mode (operation clock) of the function unit. In addition, the bus occupation time of the image processing circuit 105 and other function units is determined from the individual bus occupation time corresponding to the operation mode of each functional unit and the priority of processing.

Assuming that the image processing circuit 105 is changed to the high-speed operation mode, the total power consumption is assumed to be 0.6 W of the microcomputer 104 operating in the high-speed operation mode and operating in the high-speed operation mode. 0.6 W of image processing circuit 105, audio processing circuit operating in high-speed operation mode 0.4 W of peripheral processing circuit 106 operating in high-speed operation mode . Add 2 W and It will exceed the limit power consumption of 1.8 W.

Therefore, control is performed so that the power consumption of the function unit with a low priority is reduced. Assuming that all four function units operate in the high-speed operation mode, the priority of the microcomputer 104 is 4, the priority of the image processing circuit 105 is 2, and the priority of the audio processing circuit 106 is 1, Since the peripheral input / output circuit 107 has a priority of 3, the operation mode of the microcomputer 104, which has the lowest priority, is reduced from high speed to medium speed. As a result, the power consumption of the microcomputer 104 decreases from 0.6 \ ¥ to 0.3 W, so that the total power consumption becomes 1.5 W, which is below the limit power consumption.

The bus occupation time is 50%, 5%, 40% for the image processing circuit 105, the audio processing circuit 106, and the peripheral input / output circuit 107 that operate in the high-speed operation mode. Since the microcomputer 104 operating in the high-speed operation mode is 10%, the total sum exceeds 105%. For this reason, the operation mode of the microcomputer 104 with low processing priority is changed from medium speed to low speed, the bus occupation time is set to 5%, and the total bus occupation time is set to 100% or less.

Since the operation mode of the microcomputer 104 becomes slow, the power consumption of the microcomputer 104 becomes 0.15 W.

As a result, at time T3, the operation mode of each function unit is such that the microcomputer 104 is in the low-speed operation mode and the image processing circuit 105, the audio processing circuit 106, and the peripheral input / output circuit 107 are in the high-speed operation mode. The operation mode is set.

In the present embodiment, the microcomputer 104 is changed to the low-speed operation mode at time T3 to reduce the bus occupation time to 100% or less, but the microcomputer 104 remains in the medium-speed operation mode. The control sequence can be easily changed to change the peripheral input / output circuit 107 having the second lowest priority from the high-speed operation mode to the medium-speed operation mode.

Thus, the power consumption of each function unit, the bus occupation time, and the priority of processing The operation mode of each function unit is determined from the order, and optimal control can be performed within a range where the power consumption of the system LSI is kept below the limit power consumption. FIG. 5 and FIG. 6 are flow charts showing the control of the power consumption and the bus of the power processing speed control circuit 109, respectively. The flowchart shows control procedures executed by the clock control circuit 401 and the bus control circuit 402, respectively.

First, a control procedure of power consumption will be described with reference to FIG. Step 1: Operation mode change request signal from each function unit 4 4 4 to

4 Changes in 4 7 are detected. If a change is detected, go to step 2. If not, go to step 1.

Step 2: Select the power consumption corresponding to the operation mode of each function unit from the power consumption of each function unit 51a output from the power processing speed control table 404 (see Fig. 3). I do.

Step 3: Allocate the power consumption budget from the function unit with the highest processing priority from the priority unit 451c of each function unit output from the power processing speed control table 404.

Step 4: Check whether the total power consumption exceeds the LSI's limit power consumption. If so, go to step 5. If not, go to step 6.

Step 5: Select the operation mode (clock frequency) so that the power consumption decreases in order from the functional unit with the lowest processing priority. Then, return to Step 4.

Step 6: Activate the bus control circuit 402.

Step 7: Termination from the bus control circuit 402 (detailed in FIG. 6) Wait. When finished, go to step 8.

Step 8: Operation of each function unit determined by the bus control circuit 402 Selects the clock frequency corresponding to the mode and outputs clock control signals 414 to 417. Go to step 1.

Next, a control procedure for controlling the occupation time of the bus will be described with reference to FIG.

Step 1: Clock control processing Waiting for activation from 401. If there is activation (Step 6 in Figure 5), go to Step 2.

Step 2: Each function determined by the clock control processing 401 based on the individual bus occupation time 451b of each function unit output from the power processing speed control table 404 (see Fig. 3) Select the bus occupation time corresponding to the unit operation mode.

Step 3: Allocate the budget of bus occupation time from the higher priority function unit from the priority order of function units output from the power processing speed control table.

Step 4: Check whether the total bus occupation time exceeds 100%. If it does, go to step 5. If not, go to step 6.

Step 5: Change the operation mode so that the bus occupancy time becomes shorter in order from the function unit with the lowest priority. Go to step 4.

Step 6: The operation mode determined by the bus control circuit 402 is output to the clock control circuit 401 (FIG. 5, step 7).

Step 7: Control the bus occupation time corresponding to the operation mode of each function unit. Outputs a bus enable signal (bus occupation time control signal) 4 2 4 to 4 2 7 to each function unit according to the bus occupation time for the bus request signal 4 3 4 to 4 3 7 from each function unit . Go to step 1.

As described above, the clock control circuit 401 and the bus control circuit 402 perform simple control, and therefore, the state machine, the sequencer, the PLA (program (Mable logic array). Also, control may be performed by a microcomputer.

Here, the configuration of the bus control circuit 402 is shown in FIG. The bus control circuit 402 is composed of a bus occupation time control circuit 510 and a bus arbitration control circuit 520. The bus occupancy time control circuit 510 controls the bus occupancy time in accordance with the flowchart described in FIG. The bus arbitration control circuit 520 receives the bus occupancy time 452 for each functional unit allocated by the bus occupancy time control circuit 510, and receives a bus request signal from each functional unit 4 3 4 to 4 4 According to 37, a bus enable signal (bus occupancy time control signal) is sent to each function unit so that the bus occupation time of each function unit becomes a predetermined time. Is output.

In system LSIs, the power supply voltage supplied from the outside may be lowered (or raised) to operate depending on the requirements of the constituent system. The purpose is to match the power supply voltage with the peripheral LSI, to reduce the power supply voltage to reduce power consumption, or to increase the power supply voltage to increase the operating frequency. Or In addition, when operating with dry cells and storage batteries, the power supply voltage gradually decreases over time.

When the power supply voltage changes in this way, the actual power consumption can be calculated even if the clock frequency is controlled by the power processing speed control circuit 109 so that the power consumption of the LSI falls below the limit power consumption. Differences from the results may occur. In this case, it is necessary to accurately detect the power supply voltage supplied to the system LSI, calculate the power consumption using that voltage, and perform optimal power control.

FIG. 8 shows the configuration of the voltage detection circuit 110 used in such a case. The voltage detection circuit 110 inputs a reference voltage Vref from outside and The actual measured value of the power supply voltage is obtained.

That is, the reference voltage Vref is divided by resistors R1, R2, R3, and R4, and the divided voltages are set as VI, V2, and V3, and these voltages are compared with the power supply voltage VDD. Compare with 5 0 1-5 0 3. Assuming that the output of the comparator is 0 when the divided voltage is higher than VDD and 1 when the divided voltage is lower, the point at which the voltage changes from 0 to 1 is the voltage of VDD. This signal is digitized (converted to a voltage value) by the encoder 504 and output to the internal bus 10. As a result, the numerical value is read out by the microcomputer 104.

Assuming that the power consumption p of each function unit written in the power processing speed control table 404 is calculated from the power supply voltage V, the power consumption is proportional to the square of the voltage. If the measured power supply voltage has decreased to Vm, power consumption Pm is calculated by Pm = PVm ^² / V ^2. By rewriting and storing this value of Pm in the power consumption area of each functional unit in the power processing speed control table 404, the power consumption of the LSI can be calculated more accurately.

To measure the actual measured value of the power supply voltage more accurately, the number of voltage dividers and the number of comparators should be increased.

When each functional unit operates at a different voltage, the voltage detection circuit 110 may be mounted for each voltage.

According to the present embodiment, in a system LSI mounting a plurality of functional units, power consumption according to an operation mode (operating clock frequency) and bus occupation required for real-time processing are provided for each functional unit. By controlling the clock frequency of each function unit and the occupation time of the bus using the time and the priority of the processing of each function unit, the power consumption of the system LSI can be reduced to the limit power consumption (the upper limit value of the power consumption). ) Real-time processing of a high-priority functional unit can be realized while maintaining the following. Power control of high-performance system LSI with low power consumption becomes possible.

(Example 2)

FIG. 9 shows an embodiment in which the information of the power consumption of each functional unit, the occupation time of the individual bus, and the processing priority is collectively stored in the external memory 500. In FIG. 9, reference numeral 108 denotes an external memory control circuit for reading information stored in the external memory 500, and the microcomputer 104 controls the external memory control circuit 108 at initialization. The information in the external memory 500 is read out via the external memory 500, and written into the power processing speed control table 404 in the power processing speed control circuit 109. The subsequent operation is the same as in the first embodiment.

In this embodiment, the power and the bus occupation time can be controlled for the external memory control circuit 108 in the same manner as the other function units 104 to 107.

According to this embodiment, data required for power control and bus occupation time control can be supplied from the external memory even after the LSI design is completed, so system specifications can be changed simply by rewriting data in the external memory. Etc. can be easily handled.

(Example 3)

FIG. 10 shows an embodiment in which information relating to the power consumption of the functional units, the individual bus occupation time, and the processing priority is stored on its own. In FIG. 10, reference numerals 204 to 207 denote power processing speed storage circuits which are sub-storage means provided in the function units 104 to 107, respectively, and store the above information. ing.

FIG. 11 shows information stored in the power processing speed storage circuit 204. The memory circuit 204 is a source of information stored in the power processing speed control table 404. The operation mode is a high-speed clock mode (200 MHz). There are three types: medium-speed clock mode (100 MHz) and low-speed clock mode (500 MHz). In each mode, power consumption, individual bus occupation time, and processing priority are stored. I have.

At the time of initialization, the microcomputer 104 reads out the information from the storage circuits 204 to 207 and writes the information to the power processing speed control table 404 in the power processing speed control circuit 109. The subsequent operation is the same as in the first embodiment.

In this way, by preserving information on power consumption, bus occupation time, and priority for each functional unit in this way, when developing a system LSI, even if the type and number of functional units change every design, Without changing the basic configuration of the microcomputer 104 and the power processing speed control circuit 109 for storing the power consumption, bus occupation time and priority in the power processing speed control circuit 109, It becomes possible to develop various types of system LSI. Further, in the present embodiment, the information on the power consumption and the bus occupation time has been described as being stored in the power processing speed storage circuits 204 to 207, but the basic function of the function unit, the basic specification, the version information, By writing bug information etc. in the storage circuit of each function unit, even if the function unit of the system LSI is added or deleted and redesigned, the data of the storage circuit can be read simply by reading the data of the storage circuit. Since the internal configuration is known, the control software that controls this can be created (corrected) correctly.

As described in detail above, according to the present invention, it is possible to realize a system LSI that can execute real-time processing with a certain power consumption or less. Thus, a low-cost semiconductor device capable of mounting a large number of functional units without using a package having a high heat radiation effect or forced cooling can be provided.

In addition, power consumption for each function unit operation mode in the system LSI, By storing the bus occupation time and priorities in advance, the control software for reading this information and the configuration of the power processing speed control circuit can be made the same at initialization. Power control sequence can be standardized.

Also, even if the system LSI is used under any operating conditions, the power consumption does not exceed the upper limit (constant value), so that the reliability of the semiconductor device to which the present invention is applied and the system using the device are improved. can do. Industrial applicability

The semiconductor device according to the present invention is capable of performing various functions and has a low cost, so that it is widely applied to fields such as multimedia, communication, and consumer equipment.

Claims

The scope of the claims

1. In a semiconductor device having a plurality of function units interconnected by an internal bus, a request for changing from an operation mode of an operating speed to another operation mode is output according to data processing contents. The sum of the power consumption of the operation mode output means provided for each of the plurality of function units and the function unit executing the processing in the plurality of function units exceeds the limit power consumption given to the semiconductor device. Power processing speed control means for controlling the frequency of the clock signal and the bus occupation time used by the function unit for executing the processing in accordance with the operation mode change request. Semiconductor device.

2. The power processing speed control means includes means for storing information on power consumption, individual bus occupation time, and data processing priority for each operation mode of the plurality of functional units; The power consumption and the individual bus occupation time are allocated to the function blocks to be executed in the order of the function blocks having the highest data processing priority using the above information, and the memory blocks are allocated according to the allocated power consumption. The frequency of the signal is set, and the assigned individual bus occupancy time is set as the bus occupancy time, and the clock control signal for operating at the set clock signal frequency and the bus occupancy for using the set bus occupancy time And a means for supplying a time control signal to a function unit for executing the processing. Location.

3. The means for storing the information includes a power processing speed control table for storing the information, and the means for supplying the clock control signal and the bus occupation time control signal to the functional unit for executing the processing includes the clock Control system that generates and outputs control signals and bus occupancy time control signals 3. The semiconductor device according to claim 2, comprising a control circuit and a bus control circuit.

4. Each of the plurality of functional units further includes: a clock switching unit that receives the clock control signal and selects a clock signal of a corresponding frequency from the plurality of clock signals; Claims 1 to 5 characterized by having data processing means which operates and sets a transfer rate of data transmitted to a bus in accordance with the bus occupation time control signal. 4. The semiconductor device according to claim 3.

5. The power processing speed control means includes means for detecting a change in the operation mode in the operation mode change request, and detects a change in the operation mode of any of the function units that execute the processing. An operation for controlling a frequency of an acknowledgment signal and a bus occupation time is started.

4. The semiconductor device according to any one of items 1 to 3.

6. The power processing speed control means includes means for calculating the total power consumption of the functional unit that executes the processing, so that the calculated total power consumption does not exceed the limit power consumption given to the semiconductor device. 4. The semiconductor device according to claim 1, wherein control is performed such that a clock frequency of a functional unit having a lower priority in data processing is reduced.

7. It further includes voltage detection means for detecting the voltage of a power supply used internally, and the power processing speed control means detects the total power consumption of the function unit executing the processing by the voltage detection means. The semiconductor according to any one of claims 1 to 3, wherein the calculation is performed using the voltage obtained.

8. An external storage device for storing information on power consumption, individual bus occupation time, and data processing priority for each operation mode of the plurality of functional units, and the external storage device inside To control the operation of the device An external storage device control unit, wherein the power processing speed control unit stores information on the external storage device read by the external storage device control unit; and a data for a function block executing the processing. The power consumption and the individual bus occupation time are allocated using the information stored in the storage means in the order of the function blocks having the highest processing priority, and the frequency of the clock signal is set in accordance with the allocated power consumption. The allocated individual bus occupancy time is set as the bus occupancy time, and the above process is performed by using the clock control signal for operating at the frequency of the set clock signal and the bus occupancy time control signal for using the set bus occupancy time. 2. A semiconductor device according to claim 1, further comprising means for supplying a function unit to be executed. Place.

9. Each of the plurality of functional units has sub-storage means for storing information on power consumption, individual bus occupation time, and data processing priority for each operation mode, and the power processing speed control means. Storage means for reading and storing information stored in the sub-storage means; power consumption and individual buses in order of function blocks having higher data processing priorities with respect to the function blocks executing the processing. The occupation time is assigned using the information stored in the storage means, the frequency of the click signal is set in accordance with the assigned power consumption, and the assigned individual bus occupation time is set as the bus occupation time. A clock control signal for operating at the set clock signal frequency and a bus occupancy time control signal for using the set bus occupancy time are used. The semiconductor device according to claim 1, characterized in that it e Bei and means for supplying the functional Yuni' you want to execute the serial processing.

10. In a semiconductor device having a plurality of function units interconnected by an internal bus, a total sum of power consumption of the function units executing processing in the plurality of function units is given to the semiconductor device. Marginal power consumption Control and set the clock signal frequency and bus occupancy time used by the function unit that performs the relevant processing so that the frequency does not exceed, and set the frequency and bus occupancy of the set clock signal to the function unit that performs the processing. A power processing speed control circuit for outputting a clock control signal for operating with time and a bus occupancy time control signal, wherein each of the plurality of functional units receives the clock control signal and receives a plurality of clocks. A clock switching circuit for selecting a clock signal having a corresponding frequency from the signals; and a bus operation time control signal which operates according to the selected clock signal and transfers a transfer rate of data to be transmitted to a bus. A data processing circuit to be set according to the data processing request, and an operation mode change request from the operation mode of the operating speed to another operation mode according to the data processing content. The power processing speed control circuit generates and outputs the quick control signal and the bus occupancy time control signal in response to the operation mode change request. A semiconductor device characterized by the following.

11. The power processing speed control circuit includes: a power processing speed control table that stores information on power consumption, an individual bus occupation time, and data processing priority for each operation mode of the plurality of function units. The power consumption is allocated to the function blocks that execute the processing in the order of the function blocks having the highest data processing priority using the information, and corresponds to the power consumption to which the frequency of the mouth signal is allocated. A clock control circuit that outputs the clock control signal by setting the function block; and a function block that performs the processing. The bus occupancy time control signal is output by setting the assigned individual bus occupancy time as the bus occupancy time. The semiconductor device according to a first 0 wherein claims, characterized in that a bus control circuit.

12. The power processing speed control circuit starts the operation of outputting the clock control signal and the bus occupation time control signal when any of the function units executing the processing outputs an operation mode change request. The semiconductor device according to claim 10 or 11, wherein:

13. The power processing speed control circuit has a circuit for calculating the total power consumption of the function unit for executing the processing, and the calculated total power consumption does not exceed the limit power consumption given to the semiconductor device. 12. The semiconductor device according to claim 10, wherein control is performed so as to lower the clock frequency of the function unit having a lower priority in data processing.

14. A voltage detection circuit for detecting a voltage of a power supply used internally, wherein the power processing speed control circuit detects a total power consumption of the function unit executing the processing by the voltage detection circuit. 12. The semiconductor device according to claim 10, wherein the calculation is performed using a voltage.