WO2000070678A1 - Chip package with molded underfill - Google Patents

Chip package with molded underfill Download PDF

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Publication number
WO2000070678A1
WO2000070678A1 PCT/US1999/010771 US9910771W WO0070678A1 WO 2000070678 A1 WO2000070678 A1 WO 2000070678A1 US 9910771 W US9910771 W US 9910771W WO 0070678 A1 WO0070678 A1 WO 0070678A1
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
substrate
circuit chip
underfilling
mold
Prior art date
Application number
PCT/US1999/010771
Other languages
French (fr)
Inventor
Patrick O. Weber
Original Assignee
Hestia Technologies, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US08/959,927 priority Critical patent/US6038136A/en
Application filed by Hestia Technologies, Inc. filed Critical Hestia Technologies, Inc.
Priority to PCT/US1999/010771 priority patent/WO2000070678A1/en
Priority to KR1020017014402A priority patent/KR20020035477A/en
Priority to JP2000619029A priority patent/JP2003500833A/en
Priority to EP99923109A priority patent/EP1190448A4/en
Publication of WO2000070678A1 publication Critical patent/WO2000070678A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Definitions

  • the invention relates to an integrated circuit chip mounting system and more particularly, to an integrated circuit chip package and a method of electrically connecting and mounting integrated circuit chips to a substrate.
  • Flip chip technology is well known in the art for electrically connecting an integrated circuit chip to an integrated circuit substrate or package. Formation of one type of flip chip involves forming solder bumps on electrical interconnection pads on the active or front side of a semiconductor chip. The chip with solder bumps is then inverted onto a laminate substrate with the solder bumps aligned with metal circuits provided on the substrate. The solder bumps on the chip are then soldered to the metal pads on the substrate by melting the solder in a reflow furnace. A solder joint is formed by the reflowing of the solder between the semiconductor chip and the substrate. After the chip has been attached to the substrate by the reflow soldering process, narrow gaps are present between the solder bumps.
  • the substrate is typically comprised of a ceramic material or a polymer composite laminate, while the chip is formed of silicon. Due to these different materials, there is a mismatch in the coefficient of thermal expansion between the semiconductor chip and the substrate on which the chip is mounted. During temperature cycling the semiconductor chip and substrate expand and contract at differing rates. Accordingly, the soldered joints between the semiconductor chip and the substrate will have a tendency to fail because of the coefficient of thermal expansion mismatch. In addition, because of the very small size of the solder joints, the joints are subject to failures.
  • the strength of the solder joints between the integrated circuit chip and the substrate are typically enhanced by underfilling the space between the semiconductor chip and the substrate and around the solder joints.
  • the underfill material is typically a polymer adhesive which reduces stress on the solder joints.
  • the conventional method of underfilling includes dispensing the underfill material in a fillet or bead extending along two or more edges of the chip and allowing the underfill material to flow by capillary action under the chip to fill all the gaps between the semiconductor chip and the substrate.
  • the solder bumps create a very narrow gap between the semiconductor chip and the substrate which is about 0.002 - 0.005 inches (0.051 - 0.127mm).
  • the underfill material which is capable of flowing through these narrow gaps contains only a small amount of filler material because the filler material will prevent the underfill material from flowing easily into the gaps.
  • This type of underfill material with a low amount of filler material has an extremely high mismatch of coefficient of thermal expansion with the semiconductor chip, the solder bumps, and the substrate. Accordingly, it would be desirable to use an underfill material having more filler and thus, less of a thermal expansion coefficient mismatch with the substrate and chip.
  • FIGS. 3 and 3a An example of an integrated circuit chip 100 which has been attached to a substrate 102 by solder balls 104 and underfilled by a conventional method is illustrated if FIGS. 3 and 3a.
  • the underfill material 106 has been drawn into the spaces between the solder balls 104 by capillary action to fill the air spaces between the integrated circuit chip 100 and the substrate 102.
  • An integrated circuit chip package includes an integrated circuit chip having an active surface with interconnection pads disposed thereon, and a substrate having a first surface with bonding pads substantially corresponding to the interconnection pads of the integrated circuit chip and a second side having a plurality of solder pads electrically interconnected with the bonding pads.
  • a vent hole extends from the first side to the second side of the substrate, and is positioned beneath the integrated circuit chip when the chip is mounted on the substrate.
  • a plurality of solder bumps electrically connect the interconnection pads of the integrated circuit chip with the bonding pads on the first side of the substrate.
  • a molded underfill material is molded around the integrated circuit chip. The molded underfill material surrounds the solder bumps between the integrated circuit chip and the substrate and extends into the vent hole in the substrate.
  • a further aspect of the present invention relates to a method of underfilling an integrated circuit chip which has been electrically interconnected to a substrate.
  • the method includes the steps of placing the integrated circuit chip and substrate within a mold cavity, injecting a mold compound into the mold cavity, underfilling a space between the integrated circuit chip and the substrate with the mold compound by the pressure of injection of the mold compound into the mold cavity, and allowing air to escape from between the integrated circuit chip and the substrate during underfilling through a vent in the substrate.
  • the present invention addresses the deficiencies of known underfilling methods by underfilling faster and more reliably than the known methods.
  • the present invention forms an encapsulated integrated circuit chip package and performs underfilling in the same step.
  • FIG. 1 is a top view of an integrated circuit chip with solder balls positioned on an active surface of the chip;
  • FIG. 2 is a side view of the integrated circuit chip of FIG. 1;
  • FIG. 3 is a side view of an integrated circuit chip mounted on a substrate and underfilled according to a prior art method
  • FIG. 3a is an enlarged side view of a portion of the chip and substrate of FIG. 3;
  • FIG. 4 is a cross-sectional side view of an integrated circuit chip mounted on a substrate which has been underfilled and encapsulated according to the present invention
  • FIG. 4a is an enlarged cross-sectional side view of a portion of the integrated circuit chip of FIG. 4;
  • FIG. 5 is a cross-sectional side view of an alternative embodiment of an integrated circuit chip package according to the present invention
  • FIG. 6 is a cross-sectional side view of an integrated circuit chip and substrate placed within a mold cavity according to the present invention
  • FIG. 7 is a cross-sectional side view of the mold of FIG. 6 during underfilling; and FIG. 8 is a cross-sectional side view of the mold of FIG. 6 when underfilling has been completed.
  • the integrated circuit chip package 10 is illustrated by way of example in FIG. 4 and includes an integrated circuit chip 12, a substrate 14, and a mold compound 16 encapsulating the chip and underfilling between the chip and the substrate.
  • the integrated circuit chip package 10 is formed by transfer molding the package in a mold tool by a process which is described below with reference to FIGS. 6 - 8.
  • the integrated circuit chip package 10 according to the present invention can be made much faster than a similar package made using conventional underfilling techniques.
  • the mold compound 16 used for underfilling also encapsulates the integrated circuit chip 12 in a single molding step.
  • the integrated circuit chip 12 has an active upper surface 18 having metal circuits thereon.
  • a plurality of solder bumps 20 are formed on the active surface 18 of the integrated circuit chip 12 for electrical interconnection of the chip to the substrate 14.
  • the patterns of the solder bumps 20 on the integrated circuit chip 12 will vary widely between chips and may have spaces between the solder bumps which are as small as approximately 0.002 inches (0.051 mm).
  • the solder bumps 20 themselves have a height which is approximately 0.005 inches (0.127 mm).
  • the substrate 14, as shown in FIG. 4, includes an upper surface 22 having bonding pads (not shown) which are located to substantially correspond to the locations of the interconnection pads and solder bumps 20 on the active surface 18 of the integrated circuit chip 12.
  • a lower surface 28 of the substrate 14 also has a plurality of solder pads (not shown) which are electrically interconnected with the bonding pads on the top side of the substrate.
  • the solder pads on the underside of the substrate are each provided with substrate solder bumps 24 which allow electrical interconnection between the integrated chip package 10 and a circuit board.
  • the solder bumps 24 may be replaced by pins or the solder pads may be used alone without the solder bumps.
  • the substrate 14 includes a vent hole 26 extending between the upper surface 22 and the lower surface 28 of the substrate and positioned at or near a center of the integrated circuit chip 12.
  • the solder bumps 20 are melted by a reflow furnace to connect the integrated circuit chip to the substrate.
  • the reflowed chip and substrate are separated by a distance D which is 0.002 inches (0.051 mm) to 0.006 inches (0.152 mm), preferably approximately 0.003 inches (0.076 mm) to 0.005 inches (0.127 mm).
  • the underfilling material or mold material 16 is provided between the integrated circuit chip 12 and the substrate 14 and surrounding each of the solder bumps 20.
  • the underfill material 16 is a thermoset mold compound which is forced into air gaps between the chip and the substrate by the pressure of the mold compound being forced into the mold tool. The forcing of the mold compound 16 under the chip 12 to provide underfilling provides substantial time savings over the conventional method of allowing the underfill material to be drawn under the chip by capillary action.
  • the vent hole 26 extending through the substrate 14 allows air to escape from between the integrated circuit chip 12 and the substrate 16 as the mold compound is forced underneath the chip and prevents air pockets from becoming trapped by the mold compound.
  • the vent hole 26 is preferably positioned near a center point of a chip receiving area on the substrate upper surface 22. However, the locations of the solder bumps 20 may require that the vent hole 26 be located somewhat displaced from the center of the chip receiving area on the substrate. Alternatively, multiple vent holes may be used.
  • the vent hole 26 in the substrate 14 has a cross-sectional area which may vary depending on its location and the chip size and is preferably between 0.006 inches (0.152 mm) and 0.020 inches (0.50 mm).
  • the method of underfilling according to the present invention employs a mold 30 having a top half 32 and bottom half 34.
  • the bottom half 34 of the mold is provided with cavities 36 for receiving the substrate solder bumps 24 on the lower side of the substrate.
  • the mold cavities 36 may be eliminated and the substrate solder bumps 24 or pins may be attached after underfilling.
  • the bottom half 34 of the mold also includes a mold material overflow channel 38 which is positioned to receive mold material which passes through the central vent hole 26 in the substrate. Mold material which collects in the overflow channel 38 forms an overflow bead 48 of mold material on an underside of the substrate 14 as shown in FIGS. 4, 7, and 8.
  • the top half 32 of the mold defines an upper half of a mold cavity 40 and an upper half of an overflow cavity 42.
  • a mold compound inlet 44 is provided through which the mold material is introduced into the mold cavity 40.
  • a vent 46 connects the mold cavity 40 to the overflow cavity 42.
  • the molding process of the present invention is a transfer molding process with an operating temperature between approximately 150° C and 180° C and material pressures of approximately 300 - 1000 psi (0.144 - 0.479 bars).
  • the transfer molding composition used in the present invention once cured, does not become flowable upon reheating.
  • the mold compound fills the mold cavity surrounding the integrated circuit chip 12 and the sides of the substrate 14.
  • the mold compound is also forced between the chip 12 and the substrate 14 into the air gaps which are present between the solder joints formed by the solder bumps 20.
  • a pressure within the mold cavity 40 must be carefully controlled while the underfilling process is performed to prevent the pressure within the mold cavity from exceeding a predetermined pressure threshold and pressing the chip 12 down onto the substrate with a force causing crushing of the solder bumps 20 before the underfilling process is complete.
  • the mold cavity pressure is controlled by the mold vent 46 which allows some of the mold compound to escape from the mold cavity 40 into the overflow cavity 42.
  • the size and shape of the mold vent 46 is particularly designed so that a predetermined threshold pressure within the mold cavity at which the solder bumps 20 would be crushed is not reached.
  • the overflow cavity 42 accommodates a sufficient amount of mold compound to provide pressure control during the underfilling process. Once underfilling has been completed, and the solder bumps 20 are completely surrounded by the mold compound, there is no longer a risk of excessive pressure in the mold cavity 40 causing the solder bumps to be crushed.
  • the mold compound moves radially inwardly from each of the edges of the integrated circuit chip 12 until it reaches the vent hole 26 in the substrate. The mold compound then passes through the vent hole 26 into the overflow channel 38 in the bottom half of the mold 34 forming the overflow bead 48.
  • the volume of mold compound which can be held in both the vent hole 26 and the overflow channel 38 are designed to allow mold material to continue to pass into the vent hole of the substrate 14 until all the air spaces between the integrated circuit chip 12 and substrate have been completely filled.
  • the total transfer time for the mold cavity 40 to be filled and for underfilling to be completed is preferably between approximately 15 and 20 seconds.
  • the cure time for the thermoset mold material to cure is then between about 60 and 200 seconds. After this cure time, the mold is opened and the integrated circuit chip package 10 is removed from the mold.
  • the total cycle time for underfilling and encapsulation of the integrated circuit chip 12 in the present invention is significantly better than the time for underfilling alone with the known underfilling methods employing capillary action.
  • An apparatus for delivery of the mold compound to the mold inlet 44 may be any of the known delivery systems including those employing a plunger to press a mold compound in pellet form into the mold tool.
  • a multiple plunger system may be used to control the pressure of the mold compound being pressed into each mold cavity when a plurality of cavities are being filled.
  • the multiple plunger system may be used either with or without the use of an overflow cavity 42 for additional pressure regulation.
  • an integrated circuit chip package 50 as shown in FIG. 5 is formed in which the integrated circuit chip 52 is mounted on a substrate 54 and is not fully encapsulated by a mold compound 56.
  • the integrated chip package 50 is formed in a mold cavity having an upper mold half which engages a surface 58 of the integrated circuit chip 52.
  • the mold compound 56 surrounds the edges of the integrated circuit chip 52 and the edge of the substrate 54, but does not enclose the chip within the mold compound 56.
  • the integrated circuit chip package 50 shown in FIG. 5 is formed in the same manner as that of FIG. 4 by reflow soldering the integrated circuit chip to the substrate 54 by a plurality of solder pumps.
  • the integrated circuit chip 52 and substrate 54 are then placed into a mold cavity and a transfer molding compound 56 is injected into the mold cavity around the integrated circuit chip 52 and substrate 54 and forced into the space between the chip and the substrate to underfill all gaps between the solder bumps.
  • the modified integrated circuit chip package 50 of FIG. 5 does not require that precautions be taken to prevent crushing solder bumps due to the fact that pressure is not applied by the mold compound to the exposed backside surface 58 of the chip 52.
  • the transfer molding process according to the present invention may be used for a wide variety of integrated circuit chip shapes, sizes, and types.
  • the transfer molding composition may be modified as known to those in the art to achieve different transfer times, cure times, flow characteristics, and post cure properties.
  • the mold compound 16 for use in the present invention includes a combination of one or more adhesive and one or more filler material.
  • the filler material is between about 70 and 90 percent of the mold compound, preferably between 75 and 85 percent.
  • the filler material may be silica, quartz, or any other known filler material having particle diameters which are preferably 0.35 - 2 mils (0.01 - 0.05 mm).
  • the filler material particles may be formed in different shapes such as spherical, elongated, or irregularly shaped to achieve different flow characteristics.
  • the adhesive material may be any known adhesive material, such as a novolac epoxy.

Abstract

An integrated circuit chip package (10) according to the present invention includes an integrated circuit chip (12) mounted on a substrate (14) by a plurality of solder bumps (20). A mold compound (16) is used for underfilling air gaps between the chip (12) and the substrate (14). The integrated circuit chip package (10) is formed by placing the chip (12) and substrate (14) within a mold cavity (36) and pressing a transfer mold compound (16) into the mold cavity (36). Air spaces between the integrated circuit chip (12) and the substrate (14) are underfilled by the mold compound as it is pressed in between the integrated circuit chip (12) and the substrate (14). Air is allowed to escape from between the chip (12) and the substrate (14) during the underfilling through a vent (26) which extends through the substrate (14). The underfilling material (16) may also be used to encapsulate the chip (12) at the same time that underfilling is performed.

Description

CHIP PACKAGE WITH MOLDED UNDERFILL
Field of the Invention
The invention relates to an integrated circuit chip mounting system and more particularly, to an integrated circuit chip package and a method of electrically connecting and mounting integrated circuit chips to a substrate.
Background of the Invention
Flip chip technology is well known in the art for electrically connecting an integrated circuit chip to an integrated circuit substrate or package. Formation of one type of flip chip involves forming solder bumps on electrical interconnection pads on the active or front side of a semiconductor chip. The chip with solder bumps is then inverted onto a laminate substrate with the solder bumps aligned with metal circuits provided on the substrate. The solder bumps on the chip are then soldered to the metal pads on the substrate by melting the solder in a reflow furnace. A solder joint is formed by the reflowing of the solder between the semiconductor chip and the substrate. After the chip has been attached to the substrate by the reflow soldering process, narrow gaps are present between the solder bumps.
The substrate is typically comprised of a ceramic material or a polymer composite laminate, while the chip is formed of silicon. Due to these different materials, there is a mismatch in the coefficient of thermal expansion between the semiconductor chip and the substrate on which the chip is mounted. During temperature cycling the semiconductor chip and substrate expand and contract at differing rates. Accordingly, the soldered joints between the semiconductor chip and the substrate will have a tendency to fail because of the coefficient of thermal expansion mismatch. In addition, because of the very small size of the solder joints, the joints are subject to failures.
The strength of the solder joints between the integrated circuit chip and the substrate are typically enhanced by underfilling the space between the semiconductor chip and the substrate and around the solder joints. The underfill material is typically a polymer adhesive which reduces stress on the solder joints. The conventional method of underfilling includes dispensing the underfill material in a fillet or bead extending along two or more edges of the chip and allowing the underfill material to flow by capillary action under the chip to fill all the gaps between the semiconductor chip and the substrate. The solder bumps create a very narrow gap between the semiconductor chip and the substrate which is about 0.002 - 0.005 inches (0.051 - 0.127mm). Therefore, the underfill material which is capable of flowing through these narrow gaps contains only a small amount of filler material because the filler material will prevent the underfill material from flowing easily into the gaps. This type of underfill material with a low amount of filler material has an extremely high mismatch of coefficient of thermal expansion with the semiconductor chip, the solder bumps, and the substrate. Accordingly, it would be desirable to use an underfill material having more filler and thus, less of a thermal expansion coefficient mismatch with the substrate and chip.
An example of an integrated circuit chip 100 which has been attached to a substrate 102 by solder balls 104 and underfilled by a conventional method is illustrated if FIGS. 3 and 3a. The underfill material 106 has been drawn into the spaces between the solder balls 104 by capillary action to fill the air spaces between the integrated circuit chip 100 and the substrate 102.
The use of capillary action to suck the underfill material into the gap between the integrated circuit chip and the substrate takes between 5 and 20 minutes, depending on many factors including the size of the chip and the underfill material used. Another drawback of the conventional underfilling method is the occurrence of voids in the underfilling material.
Accordingly, a need exists for an underfilling method for completely filling the spaces between an integrated circuit chip and a substrate which can reliably underfill at a faster rate than known methods.
Summary of the Invention
An integrated circuit chip package according to one aspect of the present invention includes an integrated circuit chip having an active surface with interconnection pads disposed thereon, and a substrate having a first surface with bonding pads substantially corresponding to the interconnection pads of the integrated circuit chip and a second side having a plurality of solder pads electrically interconnected with the bonding pads. A vent hole extends from the first side to the second side of the substrate, and is positioned beneath the integrated circuit chip when the chip is mounted on the substrate. A plurality of solder bumps electrically connect the interconnection pads of the integrated circuit chip with the bonding pads on the first side of the substrate. A molded underfill material is molded around the integrated circuit chip. The molded underfill material surrounds the solder bumps between the integrated circuit chip and the substrate and extends into the vent hole in the substrate.
A further aspect of the present invention relates to a method of underfilling an integrated circuit chip which has been electrically interconnected to a substrate. The method includes the steps of placing the integrated circuit chip and substrate within a mold cavity, injecting a mold compound into the mold cavity, underfilling a space between the integrated circuit chip and the substrate with the mold compound by the pressure of injection of the mold compound into the mold cavity, and allowing air to escape from between the integrated circuit chip and the substrate during underfilling through a vent in the substrate. The present invention addresses the deficiencies of known underfilling methods by underfilling faster and more reliably than the known methods. In addition, the present invention forms an encapsulated integrated circuit chip package and performs underfilling in the same step.
Brief Description of the Drawing Figures
The invention will be described in greater detail with reference to the accompanying drawings in which like elements bear like reference numerals, and wherein:
FIG. 1 is a top view of an integrated circuit chip with solder balls positioned on an active surface of the chip;
FIG. 2 is a side view of the integrated circuit chip of FIG. 1;
FIG. 3 is a side view of an integrated circuit chip mounted on a substrate and underfilled according to a prior art method;
FIG. 3a is an enlarged side view of a portion of the chip and substrate of FIG. 3;
FIG. 4 is a cross-sectional side view of an integrated circuit chip mounted on a substrate which has been underfilled and encapsulated according to the present invention;
FIG. 4a is an enlarged cross-sectional side view of a portion of the integrated circuit chip of FIG. 4;
FIG. 5 is a cross-sectional side view of an alternative embodiment of an integrated circuit chip package according to the present invention; FIG. 6 is a cross-sectional side view of an integrated circuit chip and substrate placed within a mold cavity according to the present invention;
FIG. 7 is a cross-sectional side view of the mold of FIG. 6 during underfilling; and FIG. 8 is a cross-sectional side view of the mold of FIG. 6 when underfilling has been completed.
Detailed Description of the Preferred Embodiments
The integrated circuit chip package 10 according to the present invention is illustrated by way of example in FIG. 4 and includes an integrated circuit chip 12, a substrate 14, and a mold compound 16 encapsulating the chip and underfilling between the chip and the substrate. The integrated circuit chip package 10 is formed by transfer molding the package in a mold tool by a process which is described below with reference to FIGS. 6 - 8.
The integrated circuit chip package 10 according to the present invention can be made much faster than a similar package made using conventional underfilling techniques. In addition, the mold compound 16 used for underfilling also encapsulates the integrated circuit chip 12 in a single molding step.
With reference to FIGS. 1 and 2, the integrated circuit chip 12 has an active upper surface 18 having metal circuits thereon. A plurality of solder bumps 20 are formed on the active surface 18 of the integrated circuit chip 12 for electrical interconnection of the chip to the substrate 14. The patterns of the solder bumps 20 on the integrated circuit chip 12 will vary widely between chips and may have spaces between the solder bumps which are as small as approximately 0.002 inches (0.051 mm). The solder bumps 20 themselves have a height which is approximately 0.005 inches (0.127 mm).
The substrate 14, as shown in FIG. 4, includes an upper surface 22 having bonding pads (not shown) which are located to substantially correspond to the locations of the interconnection pads and solder bumps 20 on the active surface 18 of the integrated circuit chip 12. A lower surface 28 of the substrate 14 also has a plurality of solder pads (not shown) which are electrically interconnected with the bonding pads on the top side of the substrate. The solder pads on the underside of the substrate are each provided with substrate solder bumps 24 which allow electrical interconnection between the integrated chip package 10 and a circuit board. The solder bumps 24 may be replaced by pins or the solder pads may be used alone without the solder bumps. According to the present invention the substrate 14 includes a vent hole 26 extending between the upper surface 22 and the lower surface 28 of the substrate and positioned at or near a center of the integrated circuit chip 12.
When the integrated circuit chip 12 is positioned on the substrate 14 the solder bumps 20 are melted by a reflow furnace to connect the integrated circuit chip to the substrate. The reflowed chip and substrate are separated by a distance D which is 0.002 inches (0.051 mm) to 0.006 inches (0.152 mm), preferably approximately 0.003 inches (0.076 mm) to 0.005 inches (0.127 mm).
According to the present invention, the underfilling material or mold material 16 is provided between the integrated circuit chip 12 and the substrate 14 and surrounding each of the solder bumps 20. The underfill material 16 is a thermoset mold compound which is forced into air gaps between the chip and the substrate by the pressure of the mold compound being forced into the mold tool. The forcing of the mold compound 16 under the chip 12 to provide underfilling provides substantial time savings over the conventional method of allowing the underfill material to be drawn under the chip by capillary action.
The vent hole 26 extending through the substrate 14 allows air to escape from between the integrated circuit chip 12 and the substrate 16 as the mold compound is forced underneath the chip and prevents air pockets from becoming trapped by the mold compound. The vent hole 26 is preferably positioned near a center point of a chip receiving area on the substrate upper surface 22. However, the locations of the solder bumps 20 may require that the vent hole 26 be located somewhat displaced from the center of the chip receiving area on the substrate. Alternatively, multiple vent holes may be used. The vent hole 26 in the substrate 14 has a cross-sectional area which may vary depending on its location and the chip size and is preferably between 0.006 inches (0.152 mm) and 0.020 inches (0.50 mm).
With reference to FIGS. 6 - 8, the method of underfilling according to the present invention employs a mold 30 having a top half 32 and bottom half 34. The bottom half 34 of the mold is provided with cavities 36 for receiving the substrate solder bumps 24 on the lower side of the substrate. Alternatively, the mold cavities 36 may be eliminated and the substrate solder bumps 24 or pins may be attached after underfilling.
The bottom half 34 of the mold also includes a mold material overflow channel 38 which is positioned to receive mold material which passes through the central vent hole 26 in the substrate. Mold material which collects in the overflow channel 38 forms an overflow bead 48 of mold material on an underside of the substrate 14 as shown in FIGS. 4, 7, and 8.
The top half 32 of the mold defines an upper half of a mold cavity 40 and an upper half of an overflow cavity 42. Between the top and bottom halves of the mold 30, a mold compound inlet 44 is provided through which the mold material is introduced into the mold cavity 40. In addition, a vent 46 connects the mold cavity 40 to the overflow cavity 42.
The molding process of the present invention is a transfer molding process with an operating temperature between approximately 150° C and 180° C and material pressures of approximately 300 - 1000 psi (0.144 - 0.479 bars). The transfer molding composition used in the present invention, once cured, does not become flowable upon reheating.
When the mold material is injected into the mold cavity 40 through the inlet 44 as shown in FIG. 7, the mold compound fills the mold cavity surrounding the integrated circuit chip 12 and the sides of the substrate 14. The mold compound is also forced between the chip 12 and the substrate 14 into the air gaps which are present between the solder joints formed by the solder bumps 20. A pressure within the mold cavity 40 must be carefully controlled while the underfilling process is performed to prevent the pressure within the mold cavity from exceeding a predetermined pressure threshold and pressing the chip 12 down onto the substrate with a force causing crushing of the solder bumps 20 before the underfilling process is complete. The mold cavity pressure is controlled by the mold vent 46 which allows some of the mold compound to escape from the mold cavity 40 into the overflow cavity 42. The size and shape of the mold vent 46 is particularly designed so that a predetermined threshold pressure within the mold cavity at which the solder bumps 20 would be crushed is not reached. The overflow cavity 42 accommodates a sufficient amount of mold compound to provide pressure control during the underfilling process. Once underfilling has been completed, and the solder bumps 20 are completely surrounded by the mold compound, there is no longer a risk of excessive pressure in the mold cavity 40 causing the solder bumps to be crushed. During the underfilling process, the mold compound moves radially inwardly from each of the edges of the integrated circuit chip 12 until it reaches the vent hole 26 in the substrate. The mold compound then passes through the vent hole 26 into the overflow channel 38 in the bottom half of the mold 34 forming the overflow bead 48. The volume of mold compound which can be held in both the vent hole 26 and the overflow channel 38 are designed to allow mold material to continue to pass into the vent hole of the substrate 14 until all the air spaces between the integrated circuit chip 12 and substrate have been completely filled. The total transfer time for the mold cavity 40 to be filled and for underfilling to be completed is preferably between approximately 15 and 20 seconds. The cure time for the thermoset mold material to cure is then between about 60 and 200 seconds. After this cure time, the mold is opened and the integrated circuit chip package 10 is removed from the mold. The total cycle time for underfilling and encapsulation of the integrated circuit chip 12 in the present invention is significantly better than the time for underfilling alone with the known underfilling methods employing capillary action.
An apparatus for delivery of the mold compound to the mold inlet 44 may be any of the known delivery systems including those employing a plunger to press a mold compound in pellet form into the mold tool. Alternatively, a multiple plunger system may be used to control the pressure of the mold compound being pressed into each mold cavity when a plurality of cavities are being filled. The multiple plunger system may be used either with or without the use of an overflow cavity 42 for additional pressure regulation. According to another variation of the present invention, an integrated circuit chip package 50 as shown in FIG. 5 is formed in which the integrated circuit chip 52 is mounted on a substrate 54 and is not fully encapsulated by a mold compound 56. According to this aspect of the invention the integrated chip package 50 is formed in a mold cavity having an upper mold half which engages a surface 58 of the integrated circuit chip 52. In this manner, the mold compound 56 surrounds the edges of the integrated circuit chip 52 and the edge of the substrate 54, but does not enclose the chip within the mold compound 56.
The integrated circuit chip package 50 shown in FIG. 5 is formed in the same manner as that of FIG. 4 by reflow soldering the integrated circuit chip to the substrate 54 by a plurality of solder pumps. The integrated circuit chip 52 and substrate 54 are then placed into a mold cavity and a transfer molding compound 56 is injected into the mold cavity around the integrated circuit chip 52 and substrate 54 and forced into the space between the chip and the substrate to underfill all gaps between the solder bumps. The modified integrated circuit chip package 50 of FIG. 5 does not require that precautions be taken to prevent crushing solder bumps due to the fact that pressure is not applied by the mold compound to the exposed backside surface 58 of the chip 52.
The transfer molding process according to the present invention may be used for a wide variety of integrated circuit chip shapes, sizes, and types. The transfer molding composition may be modified as known to those in the art to achieve different transfer times, cure times, flow characteristics, and post cure properties.
The mold compound 16 for use in the present invention includes a combination of one or more adhesive and one or more filler material. The filler material is between about 70 and 90 percent of the mold compound, preferably between 75 and 85 percent. The filler material may be silica, quartz, or any other known filler material having particle diameters which are preferably 0.35 - 2 mils (0.01 - 0.05 mm). The filler material particles may be formed in different shapes such as spherical, elongated, or irregularly shaped to achieve different flow characteristics. The adhesive material may be any known adhesive material, such as a novolac epoxy.
While the invention has been described in detail with reference to the preferred embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made, and equivalence employed without departing from the spirit and scope of the inventions.

Claims

Claims:
1. An integrated circuit chip package comprising: an integrated circuit chip having an active surface with interconnection pads disposed thereon; a substrate having a first side with bonding pads substantially corresponding to the interconnection pads of the integrated circuit chip, a second side having a plurality of solder pads electrically interconnected with the bonding pads, and a vent hole extending from the first side to the second side of the substrate and positioned beneath the integrated circuit chip when the chip is mounted on the substrate; a plurality of solder bumps electrically connecting the interconnection pads of the integrated circuit chip with the bonding pads on the first side of the substrate; and a molded underfill material molded around the integrated circuit chip, the molded underfill material surrounding the solder bumps between the integrated circuit chip and the substrate, and the molded underfill material extending into the vent hole in the substrate.
2. The integrated circuit chip package according to claim 1, wherein the molded underfill material covers a backside of the integrated circuit chip encapsulating the chip.
3. The integrated circuit chip package according to claim 1, wherein the molded underfill material overflows the vent hole and extends along a portion the second side of the substrate.
4. The integrated circuit chip package according to claim 1, wherein the substrate includes edge surfaces and the molded underfill material covers the edge surfaces of the substrate.
5. The integrated circuit chip package according to claim 1, wherein the molded underfill material is epoxy.
6. The integrated circuit chip package according to claim 1, wherein the vent hole is positioned in the substrate at substantially a center of an area occupied by the integrated circuit chip.
7. The integrated circuit chip package according to claim 1, wherein the molded underfill material includes epoxy and between 70 and 90 percent filler material.
8. The integrated circuit chip package according to claim 1, wherein a distance between the integrated circuit chip and the substrate is approximately 0.002 - 0.006 inches.
9. A method of underfilling an integrated circuit chip which has been electrically interconnected to a substrate, the method of underfilling comprising: placing the integrated circuit chip and substrate within a mold cavity; injecting a mold compound into the mold cavity; underfilling a space between the integrated circuit chip and the substrate with the mold compound by the pressure of injection of the mold compound into the mold cavity; and allowing air to escape from between the integrated circuit chip and the substrate during underfilling through a vent in the substrate.
10. The method of underfilling according to claim 9, wherein the mold compound passes into the vent in the substrate to insure complete underfilling of all spaces between the integrated circuit chip and the substrate.
11. The method of underfilling according to claim 9, wherein excess mold compound passes into an overflow cavity provided in the mold adjacent the vent at a side of the substrate opposite the integrated circuit chip.
12. The method of underfilling according to claim 9, wherein excess mold compound is vented out of the mold cavity to prevent the pressure in the mold cavity from reaching a predetermined level which crushes the electrical interconnections between the integrated circuit chip and the substrate.
13. The method of underfilling according to claim 9, wherein the mold compound is a transfer molding compound.
14. The method of underfilling according to claim 9, wherein the integrated circuit chip is encapsulated by the mold compound injected into the mold cavity.
15. The method of underfilling according to claim 9, wherein the mold compound includes epoxy and between 70 and 90 percent filler material.
PCT/US1999/010771 1997-10-29 1999-05-14 Chip package with molded underfill WO2000070678A1 (en)

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US08/959,927 US6038136A (en) 1997-10-29 1997-10-29 Chip package with molded underfill
PCT/US1999/010771 WO2000070678A1 (en) 1997-10-29 1999-05-14 Chip package with molded underfill
KR1020017014402A KR20020035477A (en) 1999-05-14 1999-05-14 Chip package with molded underfill
JP2000619029A JP2003500833A (en) 1999-05-14 1999-05-14 Chip package with mold underfill
EP99923109A EP1190448A4 (en) 1999-05-14 1999-05-14 Chip package with molded underfill

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US08/959,927 US6038136A (en) 1997-10-29 1997-10-29 Chip package with molded underfill
PCT/US1999/010771 WO2000070678A1 (en) 1997-10-29 1999-05-14 Chip package with molded underfill

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Families Citing this family (110)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5981312A (en) * 1997-06-27 1999-11-09 International Business Machines Corporation Method for injection molded flip chip encapsulation
JP2000339648A (en) * 1999-05-24 2000-12-08 Tdk Corp Manufacture of magnetic head device
US6207476B1 (en) 1999-06-10 2001-03-27 Vlsi Technology, Inc. Methods of packaging an integrated circuit and methods of forming an integrated circuit package
US6490166B1 (en) 1999-06-11 2002-12-03 Intel Corporation Integrated circuit package having a substrate vent hole
JP2001044137A (en) * 1999-08-04 2001-02-16 Hitachi Ltd Electronic device and manufacture of the same
US6329220B1 (en) 1999-11-23 2001-12-11 Micron Technology, Inc. Packages for semiconductor die
US6338985B1 (en) 2000-02-04 2002-01-15 Amkor Technology, Inc. Making chip size semiconductor packages
SE517086C2 (en) * 2000-08-08 2002-04-09 Ericsson Telefon Ab L M Method for securing solder beads and any components attached to one and the same side of a substrate
US6559537B1 (en) * 2000-08-31 2003-05-06 Micron Technology, Inc. Ball grid array packages with thermally conductive containers
US6632704B2 (en) * 2000-12-19 2003-10-14 Intel Corporation Molded flip chip package
US20020110956A1 (en) * 2000-12-19 2002-08-15 Takashi Kumamoto Chip lead frames
US6772512B2 (en) 2001-01-13 2004-08-10 Siliconware Precision Industries Co., Ltd. Method of fabricating a flip-chip ball-grid-array package without causing mold flash
US6451625B1 (en) * 2001-01-13 2002-09-17 Siliconware Precision Industries, Co., Ltd. Method of fabricating a flip-chip ball-grid-array package with molded underfill
US6610560B2 (en) 2001-05-11 2003-08-26 Siliconware Precision Industries Co., Ltd. Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same
TW486793B (en) 2001-05-29 2002-05-11 Siliconware Precision Industries Co Ltd Packaging method for preventing a low viscosity encapsulant from flashing
US6555924B2 (en) 2001-08-18 2003-04-29 Siliconware Precision Industries Co., Ltd. Semiconductor package with flash preventing mechanism and fabrication method thereof
US6693239B2 (en) * 2001-09-06 2004-02-17 Delphi Technologies Inc. Overmolded circuit board with underfilled surface-mount component and method therefor
SG120053A1 (en) * 2001-10-05 2006-03-28 Advanced Systems Automation Apparatus for molding a semiconductor wafer and process therefor
US6963142B2 (en) * 2001-10-26 2005-11-08 Micron Technology, Inc. Flip chip integrated package mount support
SG107567A1 (en) * 2001-11-07 2004-12-29 Advanced Systems Automation Method and apparatus for forming a flip chip semiconductor package and method for producing a substrate for the flip chip semiconductor package
US6677179B2 (en) 2001-11-16 2004-01-13 Indium Corporation Of America Method of applying no-flow underfill
JP2003229443A (en) * 2002-02-01 2003-08-15 Hitachi Ltd Semiconductor device and its manufacturing method
TW559960B (en) * 2002-09-19 2003-11-01 Siliconware Precision Industries Co Ltd Fabrication method for ball grid array semiconductor package
US20060147719A1 (en) * 2002-11-22 2006-07-06 Slawomir Rubinsztajn Curable composition, underfill, and method
US20050048291A1 (en) * 2003-08-14 2005-03-03 General Electric Company Nano-filled composite materials with exceptionally high glass transition temperature
US20040102529A1 (en) * 2002-11-22 2004-05-27 Campbell John Robert Functionalized colloidal silica, dispersions and methods made thereby
US20040101688A1 (en) * 2002-11-22 2004-05-27 Slawomir Rubinsztajn Curable epoxy compositions, methods and articles made therefrom
US20050181214A1 (en) * 2002-11-22 2005-08-18 John Robert Campbell Curable epoxy compositions, methods and articles made therefrom
US20060012035A1 (en) * 2002-12-10 2006-01-19 Infineon Technologies Ag Method of packaging integrated circuits, and integrated circuit packages produced by the method
US20050008865A1 (en) * 2003-07-07 2005-01-13 General Electric Company Curable epoxy compositions and articles made therefrom
US20050028361A1 (en) * 2003-08-07 2005-02-10 Indium Corporation Of America Integrated underfill process for bumped chip assembly
TWI244145B (en) * 2004-06-24 2005-11-21 Siliconware Precision Industries Co Ltd Method for fabricating semiconductor package
TWI244707B (en) * 2004-06-24 2005-12-01 Siliconware Precision Industries Co Ltd Method for fabricating semiconductor package
TWI240393B (en) * 2004-09-29 2005-09-21 Siliconware Precision Industries Co Ltd Flip-chip ball grid array chip packaging structure and the manufacturing process for the same
WO2006052616A1 (en) 2004-11-03 2006-05-18 Tessera, Inc. Stacked packaging improvements
EP1897426A2 (en) * 2005-05-18 2008-03-12 President And Fellows Of Harvard College Fabrication of conductive pathways, microcircuits and microstructures in microfluidic networks
US7408786B2 (en) * 2005-06-13 2008-08-05 Research In Motion Limited Electrical connector and system for a component in an electronic device
US7510108B2 (en) * 2005-07-26 2009-03-31 Delphi Technologies, Inc. Method of making an electronic assembly
US8058101B2 (en) * 2005-12-23 2011-11-15 Tessera, Inc. Microelectronic packages and methods therefor
TWM305962U (en) * 2006-04-21 2007-02-01 Powertech Technology Inc Ball grid array package structure
TWI309880B (en) * 2006-09-11 2009-05-11 Siliconware Precision Industries Co Ltd Semiconductor chip and package structure and fabrication method thereof
US20080067650A1 (en) * 2006-09-15 2008-03-20 Hong Kong Applied Science and Technology Research Institute Company Limited Electronic component package with EMI shielding
US7898093B1 (en) 2006-11-02 2011-03-01 Amkor Technology, Inc. Exposed die overmolded flip chip package and fabrication method
US7833456B2 (en) 2007-02-23 2010-11-16 Micron Technology, Inc. Systems and methods for compressing an encapsulant adjacent a semiconductor workpiece
TWI326475B (en) * 2007-03-03 2010-06-21 Siliconware Precision Industries Co Ltd Method for fabricating semiconductor device and carrier applied therein
TW200839969A (en) * 2007-03-21 2008-10-01 Advanced Semiconductor Eng Semiconductor package and the method for manufacturing the same
US7939382B2 (en) * 2007-06-28 2011-05-10 Sandisk Corporation Method of fabricating a semiconductor package having through holes for molding back side of package
US7952179B2 (en) * 2007-06-28 2011-05-31 Sandisk Corporation Semiconductor package having through holes for molding back side of package
US7781899B2 (en) * 2008-02-27 2010-08-24 Infineon Technologies Ag Leadframe having mold lock vent
US7732937B2 (en) * 2008-03-04 2010-06-08 Infineon Technologies Ag Semiconductor package with mold lock vent
US20110216514A1 (en) * 2010-03-03 2011-09-08 Mutual-Tek Industries Co., Ltd. Combined multilayer circuit board having embedded components and manufacturing method of the same
US20120314390A1 (en) * 2010-03-03 2012-12-13 Mutual-Tek Industries Co., Ltd. Multilayer circuit board
DE102010026843A1 (en) 2010-07-12 2012-01-12 Epcos Ag Module package and manufacturing process
US8482111B2 (en) 2010-07-19 2013-07-09 Tessera, Inc. Stackable molded microelectronic packages
US9159708B2 (en) 2010-07-19 2015-10-13 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
TW201208008A (en) * 2010-08-05 2012-02-16 Advanced Semiconductor Eng Semiconductor package
US20120098114A1 (en) * 2010-10-21 2012-04-26 Nokia Corporation Device with mold cap and method thereof
KR101075241B1 (en) 2010-11-15 2011-11-01 테세라, 인코포레이티드 Microelectronic package with terminals on dielectric mass
US20120146206A1 (en) 2010-12-13 2012-06-14 Tessera Research Llc Pin attachment
KR101128063B1 (en) 2011-05-03 2012-04-23 테세라, 인코포레이티드 Package-on-package assembly with wire bonds to encapsulation surface
US8618659B2 (en) 2011-05-03 2013-12-31 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US8872318B2 (en) 2011-08-24 2014-10-28 Tessera, Inc. Through interposer wire bond using low CTE interposer with coarse slot apertures
US8404520B1 (en) 2011-10-17 2013-03-26 Invensas Corporation Package-on-package assembly with wire bond vias
US8946757B2 (en) 2012-02-17 2015-02-03 Invensas Corporation Heat spreading substrate with embedded interconnects
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8372741B1 (en) 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US8835228B2 (en) 2012-05-22 2014-09-16 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
KR101965127B1 (en) 2012-10-29 2019-04-04 삼성전자 주식회사 Semiconductor package and method for fabricating the same
US8975738B2 (en) 2012-11-12 2015-03-10 Invensas Corporation Structure for microelectronic packaging with terminals on dielectric mass
US8878353B2 (en) 2012-12-20 2014-11-04 Invensas Corporation Structure for microelectronic packaging with bond elements to encapsulation surface
US9136254B2 (en) 2013-02-01 2015-09-15 Invensas Corporation Microelectronic package having wire bond vias and stiffening layer
US9034696B2 (en) 2013-07-15 2015-05-19 Invensas Corporation Microelectronic assemblies having reinforcing collars on connectors extending through encapsulation
US9023691B2 (en) 2013-07-15 2015-05-05 Invensas Corporation Microelectronic assemblies with stack terminals coupled by connectors extending through encapsulation
US8883563B1 (en) 2013-07-15 2014-11-11 Invensas Corporation Fabrication of microelectronic assemblies having stack terminals coupled by connectors extending through encapsulation
US9167710B2 (en) 2013-08-07 2015-10-20 Invensas Corporation Embedded packaging with preformed vias
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9607863B1 (en) 2013-08-09 2017-03-28 Altera Corporation Integrated circuit package with vacant cavity
US20150076714A1 (en) 2013-09-16 2015-03-19 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US9515006B2 (en) 2013-09-27 2016-12-06 Freescale Semiconductor, Inc. 3D device packaging using through-substrate posts
US9508702B2 (en) 2013-09-27 2016-11-29 Freescale Semiconductor, Inc. 3D device packaging using through-substrate posts
US9508701B2 (en) 2013-09-27 2016-11-29 Freescale Semiconductor, Inc. 3D device packaging using through-substrate pillars
US9087815B2 (en) 2013-11-12 2015-07-21 Invensas Corporation Off substrate kinking of bond wire
US9082753B2 (en) 2013-11-12 2015-07-14 Invensas Corporation Severing bond wire by kinking and twisting
US9583456B2 (en) 2013-11-22 2017-02-28 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9263394B2 (en) 2013-11-22 2016-02-16 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9379074B2 (en) 2013-11-22 2016-06-28 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9917068B2 (en) * 2014-03-14 2018-03-13 Taiwan Semiconductor Manufacturing Company Package substrates, packaged semiconductor devices, and methods of packaging semiconductor devices
US9214454B2 (en) 2014-03-31 2015-12-15 Invensas Corporation Batch process fabrication of package-on-package microelectronic assemblies
US10381326B2 (en) 2014-05-28 2019-08-13 Invensas Corporation Structure and method for integrated circuits packaging with increased density
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9888579B2 (en) 2015-03-05 2018-02-06 Invensas Corporation Pressing of wire bond wire tips to provide bent-over tips
US9502372B1 (en) 2015-04-30 2016-11-22 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10490528B2 (en) 2015-10-12 2019-11-26 Invensas Corporation Embedded wire bond wires
US9490222B1 (en) 2015-10-12 2016-11-08 Invensas Corporation Wire bond wires for interference shielding
US10332854B2 (en) 2015-10-23 2019-06-25 Invensas Corporation Anchoring structure of fine pitch bva
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US10299368B2 (en) 2016-12-21 2019-05-21 Invensas Corporation Surface integrated waveguides and circuit structures therefor
US11282717B2 (en) 2018-03-30 2022-03-22 Intel Corporation Micro-electronic package with substrate protrusion to facilitate dispense of underfill between a narrow die-to-die gap
JP2020129608A (en) * 2019-02-08 2020-08-27 セイコーエプソン株式会社 Method of manufacturing electronic device
CN114571664B (en) * 2022-02-28 2024-01-16 广东风华芯电科技股份有限公司 Flash removing device and method for semiconductor chip packaging

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5371404A (en) * 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
US5408121A (en) * 1992-10-02 1995-04-18 Matsushita Electric Industrial Co., Ltd. Semiconductor device, an image sensor device, and methods for producing the same
US5486995A (en) * 1994-03-17 1996-01-23 Dow Benelux N.V. System for real time optimization
US5535101A (en) * 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4143456A (en) * 1976-06-28 1979-03-13 Citizen Watch Commpany Ltd. Semiconductor device insulation method
JPH0617458B2 (en) * 1987-03-16 1994-03-09 信越化学工業株式会社 Epoxy resin composition
US4770899A (en) * 1987-06-10 1988-09-13 Unisys Corporation Method of coating copper conductors on polyimide with a corrosion resistant metal, and module produced thereby
US5218234A (en) * 1991-12-23 1993-06-08 Motorola, Inc. Semiconductor device with controlled spread polymeric underfill
US5203076A (en) * 1991-12-23 1993-04-20 Motorola, Inc. Vacuum infiltration of underfill material for flip-chip devices
US5557150A (en) * 1992-02-07 1996-09-17 Lsi Logic Corporation Overmolded semiconductor package
US5249101A (en) * 1992-07-06 1993-09-28 International Business Machines Corporation Chip carrier with protective coating for circuitized surface
US5380560A (en) * 1992-07-28 1995-01-10 International Business Machines Corporation Palladium sulfate solution for the selective seeding of the metal interconnections on polyimide dielectrics for electroless metal deposition
US5323947A (en) * 1993-05-03 1994-06-28 Motorola, Inc. Method and apparatus for use in forming pre-positioned solder bumps on a pad arrangement
US5385869A (en) * 1993-07-22 1995-01-31 Motorola, Inc. Semiconductor chip bonded to a substrate and method of making
JP3073644B2 (en) * 1993-12-28 2000-08-07 株式会社東芝 Semiconductor device
US5827999A (en) * 1994-05-26 1998-10-27 Amkor Electronics, Inc. Homogeneous chip carrier package
JPH0831988A (en) * 1994-07-20 1996-02-02 Nec Corp Sealing structure of tape carrier package
FR2722915B1 (en) * 1994-07-21 1997-01-24 Sgs Thomson Microelectronics BGA INJECTION MOLDING HOUSING
US5581122A (en) * 1994-10-25 1996-12-03 Industrial Technology Research Institute Packaging assembly with consolidated common voltage connections for integrated circuits
KR0181615B1 (en) * 1995-01-30 1999-04-15 모리시다 요이치 Semiconductor unit package, semiconductor unit packaging method, and encapsulant for use in semiconductor unit packaging
KR0170024B1 (en) * 1995-10-27 1999-02-01 황인길 Ball grid array semiconductor package having moisture radiating property
US5892290A (en) * 1995-10-28 1999-04-06 Institute Of Microelectronics Highly reliable and planar ball grid array package
US5710071A (en) * 1995-12-04 1998-01-20 Motorola, Inc. Process for underfilling a flip-chip semiconductor device
JP3170199B2 (en) * 1996-03-15 2001-05-28 株式会社東芝 Semiconductor device, method of manufacturing the same, and substrate frame
JPH09260436A (en) * 1996-03-27 1997-10-03 Mitsubishi Electric Corp Semiconductor device
US5700723A (en) * 1996-05-15 1997-12-23 Lsi Logic Corporation Method of packaging an integrated circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5408121A (en) * 1992-10-02 1995-04-18 Matsushita Electric Industrial Co., Ltd. Semiconductor device, an image sensor device, and methods for producing the same
US5535101A (en) * 1992-11-03 1996-07-09 Motorola, Inc. Leadless integrated circuit package
US5371404A (en) * 1993-02-04 1994-12-06 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
US5486995A (en) * 1994-03-17 1996-01-23 Dow Benelux N.V. System for real time optimization

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP1190448A4 *

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