WO2000069236A1 - A thermally enhanced via/bga microwave circuit ceramic package - Google Patents

A thermally enhanced via/bga microwave circuit ceramic package Download PDF

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Publication number
WO2000069236A1
WO2000069236A1 PCT/US2000/012720 US0012720W WO0069236A1 WO 2000069236 A1 WO2000069236 A1 WO 2000069236A1 US 0012720 W US0012720 W US 0012720W WO 0069236 A1 WO0069236 A1 WO 0069236A1
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WO
WIPO (PCT)
Prior art keywords
thermal
heat sink
substrate
backing plate
package
Prior art date
Application number
PCT/US2000/012720
Other languages
French (fr)
Inventor
Robert T. Griffin
Original Assignee
Microsubstrates Corporation
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Filing date
Publication date
Application filed by Microsubstrates Corporation filed Critical Microsubstrates Corporation
Publication of WO2000069236A1 publication Critical patent/WO2000069236A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H05K1/0206—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate by printed thermal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/021—Components thermally connected to metal substrates or heat-sinks by insert mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/141—Analog devices
    • H01L2924/1423—Monolithic Microwave Integrated Circuit [MMIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink

Definitions

  • the present invention relates to the field of microwave circuit packages. More particularly, the invention relates to a thermally enhanced BGA microwave circuit package.
  • the invention provides a thermally enhanced low cost microwave circuit package having an integral heat sink configured to thermally couple with a backing plate of a printed circuit board.
  • the invention is based upon a package such as that disclosed in U.S. Patent No. 5,832,598 which is fully incorporated herein by reference.
  • the invention allows a microwave circuit to function with power in excess of two watts.
  • thermal vias are preferably provided in relatively high density underneath the MMIC of the package. Since thin metalization spreads the heat conducted by the thermal vias and is in conductive contact with a heat sink.
  • the heat sink is preferably constructed of a highly conductive material.
  • the heat sink is dimensioned such that when balls or bumps in the underside of the package are in contact with a PC board in order to perform the intended application of the package, the heat sink will extend through an opening in the PC board therein and into thermal contact with a PC backing plate.
  • alternate embodiment of the invention which provides two sub embodiments employs thermally conductive vias through the mother printed circuit board so that significant amounts of heat from a heat sink on the package can be dissipated.
  • heat is dissipated to atmosphere and in the second sub embodiment heat is dissipated to a metal backing plate which is attached to a mother printed circuit board.
  • FIGURE 1 is a cross-sectional view of the invention with the package lid exploded away from the package;
  • FIGURE 2 is a perspective view of the invention with the package hovering above the PC board and backing plate;
  • FIGURE 3 is a perspective bottom view of the package of the invention
  • FIGURE 4 is an alternate embodiment of the invention where thermal vias are employed extending through the printed circuit board
  • FIGURE 5 is another alternate embodiment of the invention which adds to the embodiment of FIGURE 4 a metal backing plate to further dissipate heat removed by thermal vias extending through the printed circuit board.
  • microwave circuit package substrate 12 which typically is composed of a dielectric material.
  • the substrate also will contain several vias these being either electrically conductive or thermally conductive in nature. Conductive vias are labeled as 14 while thermal vias are labeled as 16.
  • Thin film metallization 18 is generally preferred for the top and bottom surface of the substrate 12 as is known from the art.
  • a microwave circuit chip 20 is positioned centrally in the figure with wire bonds 22 connecting it to the thin film metallization 18.
  • a lid 24 is illustrated suspended above the upper surface of the substrate 12 to which it will be bonded in a completed package. This too is known from the prior art.
  • balls or bumps 26 which extend from the lower surface of the substrate 12 in order to provide electrical contact with PC board traces 28.
  • the invention employs a heat sink 30 thermally conductively attached to the thermal spreading metallization 32 which is bonded to the undersurface of substrate 12 and which is in thermal contact with thermal via 16.
  • Heat sink 30 increases the heat dissipation properties of the package as a whole and therefore allows for higher power dissipation within the microwave circuit package. This is of course beneficial to the art and solves the need of the art.
  • heat sink 30 In order to further spread and dissipate the heat of the microwave circuit, it is contemplated by the inventor hereof to place heat sink 30 in thermal contact with a backing plate 34 of an otherwise conventional PC board 36 which has been modified by providing an opening 38 therein which allows through passage of heat sink 30 such that heat sink 30 may thermally contact backing plate 34 while bumps or balls 26 are in electrical contact with traces 28. It is desirable that heat sink 30 be fully thermally coupled with backing plate 34 which may be achieved by providing carefully machined surfaces that have no surface irregularities to create an air gap which would otherwise function as an insulator.
  • heat sink 30 could be coated with a thermal grease which would then be disposed between heat sink 30 and backing plate 34 to absorb any irregularities in the surfaces of the mating surfaces and ensure that thermal conductivity is maintained in all points thereof.
  • Heat sink 30 is preferably constructed of a tungsten-copper, tungsten-molybdenum or other material with sufficiently high thermal conductivity and of a coefficient of thermal expansion (CTE) that reasonably coincides with that of the package ceramic substrate 12. A reasonable match would be that within the range of about 10% to 20% of the CTE of the substrate.
  • the invention is optimized by ensuring that the CTE of the package (e.g. substrate, heat sink and vias) are closely matched to the CTE of the MMIC chip to be mounted thereon.
  • a PC board 50 does not include an opening as in Figure 2 but rather includes at least one and preferably a plurality of thermal vias 52 through the PC board 50.
  • a heat sink 54 is connected to the ground plane of the circuit package 56 as in the previous embodiment.
  • the heat sink 30 is thicker than the heat sink 54 because heat sink 30 is intended to extend through the PC board 50 whereas heat sink 54 is intended merely to contact the surface of PC board 50 and the thermal vias 52.
  • a thermal grease 58 is preferably applied between heat sink 54 and thermal vias 52.
  • the assembly includes a metal backing plate 64 which conductively removes heat from thermal vias 52, heat sink 54 and microwave circuit chip 60.

Abstract

A thermally enhanced VIA/BGA microwave circuit ceramic package having an integrated heat sink (30) which allows direct thermal coupling with a backing plate (34) of a printed circuit board (36). A configuration allows a low cost substrate material (12) such as an aluminum oxide to be employed for microwave circuit packages that dissipate powers in excess of two watts.

Description

A THERMALLY ENHANCED VIN'BGA MICROWAVE CIRCUIT CERAMIC PACKAGE
BACKGROUND OF THE INVENTION Field of the Invention
The present invention relates to the field of microwave circuit packages. More particularly, the invention relates to a thermally enhanced BGA microwave circuit package.
Prior Art
Prior art microwave circuit packages employing ball grid arrays have become increasingly popular in recent years due to their miserly use of printed circuit board space. A bi -product of more densely populating printed circuit boards is less heat dissipation by convection. Moreover, with the ever increasing demand for higher power electronic devices, market pressure demands that microwave circuit packages dissipate powers in excess of two watts. The conditions of dense population of the printed circuit board and higher power circuit packages makes power dissipation a significant problem with respect to heat. The practical limitation for the generally cost effective Galium Arsenide (GaAs) MMIC packages based upon an aluminum oxide substrate is thus about two watts. Although two watt power dissipation capabilities enable significant electronic devices, power in excess of two watts is now demanded by the electronics industry. While aluminum nitride package substrate material will allow higher powers and apparently solves the problem, the cost is prohibitive and the coefficient of thermal expansion (CTE) mismatch between aluminum nitride and typical PC board materials renders questionable the reliability of the solder joints between the package balls and the PC board. Thus, the art is still in need of a low cost thermally enhanced VIA/BGA microwave circuit ceramic package which can dissipate powers in excess of two watts and have no potential solder joint reliability problems in order to meet market desires.
SUMMARY OF THE INVENTION The above-identified drawbacks of the prior art are overcome or alleviated by the thermally enhanced VIA/BGA microwave circuit ceramic package of the invention.
The invention provides a thermally enhanced low cost microwave circuit package having an integral heat sink configured to thermally couple with a backing plate of a printed circuit board. The invention is based upon a package such as that disclosed in U.S. Patent No. 5,832,598 which is fully incorporated herein by reference. The invention allows a microwave circuit to function with power in excess of two watts.
Thermal energy must be dissipated more rapidly in higher power applications. In order to increase the heat dissipating capability of the package, thermal vias are preferably provided in relatively high density underneath the MMIC of the package. Since thin metalization spreads the heat conducted by the thermal vias and is in conductive contact with a heat sink. The heat sink is preferably constructed of a highly conductive material. The heat sink is dimensioned such that when balls or bumps in the underside of the package are in contact with a PC board in order to perform the intended application of the package, the heat sink will extend through an opening in the PC board therein and into thermal contact with a PC backing plate. By providing an opening in the PC board so that the heat sink makes thermal contact with the backing plate, significantly more heat will be dissipated from the MMIC through thermal conduction thus allowing higher wattage.
In alternate embodiment of the invention which provides two sub embodiments employs thermally conductive vias through the mother printed circuit board so that significant amounts of heat from a heat sink on the package can be dissipated. In the first sub embodiment heat is dissipated to atmosphere and in the second sub embodiment heat is dissipated to a metal backing plate which is attached to a mother printed circuit board.
BRIEF DESCRIPTION OF THE DRAWINGS FIGURE 1 is a cross-sectional view of the invention with the package lid exploded away from the package;
FIGURE 2 is a perspective view of the invention with the package hovering above the PC board and backing plate; and
FIGURE 3 is a perspective bottom view of the package of the invention; FIGURE 4 is an alternate embodiment of the invention where thermal vias are employed extending through the printed circuit board; and
FIGURE 5 is another alternate embodiment of the invention which adds to the embodiment of FIGURE 4 a metal backing plate to further dissipate heat removed by thermal vias extending through the printed circuit board.
DETAILED DESCRIPTION OF THE INVENTION
Referring to Figure 1 , one of ordinary skill in the art will recognize several of the components of the general illustration of Figure 1. More specifically, one should recognize a microwave circuit package substrate 12 which typically is composed of a dielectric material. The substrate also will contain several vias these being either electrically conductive or thermally conductive in nature. Conductive vias are labeled as 14 while thermal vias are labeled as 16. Thin film metallization 18 is generally preferred for the top and bottom surface of the substrate 12 as is known from the art. A microwave circuit chip 20 is positioned centrally in the figure with wire bonds 22 connecting it to the thin film metallization 18. A lid 24 is illustrated suspended above the upper surface of the substrate 12 to which it will be bonded in a completed package. This too is known from the prior art. One of ordinary skill in the art should also recognize balls or bumps 26 which extend from the lower surface of the substrate 12 in order to provide electrical contact with PC board traces 28.
In order to increase the heat dissipation properties of the package as a whole, the invention employs a heat sink 30 thermally conductively attached to the thermal spreading metallization 32 which is bonded to the undersurface of substrate 12 and which is in thermal contact with thermal via 16. Heat sink 30 increases the heat dissipation properties of the package as a whole and therefore allows for higher power dissipation within the microwave circuit package. This is of course beneficial to the art and solves the need of the art.
In order to further spread and dissipate the heat of the microwave circuit, it is contemplated by the inventor hereof to place heat sink 30 in thermal contact with a backing plate 34 of an otherwise conventional PC board 36 which has been modified by providing an opening 38 therein which allows through passage of heat sink 30 such that heat sink 30 may thermally contact backing plate 34 while bumps or balls 26 are in electrical contact with traces 28. It is desirable that heat sink 30 be fully thermally coupled with backing plate 34 which may be achieved by providing carefully machined surfaces that have no surface irregularities to create an air gap which would otherwise function as an insulator. Alternatively heat sink 30 could be coated with a thermal grease which would then be disposed between heat sink 30 and backing plate 34 to absorb any irregularities in the surfaces of the mating surfaces and ensure that thermal conductivity is maintained in all points thereof. Heat sink 30 is preferably constructed of a tungsten-copper, tungsten-molybdenum or other material with sufficiently high thermal conductivity and of a coefficient of thermal expansion (CTE) that reasonably coincides with that of the package ceramic substrate 12. A reasonable match would be that within the range of about 10% to 20% of the CTE of the substrate. The invention is optimized by ensuring that the CTE of the package (e.g. substrate, heat sink and vias) are closely matched to the CTE of the MMIC chip to be mounted thereon.
In an alternate embodiment of the invention, referring to Figure 4 a PC board 50 does not include an opening as in Figure 2 but rather includes at least one and preferably a plurality of thermal vias 52 through the PC board 50. In this embodiment a heat sink 54 is connected to the ground plane of the circuit package 56 as in the previous embodiment. The difference being between the prior embodiment and this embodiment is that the heat sink 30 is thicker than the heat sink 54 because heat sink 30 is intended to extend through the PC board 50 whereas heat sink 54 is intended merely to contact the surface of PC board 50 and the thermal vias 52. In order to account for tolerances in machining, a thermal grease 58 is preferably applied between heat sink 54 and thermal vias 52. It will be understood by those of skill in the art that the invention will function even if thermal grease 58 is omitted although the heat conductivity may be diminished dependent upon machining and how close the sink is to the vias. Significant thermal benefits are achieved by the embodiment of Figure 4 even without a backing plate on PC board 50. This is because the heat sink 54 and thermal vias 52 will draw significant heat away from the chip 60 and will dissipate that heat to atmosphere adjacent surface 62 of PC board 50. In order to remove even more heat from the microwave circuit chip 60 and referring to the embodiment of
Figure 5, the assembly includes a metal backing plate 64 which conductively removes heat from thermal vias 52, heat sink 54 and microwave circuit chip 60.
While preferred embodiments have been shown and described, various modifications and substitutions may be made thereto without departing from the spirit and scope of the invention. Accordingly, it is to be understood that the present invention has been described by way of illustration and not limitation. What is claimed:

Claims

CLAIM 1. A thermally enhanced microwave circuit package comprising: a substrate having a first and a second surface; a circuit chip mounted to said substrate on said first surface; and a heat sink mounted to said second surface.
CLAIM 2. A thermally enhanced microwave circuit package as claimed in Claim 1 wherein said package further includes a cover.
CLAIM 3. A thermally enhanced microwave circuit package as claimed in Claim 1 wherein said heat sink is constructed of a material having a coefficient of thermal expansion which is in the range of 10% to 20% of a coefficient of thermal expansion of said substrate.
CLAIM 4. A thermally enhanced microwave circuit package as claimed in Claim 1 wherein said heat sink is mounted to said substrate by brazing.
CLAIM 5. A thermal management system for high power semiconductor devices comprising: a substrate having a first and a second surface; a circuit chip mounted to said substrate on said first surface; a heat sink mounted to said second surface; a printed circuit board in electrical contact with said circuit chip, said board having an opening through which said heat sink extends; and a backing plate mounted to said printed circuit board and in thermal contact with said heat sink.
CLAIM 6. A thermal management system for high power semiconductor as claimed in Claim 5 wherein said thermal contact between said heat sink and said backing plate is augmented with thermal grease.
CLAIM 7. A thermal management system for high power semiconductor as claimed in Claim 5 wherein said heat sink is constructed of a material having a coefficient of thermal expansion which is in the range of 10% to 20% of a coefficient of thermal expansion of said substrate.
CLAIM 8. A method for thermal management of a semiconductor device comprising: conducting thermal energy for a circuit chip to at least one thermal via; thermally coupling said at least one via to a heat sink extending said heat sink through a printed circuit board to a backing plate; and thermally coupling said heat sink to said backing plate.
CLAIM 9. A method for thermal management of a semiconductor device as claimed in Claim 8 wherein said thermal coupling of said heat sink to said backing plate is accomplished by applying thermal grease to an interface therebetween.
CLAIM 10. A thermally enhanced microwave BGA circuit package comprising: a substrate having at least on thermal via therein; a circuit chip mounted on the substrate; and a heat sink mounted to said substrate wherein the coefficients of thermal expansion of the substrate, heat sink and at least one thermal via are matched to those of the circuit chip.
CLAIM 11. A thermal management system for high power semiconductor devices comprising: a substrate having a first and a second surface; a circuit chip mounted to said substrate on said first surface; a heat sink mounted to said second surface; and a printed circuit board in electrical contact with said circuit chip, said board having at least one thermally conductive via extending therethrough and in thermally conductive contact with said heat sink.
CLAIM 12. A thermal management system as claimed in Claim 11 wherein a thermal grease is disposed between said printed circuit board and said heat sink to increase thermal conductivity.
CLAIM 13. A thermal management system as claimed in Claim 11 wherein said thermal management system further includes a backing plate mounted to said printed circuit board, said backing plate being in thermal conductivity with said at least one thermal via.
PCT/US2000/012720 1999-05-10 2000-05-09 A thermally enhanced via/bga microwave circuit ceramic package WO2000069236A1 (en)

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US30766099A 1999-05-10 1999-05-10
US09/307,660 1999-05-10

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002078086A2 (en) * 2001-03-27 2002-10-03 Ericsson Inc. Power transistor package with integrated flange for surface mount heat removal
WO2003090278A2 (en) * 2002-04-19 2003-10-30 Intel Corporation Dual-sided heat removal system
EP2224794A1 (en) * 2007-12-14 2010-09-01 Huawei Technologies Co., Ltd. Printed circuit board, manufacturing method and radio-frequency apparatus thereof
WO2015047350A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Dual-sided die packages
EP2911484A3 (en) * 2014-02-21 2016-01-27 LG Innotek Co., Ltd. Printed circuit board and method of fabricating the same
EP3327767A4 (en) * 2015-07-24 2019-04-03 Nec Corporation Mount structure, method of manufacturing mount structure, and wireless device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922324A (en) * 1987-01-20 1990-05-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
US5710459A (en) * 1995-05-12 1998-01-20 Industrial Technology Research Institute Integrated circuit package provided with multiple heat-conducting paths for enhancing heat dissipation and wrapping around cap for improving integrity and reliability
US5856911A (en) * 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
US6060777A (en) * 1998-07-21 2000-05-09 Intel Corporation Underside heat slug for ball grid array packages

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922324A (en) * 1987-01-20 1990-05-01 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
US5710459A (en) * 1995-05-12 1998-01-20 Industrial Technology Research Institute Integrated circuit package provided with multiple heat-conducting paths for enhancing heat dissipation and wrapping around cap for improving integrity and reliability
US5856911A (en) * 1996-11-12 1999-01-05 National Semiconductor Corporation Attachment assembly for integrated circuits
US6060777A (en) * 1998-07-21 2000-05-09 Intel Corporation Underside heat slug for ball grid array packages

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002078086A3 (en) * 2001-03-27 2003-07-31 Ericsson Inc Power transistor package with integrated flange for surface mount heat removal
WO2002078086A2 (en) * 2001-03-27 2002-10-03 Ericsson Inc. Power transistor package with integrated flange for surface mount heat removal
WO2003090278A2 (en) * 2002-04-19 2003-10-30 Intel Corporation Dual-sided heat removal system
WO2003090278A3 (en) * 2002-04-19 2003-12-18 Intel Corp Dual-sided heat removal system
CN100380642C (en) * 2002-04-19 2008-04-09 英特尔公司 Dual-sided heat removal system
EP2986088A1 (en) * 2007-12-14 2016-02-17 Huawei Technologies Co., Ltd. Printed circuit board, manufacturing method thereof and radio-frequency device
EP2224794A1 (en) * 2007-12-14 2010-09-01 Huawei Technologies Co., Ltd. Printed circuit board, manufacturing method and radio-frequency apparatus thereof
EP2224794A4 (en) * 2007-12-14 2011-03-23 Huawei Tech Co Ltd Printed circuit board, manufacturing method and radio-frequency apparatus thereof
US8633393B2 (en) 2007-12-14 2014-01-21 Huawei Technologies Co., Ltd. Printed circuit board, manufacturing method thereof and radio-frequency device
WO2015047350A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Dual-sided die packages
US9711428B2 (en) 2013-09-27 2017-07-18 Intel Corporation Dual-sided die packages
US10361142B2 (en) 2013-09-27 2019-07-23 Intel Corporation Dual-sided die packages
EP2911484A3 (en) * 2014-02-21 2016-01-27 LG Innotek Co., Ltd. Printed circuit board and method of fabricating the same
US9942985B2 (en) 2014-02-21 2018-04-10 Lg Innotek Co., Ltd. Printed circuit board and method of fabricating the same
EP3327767A4 (en) * 2015-07-24 2019-04-03 Nec Corporation Mount structure, method of manufacturing mount structure, and wireless device
US10506702B2 (en) 2015-07-24 2019-12-10 Nec Corporation Mounting structure, method for manufacturing mounting structure, and radio device

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