WO2000068991A1 - Pbga package with integrated ball grid - Google Patents

Pbga package with integrated ball grid Download PDF

Info

Publication number
WO2000068991A1
WO2000068991A1 PCT/FR2000/001201 FR0001201W WO0068991A1 WO 2000068991 A1 WO2000068991 A1 WO 2000068991A1 FR 0001201 W FR0001201 W FR 0001201W WO 0068991 A1 WO0068991 A1 WO 0068991A1
Authority
WO
WIPO (PCT)
Prior art keywords
housing
balls
integrated circuit
grid
cavity
Prior art date
Application number
PCT/FR2000/001201
Other languages
French (fr)
Inventor
Claude Petit
Yves Stricot
Original Assignee
Bull S.A.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Bull S.A. filed Critical Bull S.A.
Priority to EP00925385A priority Critical patent/EP1099253A1/en
Priority to JP2000617492A priority patent/JP3520049B2/en
Priority to US09/743,061 priority patent/US6384471B1/en
Publication of WO2000068991A1 publication Critical patent/WO2000068991A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01012—Magnesium [Mg]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate

Definitions

  • the present invention relates to the field of connection of BGA boxes, Anglo-Saxon abbreviations for "Bail Grid Array”, on electronic cards and relates more particularly to PBGA boxes, Anglo-Saxon abbreviations for "Plastic BGA”.
  • Standard boxes of the PBGA type with cavity called “cavity down” in English terminology, include a cavity in which is housed an integrated circuit, also called “chip” or “chip” in English terminology.
  • connection areas of the chip on the housing and the connection areas of a network of solder balls on the housing are arranged on the same level of the housing generally corresponding to the underside of the housing, c that is to say the face which is opposite the printed circuit board when the housing is assembled on the card.
  • the network of balls electrically and mechanically connects the chip to the printed circuit board.
  • an encapsulation material is used, by example an electrically neutral thermosetting resin, which coats the outside of the chip and its connections.
  • Another type of drawback relates to the phenomenon of sagging of the balls during assembly of the housing on the printed circuit board. This phenomenon is also known by the Anglo-Saxon terminology "collapse". In fact, during assembly, the surface tension forces of the alloy constituting the balls, typically of remelted tin-lead, causes the balls to sag on the card.
  • the subject of the invention is a case for an integrated circuit, of the type comprising a cavity in which the integrated circuit is fixed, the active face of the integrated circuit being electrically connected to the case at the connection level of a network of balls. on the box ensuring a mechanical and electrical connection between the integrated circuit and a printed circuit board on which the box must be assembled.
  • the housing is characterized in that it comprises an additional, rigid and electrically neutral layer, attached to the connection level of the integrated circuit and of the balls, and containing the balls.
  • the invention has the particular advantage of making both the mounting of the balls on the housing, also called “billing" of the housing, and of ensuring the protection of the connections and of the chip.
  • FIG. 3 a partial cross-sectional view of a housing according to the invention.
  • the same elements are designated by the same references and the scale of the drawings is not respected.
  • Figure 1 illustrates the underside of a PBGA package.
  • FIG. 2 illustrates the casing of FIG. 1 in partial section along the cutting axis AA of FIG. 1.
  • a "cavity down" PBGA box is made up of a rigid support 1 of generally parallelepipedal shape made of copper, comprising a cavity
  • the support 1 also supports a generally flexible dielectric substrate 6, disposed at the periphery of the cavity 2 and therefore of the chip 3.
  • the substrate 6 supports, on one of its faces, conductive tracks 7i arranged according to a determined design comprising the connection zones of the bonding wires and of the balls.
  • connection intermediaries 11 i here connection wires also called “bonding" wires.
  • the conductive tracks 7i extend from the cavity 2 and radially with respect to the cavity 2 and terminate respectively in conductive pads
  • the studs 12i are intended to respectively receive solder balls 13i as shown in FIGS. 2 and 3.
  • Its balls 13i forming a network of balls, provide the mechanical and electrical connection between the chip 3 and the card once the housing has been assembled on the card.
  • the wiring of the wires 11 i and of the balls 13i on the housing is carried out on the same level Ne corresponding to the plane of the tracks 7i and of the conductive pads 12i.
  • FIG. 3 schematically illustrates, also in a partial transverse section along the cutting axis AA of FIG. 1, a PBGA box according to the invention.
  • the housing comprises the same basic structure of the housing illustrated in FIG. 2 and also comprises, at a level below the level Ne of connection of the wires 11 i and of the balls 13i on the housing, an additional layer 14 containing the balls 13i and which extends between the balls 13i while remaining set back with respect to the cavity 2 so as not to cover the connection zone Zc of the wires 11 i on the housing.
  • the layer 14 has a determined mechanical rigidity and is electrically neutral.
  • This layer 14 defines a grid comprising a plurality of openings 15i in which the balls 13i are respectively housed. The openings are chosen to be wide enough to contain the balls 13i with a slight play of the order of 0.2 mm.
  • the grid 14 can be attached by gluing in the form of resin or in the form of a preform, when the box is assembled on the card, or can be integrated into the structure of the box during its manufacture.
  • the grid 14 is attached by gluing.
  • a layer of adhesive 16 is applied in such a way that it does not cover the connection pads 12i and that it cannot penetrate inside the openings 15i of the grid 14 using, for example, a screen printing screen. or a preform.
  • a coating material 17 fills the space left free by the grid 14 and which forms a second cavity 18 wider than the first cavity 2 containing the chip 3.
  • the grid 14 plays the dual role of a grid for positioning the balls 13i and of an obstacle for the coating material 17 covering the active face 10 of the chip 3 and its connection wires 11 i.
  • this additional layer or grid 14 also plays the role of spacer in the case of packages with very high weight per ball, typically above 50 mg per ball. This is particularly the case for housings having an integrated heat sink covering the entire surface of the housing.
  • This role of spacer makes it possible to guarantee a predefined distance of the housing from the card and avoids uncontrolled collapse of the balls.
  • this layer ensures electrical insulation between the balls when the housing is mounted on the card. It has the additional advantage of being able to increase the volume of solder by taking balls of larger diameter, for example 0.96 mm instead of 0.76 mm for the same pitch between balls of 1.27 mm. The reliability under thermal cycle of the assembled housing is then increased. This characteristic is particularly important in applications with high temperature constraints, in particular in automotive applications.
  • the height of the welded joints on a card, "ring" in English terminology can be greater, typically ON mm instead of 0.5 mm.
  • a welded joint typically corresponds to a copper deposit on which the components are welded to the periphery of the housing.
  • the box can then have a cheaper “Gold electroless” finish than a “Gold electrolytic” finish and without the presence of antennas (metallization feeders).
  • the dimensions of a case according to the invention are given below, as well as the materials used for each of the constituent layers of the case and their respective thicknesses. This example, given for information only, does not take dimensional tolerances into account.
  • the housing defines a parallelepiped with a side of 35 mm.
  • the central cavity 2 defines a square with a side of 15 mm and its depth is 40 mm. It is intended to receive a chip 3 of generally parallelepiped shape with a side of 13 mm and a thickness of 0.40 mm.
  • the chip 5 is fixed to the bottom 4 of the cavity 2 by means of an adhesive 5 of 0.10 mm thick which is an epoxy resin loaded with silver.
  • the sides of the cavity 2 are respectively parallel to the sides of the housing.
  • the housing consists of a support 1 0.7 mm thick overall and the thickness of the bottom of the support 1, corresponding to the bottom 4 of the cavity 2, is equal to 0.3 mm.
  • the support 1 is made of copper.
  • the support 1 receives on its underside, a stack of several layers which are described successively in increasing order of the thickness of the housing.
  • the first layer 9 is a layer of epoxy adhesive 0.10 mm thick.
  • the second layer 8 corresponds to the conductive plane which is made of copper with a thickness of 17 ⁇ m.
  • the third layer 6 corresponds to the flexible substrate proper which is made of polyimide with a thickness of 50 ⁇ m.
  • the fourth layer 7i corresponds to the conductive tracks which are made of copper with a thickness of 17 ⁇ m.
  • the fifth layer 16 is a layer of glue 0.10 mm thick intended to fix the sixth layer 14 called “additional layer” on the fourth layer 7i of the stack, that is to say on the level of connection
  • the additional layer 14 is made of 0.5 mm thick epoxy resin. It defines a grid with a pitch of 1.27 mm comprising a plurality of openings 15i intended to contain the plurality of balls 13i which in the example chosen have a diameter of 0.96 mm.
  • the openings 15i have a generally cylindrical shape of circular section.
  • the diameter of the openings 15i of the grid 14 is substantially greater than the diameter of the balls 13i and is of the order of 1.05 mm.
  • the diameter of the balls and the maximum acceptable height after reflow define the maximum thickness of the grid 14 playing its role of spacer and positioning of the balls 13i on the housing.
  • a coating material 17, for example an epoxy adhesive, covers the active face 10 of the chip 3 as well as the connection wires 11 i. It is stopped in its expansion by the fifth and sixth layers of the stack, respectively 16 and 14, and is enclosed in a second cavity 18 wider than the first and defined by the inner periphery of the grid 14 bonded to the flexible substrate 6.

Abstract

The invention concerns an integrated circuit package (5) comprising a cavity (2) wherein the integrated circuit (5) is fixed, the active surface (10) of the integrated circuit (3) being electrically connected to the package at the connection level (Nc) of a ball array (13i) on the package providing a mechanical and electrical link between the integrated circuit (5) and a printed circuit card whereon the package is to be assembled. The invention is characterised in that it comprises a rigid and electrically neutral additional layer (14) directly mounted on the connection level (Nc) of the integrated circuit (5) and the balls (13i), and contains the balls (13i). The invention is useful in particular for connections of BGA and PBGA packages.

Description

Boîtier PBGA à grille de billage intégréePBGA box with integrated billing grid
La présente invention se rapporte au domaine de la connectique des boîtiers BGA, abréviations anglo-saxonnes pour "Bail Grid Array", sur des cartes électroniques et concerne plus particulièrement les boîtiers PBGA, abréviations anglo-saxonnes pour "Plastic BGA".The present invention relates to the field of connection of BGA boxes, Anglo-Saxon abbreviations for "Bail Grid Array", on electronic cards and relates more particularly to PBGA boxes, Anglo-Saxon abbreviations for "Plastic BGA".
Les boîtiers standards de type PBGA à cavité, appelée "cavity down" en terminologie anglo-saxonne, comportent une cavité dans laquelle est logé un circuit intégré, appelé également "puce" ou "chip" en terminologie anglo- saxonne.Standard boxes of the PBGA type with cavity, called "cavity down" in English terminology, include a cavity in which is housed an integrated circuit, also called "chip" or "chip" in English terminology.
Dans ce type de boîtier, les zones de connexion de la puce sur le boîtier et les zones de connexion d'un réseau de billes de soudure sur le boîtier sont disposées sur un même niveau du boîtier correspondant généralement à la face inférieure du boîtier, c'est-à-dire la face qui se trouve en regard de la carte de circuit imprimé quand le boîtier est assemblé sur la carte.In this type of housing, the connection areas of the chip on the housing and the connection areas of a network of solder balls on the housing are arranged on the same level of the housing generally corresponding to the underside of the housing, c that is to say the face which is opposite the printed circuit board when the housing is assembled on the card.
Le réseau de billes relie électriquement et mécaniquement la puce à la carte de circuit imprimé.The network of balls electrically and mechanically connects the chip to the printed circuit board.
Pour protéger mécaniquement et vis-à-vis de l'environnement, la face active de la puce, constituée d'une couche semi-conductrice, et les connexions, par exemple des fils de bonding, on utilise un matériau d'encapsulation, par exemple une résine thermodurcissable et électriquement neutre, qui enrobe l'extérieur de la puce et ses connexions.To protect mechanically and vis-à-vis the environment, the active face of the chip, consisting of a semiconductor layer, and the connections, for example bonding wires, an encapsulation material is used, by example an electrically neutral thermosetting resin, which coats the outside of the chip and its connections.
Un tel procédé est notamment décrit dans le brevet américain US5397921A. Ce procédé appliqué au type de boîtier BGA tel que décrit ci-dessus a pour inconvénient que la hauteur des fils ainsi enrobés par la résine doit être compatible avec la hauteur des billes qui est typiquement de l'ordre de 0,6 mm pour un pas entre les billes de l'ordre de 1 ,27 mm.Such a method is notably described in American patent US5397921A. This method applied to the type of BGA box as described above has the disadvantage that the height of the wires thus coated with the resin must be compatible with the height of the balls which is typically of the order of 0.6 mm for one pitch between the balls of the order of 1.27 mm.
Ceci impose quasi exclusivement l'emploi de la technique "Or", dite "bail bonding" en terminologie anglo-saxonne, et le boîtier doit alors comporter une metallisation "Or électrolytique" nécessitant l'emploi de "nourrices" qui après metallisation laisse subsister des bouts de fils qui sont autant d'antennes pour les hautes fréquences et notamment pour les signaux d'horloge. Outre la maîtrise des boucles de câblage des fils, il faut également maîtriser la hauteur de l'enrobage pour recouvrir complètement les fils. En général, un cordon de colle très visqueuse est déposé autour des zones de connexions des fils sur le boîtier afin de servir de mur d'arrêt à la résine d'enrobage qui elle au contraire est par nature très fluide afin d'enrober correctement les fils et la puce. Ce mur permet également d'éviter un débordement de la résine d'enrobage sur les zones de connexion des billes sur le boîtier.This almost exclusively requires the use of the "Gold" technique, called "bail bonding" in English terminology, and the housing must then include a metallization "Electrolytic Gold" requiring the use of "nurses" which after metallization leaves bits of wire which are so many antennas for the high frequencies and in particular for the clock signals. In addition to mastering the wiring loops of the wires, it is also necessary to control the height of the coating to completely cover the wires. In general, a bead of very viscous glue is deposited around the connection areas of the wires on the housing in order to serve as a stop wall for the coating resin which, on the contrary, is by nature very fluid in order to properly coat the son and chip. This wall also makes it possible to avoid an overflow of the coating resin on the connection zones of the balls on the housing.
Un autre type d'inconvénient concerne le phénomène d'affaissement des billes lors de l'assemblage du boîtier sur la carte de circuit imprimé. Ce phénomène est également connu sous la terminologie anglo-saxonne "collapse". En effet, lors de l'assemblage, les forces de tension superficielle de l'alliage constituant les billes, typiquement de l'Etain-Plomb refondu, entraîne un affaissement des billes sur la carte.Another type of drawback relates to the phenomenon of sagging of the balls during assembly of the housing on the printed circuit board. This phenomenon is also known by the Anglo-Saxon terminology "collapse". In fact, during assembly, the surface tension forces of the alloy constituting the balls, typically of remelted tin-lead, causes the balls to sag on the card.
Ainsi, une bille ayant typiquement une hauteur de 0,6 mm pour un pas de 1 ,27 mm et un diamètre initial avant assemblage de 0,76 mm verra sa hauteur décroître de 0,2 mm environ. Ce phénomène est amplifié notamment quant un dissipateur thermique intégré recouvre toute la surface supérieure du boîtier ; les conséquences pouvant être alors de court-circuiter les billes entre elles. L'invention a notamment pour but de pallier les inconvénients précités. A cet effet, l'invention a pour objet un boîtier pour circuit intégré, du type comportant une cavité dans laquelle est fixé le circuit intégré, la face active du circuit intégré étant connectée électriquement au boîtier au niveau de connexion d'un réseau de billes sur le boîtier assurant une liaison mécanique et électrique entre le circuit intégré et une carte de circuit imprimé sur laquelle doit être assemblé le boîtier. Le boîtier est caractérisé en ce qu'il comporte une couche supplémentaire, rigide et électriquement neutre, rapportée sur le niveau de connexion du circuit intégré et des billes, et contenant les billes. L'invention a notamment pour avantage de rendre à la fois plus facile le montage des billes sur le boîtier, appelé également "billage" du boîtier, et d'assurer la protection des connexions et de la puce.Thus, a ball typically having a height of 0.6 mm for a pitch of 1.27 mm and an initial diameter before assembly of 0.76 mm will see its height decrease by about 0.2 mm. This phenomenon is amplified in particular when an integrated heat sink covers the entire upper surface of the housing; the consequences could then be to short-circuit the balls between them. The invention particularly aims to overcome the aforementioned drawbacks. To this end, the subject of the invention is a case for an integrated circuit, of the type comprising a cavity in which the integrated circuit is fixed, the active face of the integrated circuit being electrically connected to the case at the connection level of a network of balls. on the box ensuring a mechanical and electrical connection between the integrated circuit and a printed circuit board on which the box must be assembled. The housing is characterized in that it comprises an additional, rigid and electrically neutral layer, attached to the connection level of the integrated circuit and of the balls, and containing the balls. The invention has the particular advantage of making both the mounting of the balls on the housing, also called "billing" of the housing, and of ensuring the protection of the connections and of the chip.
Elle permet de plus, de garantir un éloignement prédéfini du boîtier par rapport à la carte, jouant ainsi un rôle d'entretoise entre le boîtier et la carte.It also makes it possible to guarantee a predefined distance of the housing from the card, thus playing a role of spacer between the housing and the card.
D'autres avantages et caractéristiques de la présente invention apparaîtront à la lecture de la description qui suit faite en référence aux figures annexées qui représentent :Other advantages and characteristics of the present invention will appear on reading the following description made with reference to the appended figures which represent:
- la figure 1 , une vue de dessous d'un boîtier PBGA équipée d'un réseau de billes ;- Figure 1, a bottom view of a PBGA box equipped with an array of balls;
- la figure 2, une vue en coupe partielle transversale du boîtier illustré à la figure 1 ; et- Figure 2, a partial cross-sectional view of the housing illustrated in Figure 1; and
- la figure 3, une vue en coupe partielle transversale d'un boîtier selon l'invention. Sur ces figures les mêmes éléments sont désignés par les mêmes références et l'échelle des dessins n'est pas respectée.- Figure 3, a partial cross-sectional view of a housing according to the invention. In these figures the same elements are designated by the same references and the scale of the drawings is not respected.
D'autre part, la carte de circuit imprimé sur laquelle est assemblée le boîtier n'est pas représentée.On the other hand, the printed circuit board on which the housing is assembled is not shown.
Les méthodes de montage des billes sur le boîtier PBGA, de montage de la puce sur le boîtier, de connexion de la puce sur le boîtier ainsi que l'assemblage du boîtier sur la carte sont supposées connues et ne seront pas décrites.The methods of mounting the balls on the PBGA box, mounting the chip on the box, connecting the chip on the box as well as assembling the box on the card are assumed to be known and will not be described.
La figure 1 illustre la face inférieure d'un boîtier PBGA.Figure 1 illustrates the underside of a PBGA package.
La figure 2 illustre le boîtier de la figure 1 en coupe partielle suivant l'axe de coupe AA de la figure 1.FIG. 2 illustrates the casing of FIG. 1 in partial section along the cutting axis AA of FIG. 1.
De façon classique, un boîtier PBGA "cavity down" est constitué d'un support rigide 1 de forme générale parallélépipèdique en cuivre, comportant une cavitéConventionally, a "cavity down" PBGA box is made up of a rigid support 1 of generally parallelepipedal shape made of copper, comprising a cavity
2, généralement centrale, renfermant une puce 3 qui est fixée sur le fond 4 de la cavité 2 par l'intermédiaire d'une colle 5 thermiquement conductrice. Le support 1 supporte en outre un substrat diélectrique 6, généralement flexible, disposé à la périphérie de la cavité 2 et donc de la puce 3. Le substrat 6 supporte, sur une de ses faces, des pistes conductrices 7i disposées suivant un design déterminé comportant les zones de connexion des fils de bonding et des billes.2, generally central, containing a chip 3 which is fixed to the bottom 4 of the cavity 2 by means of a thermally conductive adhesive 5. The support 1 also supports a generally flexible dielectric substrate 6, disposed at the periphery of the cavity 2 and therefore of the chip 3. The substrate 6 supports, on one of its faces, conductive tracks 7i arranged according to a determined design comprising the connection zones of the bonding wires and of the balls.
Il supporte sur son autre face, un plan conducteur 8 qui est fixé sur le support 1 par exemple en utilisant la même colle 9 que celle fixant la puce 3 sur le fond 4 de la cavité 2.It supports on its other face, a conducting plane 8 which is fixed on the support 1 for example by using the same glue 9 as that fixing the chip 3 on the bottom 4 of the cavity 2.
La face active 10 de la puce 3, opposée au fond 4 de la cavité 2, est reliée électriquement aux pistes 7i par l'intermédiaires de connexions 11 i, ici des fils de connexion appelés également fils de "bonding". Les pistes conductrices 7i s'étendent à partir de la cavité 2 et radialement par rapport à la cavité 2 et se terminent respectivement par des plots conducteursThe active face 10 of the chip 3, opposite the bottom 4 of the cavity 2, is electrically connected to the tracks 7i by connection intermediaries 11 i, here connection wires also called "bonding" wires. The conductive tracks 7i extend from the cavity 2 and radially with respect to the cavity 2 and terminate respectively in conductive pads
12i disposés suivant un design déterminé, à la périphérie du boîtier, et tels qu'illustré à la figure 1.12i arranged in a determined design, at the periphery of the housing, and as illustrated in FIG. 1.
Les plots 12i sont destinés à recevoir respectivement des billes de soudure 13i telles que représentées aux figures 2 et 3.The studs 12i are intended to respectively receive solder balls 13i as shown in FIGS. 2 and 3.
Ses billes 13i, formant un réseau de billes, assurent la liaison mécanique et électrique entre la puce 3 et la carte une fois l'assemblage du boîtier sur la carte effectué.Its balls 13i, forming a network of balls, provide the mechanical and electrical connection between the chip 3 and the card once the housing has been assembled on the card.
Le câblage des fils 11 i et des billes 13i sur le boîtier est réalisé sur un même niveau Ne correspondant au plan des pistes 7i et des plots conducteurs 12i.The wiring of the wires 11 i and of the balls 13i on the housing is carried out on the same level Ne corresponding to the plane of the tracks 7i and of the conductive pads 12i.
La figure 3 illustre schématiquement, également suivant une coupe partielle transversale suivant l'axe de coupe AA de la figure 1 , un boîtier PBGA selon l'invention.FIG. 3 schematically illustrates, also in a partial transverse section along the cutting axis AA of FIG. 1, a PBGA box according to the invention.
Il comporte la même structure de base du boîtier illustré à la figure 2 et comporte en outre, à un niveau inférieur au niveau Ne de connexion des fils 11 i et des billes 13i sur le boîtier, une couche supplémentaire 14 contenant les billes 13i et qui s'étend entre les billes 13i tout en restant en retrait par rapport à la cavité 2 de manière à ne pas recouvrir la zone de connexion Zc des fils 11 i sur le boîtier. La couche 14 a une rigidité mécanique déterminée et est électriquement neutre. Cette couche 14 définit une grille comportant une pluralité d'ouvertures 15i dans lesquelles les billes 13i sont respectivement logées. Les ouvertures sont choisies suffisamment larges pour contenir les billes 13i avec un léger jeu de l'ordre de 0,2 mm. La grille 14 peut être rapportée par collage sous forme de résine ou sous forme de préforme, au moment de l'assemblage du boîtier sur la carte, ou être intégré à la structure du boîtier lors de sa fabrication.It comprises the same basic structure of the housing illustrated in FIG. 2 and also comprises, at a level below the level Ne of connection of the wires 11 i and of the balls 13i on the housing, an additional layer 14 containing the balls 13i and which extends between the balls 13i while remaining set back with respect to the cavity 2 so as not to cover the connection zone Zc of the wires 11 i on the housing. The layer 14 has a determined mechanical rigidity and is electrically neutral. This layer 14 defines a grid comprising a plurality of openings 15i in which the balls 13i are respectively housed. The openings are chosen to be wide enough to contain the balls 13i with a slight play of the order of 0.2 mm. The grid 14 can be attached by gluing in the form of resin or in the form of a preform, when the box is assembled on the card, or can be integrated into the structure of the box during its manufacture.
Selon le mode de réalisation décrit, la grille 14 est rapportée par collage. Une couche de colle 16 est appliquée de telle manière qu'elle ne recouvre pas les plots de connexion 12i et qu'elle ne puisse pas pénétrer à l'intérieur des ouvertures 15i de la grille 14 en utilisant, par exemple, un écran de sérigraphie ou une préforme.According to the embodiment described, the grid 14 is attached by gluing. A layer of adhesive 16 is applied in such a way that it does not cover the connection pads 12i and that it cannot penetrate inside the openings 15i of the grid 14 using, for example, a screen printing screen. or a preform.
Un matériau d'enrobage 17 comble l'espace laissé libre par la grille 14 et qui forme une deuxième cavité 18 plus large que la première cavité 2 contenant la puce 3.A coating material 17 fills the space left free by the grid 14 and which forms a second cavity 18 wider than the first cavity 2 containing the chip 3.
On comprend alors que la grille 14 joue le double rôle de grille de positionnement des billes 13i et d'obstacle pour le matériau d'enrobage 17 recouvrant la face active 10 de la puce 3 et ses fils de connexions 11 i. Le pourtour intérieur de la grille 14, collé sur le niveau de connexion Ne, formant un mur d'arrêt entre les billes 13i et les fils 1 1 i.It will then be understood that the grid 14 plays the dual role of a grid for positioning the balls 13i and of an obstacle for the coating material 17 covering the active face 10 of the chip 3 and its connection wires 11 i. The inner periphery of the grid 14, glued to the connection level Ne, forming a barrier wall between the balls 13i and the wires 1 1 i.
De plus, en fonction d'une épaisseur déterminée, cette couche supplémentaire ou grille 14 joue également le rôle d'entretoise dans le cas de boîtiers à poids par bille très élevé, typiquement au delà de 50 mg par bille. C'est notamment le cas des boîtiers ayant un dissipateur thermique intégré couvrant toute la surface du boîtier.In addition, as a function of a determined thickness, this additional layer or grid 14 also plays the role of spacer in the case of packages with very high weight per ball, typically above 50 mg per ball. This is particularly the case for housings having an integrated heat sink covering the entire surface of the housing.
Ce rôle d'entretoise permet de garantir un éloignement prédéfini du boîtier par rapport à la carte et évite un affaissement non contrôlé des billes. Enfin, cette couche permet de garantir une isolation électrique entre les billes lorsque le boîtier est monté sur la carte. Elle a pour avantage supplémentaire de pouvoir augmenter le volume de soudure en prenant des billes de diamètre plus élevé, par exemple de 0,96 mm au lieu de 0,76 mm pour un même pas entre billes de 1 ,27 mm. La fiabilité sous cycle thermique du boîtier assemblé est alors augmentée. Cette caractéristique est particulièrement importante dans des applications à forte contrainte de température, notamment dans les applications automobiles. La hauteur des joints soudés sur carte, "ring" en terminologie anglo-saxonne, peut être plus grande, typiquement de ON mm au lieu de 0,5 mm. Un joint soudé correspond typiquement à un dépôt cuivre sur lequel sont soudés les composants à la périphérie du boîtier.This role of spacer makes it possible to guarantee a predefined distance of the housing from the card and avoids uncontrolled collapse of the balls. Finally, this layer ensures electrical insulation between the balls when the housing is mounted on the card. It has the additional advantage of being able to increase the volume of solder by taking balls of larger diameter, for example 0.96 mm instead of 0.76 mm for the same pitch between balls of 1.27 mm. The reliability under thermal cycle of the assembled housing is then increased. This characteristic is particularly important in applications with high temperature constraints, in particular in automotive applications. The height of the welded joints on a card, "ring" in English terminology, can be greater, typically ON mm instead of 0.5 mm. A welded joint typically corresponds to a copper deposit on which the components are welded to the periphery of the housing.
Ceci a pour conséquence une relaxation des contraintes de câblage et l'emploi de fils en aluminium selon une technique connue sous la terminologie anglo- saxonne '"wedge", est alors envisageable. Le boîtier peut alors avoir une finition "Or electroless" moins chère qu'une finition "Or électrolytique" et sans présence d'antennes (nourrices de metallisation).This results in a relaxation of the wiring constraints and the use of aluminum wires according to a technique known under the terminology "wedge" is then possible. The box can then have a cheaper "Gold electroless" finish than a "Gold electrolytic" finish and without the presence of antennas (metallization feeders).
A titre d'exemple non limitatif, on donne ci-après les dimensions d'un boîtier selon l'invention ainsi que les matériaux utilisés pour chacune des couches constitutives du boîtier et leurs épaisseurs respectives. Cet exemple, donné à titre indicatif, ne tient pas compte des tolérances dimensionnelles.By way of nonlimiting example, the dimensions of a case according to the invention are given below, as well as the materials used for each of the constituent layers of the case and their respective thicknesses. This example, given for information only, does not take dimensional tolerances into account.
Le boîtier définit un parallélépipède de 35 mm de côté.The housing defines a parallelepiped with a side of 35 mm.
La cavité centrale 2 définit un carrée de 15 mm de côté et sa profondeur est de 40 mm. Elle est destinée à recevoir une puce 3 de forme générale parallelepipedique de 13 mm de côté et de 0,40 mm d'épaisseur. La puce 5 est fixée sur le fond 4 de la cavité 2 par l'intermédiaire d'une colle 5 de 0,10 mm d'épaisseur qui est une résine époxy chargée à l'argent. Les côtés de la cavité 2 sont respectivement parallèles aux cotés du boîtier. Le boîtier est constitué d'un support 1 de 0,7 mm d'épaisseur hors tout et l'épaisseur du fond du support 1 , correspondant au fond 4 de la cavité 2, est égale à 0,3 mm. Le support 1 est en cuivre.The central cavity 2 defines a square with a side of 15 mm and its depth is 40 mm. It is intended to receive a chip 3 of generally parallelepiped shape with a side of 13 mm and a thickness of 0.40 mm. The chip 5 is fixed to the bottom 4 of the cavity 2 by means of an adhesive 5 of 0.10 mm thick which is an epoxy resin loaded with silver. The sides of the cavity 2 are respectively parallel to the sides of the housing. The housing consists of a support 1 0.7 mm thick overall and the thickness of the bottom of the support 1, corresponding to the bottom 4 of the cavity 2, is equal to 0.3 mm. The support 1 is made of copper.
Le support 1 reçoit sur sa face inférieure, un empilement de plusieurs couches qui sont décrites successivement dans l'ordre croissant de l'épaisseur du boîtier. La première couche 9 est une couche de colle époxy de 0,10 mm d'épaisseur.The support 1 receives on its underside, a stack of several layers which are described successively in increasing order of the thickness of the housing. The first layer 9 is a layer of epoxy adhesive 0.10 mm thick.
Elle sert à fixer le substrat flexible 6 sur le support 1.It is used to fix the flexible substrate 6 on the support 1.
La deuxième couche 8 correspond au plan conducteur qui est en cuivre d'épaisseur de 17 μm.The second layer 8 corresponds to the conductive plane which is made of copper with a thickness of 17 μm.
La troisième couche 6 correspond au substrat flexible proprement dit qui est en polyimide d'épaisseur de 50 μm.The third layer 6 corresponds to the flexible substrate proper which is made of polyimide with a thickness of 50 μm.
La quatrième couche 7i correspond aux pistes conductrices qui sont en cuivre d'épaisseur de 17 μm.The fourth layer 7i corresponds to the conductive tracks which are made of copper with a thickness of 17 μm.
C'est sur cette quatrième couche 7i que sont fixés les billes 13i et les fils de connexion 11 i. La cinquième couche 16 est une couche de colle de 0,10 mm d'épaisseur destinée à fixer la sixième couche 14 dite "couche supplémentaire" sur la quatrième couche 7i de l'empilement, c'est-à-dire sur le niveau de connexionIt is on this fourth layer 7i that the balls 13i and the connection wires 11 i are fixed. The fifth layer 16 is a layer of glue 0.10 mm thick intended to fix the sixth layer 14 called "additional layer" on the fourth layer 7i of the stack, that is to say on the level of connection
Ne.Born.
La couche supplémentaire 14 est en résine époxy d'épaisseur de 0,5 mm. Elle définit une grille au pas de 1 ,27 mm comportant une pluralité d'ouvertures 15i destinées à contenir la pluralité de billes 13i qui dans l'exemple choisi ont un diamètre de 0,96 mm. Les ouvertures 15i ont une forme générale cylindrique de section circulaire.The additional layer 14 is made of 0.5 mm thick epoxy resin. It defines a grid with a pitch of 1.27 mm comprising a plurality of openings 15i intended to contain the plurality of balls 13i which in the example chosen have a diameter of 0.96 mm. The openings 15i have a generally cylindrical shape of circular section.
Le diamètre des ouvertures 15i de la grille 14 est sensiblement supérieure au diamètre des billes 13i et est de l'ordre de 1 ,05 mm.The diameter of the openings 15i of the grid 14 is substantially greater than the diameter of the balls 13i and is of the order of 1.05 mm.
Le diamètre des billes et la hauteur maximale acceptable après refusion définissent l'épaisseur maximale de la grille 14 jouant son rôle d'entretoise et de positionnement des billes 13i sur le boîtier.The diameter of the balls and the maximum acceptable height after reflow define the maximum thickness of the grid 14 playing its role of spacer and positioning of the balls 13i on the housing.
Un matériau d'enrobage 17, par exemple une colle époxy , recouvre la face active 10 de la puce 3 ainsi que les fils de connexion 11 i. Il est stoppé dans son expansion par les cinquième et sixième couches de l'empilement, respectivement 16 et 14, et est enfermé dans une deuxième cavité 18 plus large que la première et définie par le pourtour intérieur de la grille 14 collée sur le substrat flexible 6. A coating material 17, for example an epoxy adhesive, covers the active face 10 of the chip 3 as well as the connection wires 11 i. It is stopped in its expansion by the fifth and sixth layers of the stack, respectively 16 and 14, and is enclosed in a second cavity 18 wider than the first and defined by the inner periphery of the grid 14 bonded to the flexible substrate 6.

Claims

REVENDICATIONS
1. Boîtier pour circuit intégré, du type "cavity down", comportant une cavité (2) dans laquelle est fixé le circuit intégré (3), la face active (10) du circuit intégré (3) étant connectée électriquement au boîtier, au moyen de fils de connexion (11 i), sur le niveau de connexion (Ne) d'un réseau de billes (13i) sur le boîtier assurant une liaison mécanique et électrique entre le circuit intégré (3) et une carte de circuit imprimé sur laquelle doit être assemblé le boîtier, caractérisé en ce qu'il comporte une grille (14), rigide et électriquement neutre, rapportée sur le niveau de connexion (Ne) du circuit intégré (3) et des billes (13i), et dont les ouvertures (13i) sont choisies suffisamment larges pour contenir les billes avec un jeu déterminé.1. Box for integrated circuit, of the "cavity down" type, comprising a cavity (2) in which the integrated circuit (3) is fixed, the active face (10) of the integrated circuit (3) being electrically connected to the box, means of connection wires (11 i), on the connection level (Ne) of a network of balls (13i) on the housing ensuring a mechanical and electrical connection between the integrated circuit (3) and a printed circuit board on which must be assembled the housing, characterized in that it comprises a grid (14), rigid and electrically neutral, attached to the connection level (Ne) of the integrated circuit (3) and balls (13i), and the openings (13i) are chosen wide enough to contain the balls with a determined clearance.
2. Boîtier selon la revendication 1 , caractérisé en ce que la grille (14) définit une entretoise dont l'épaisseur est déterminée en fonction du diamètre des billes (13i) et de leur hauteur maximale acceptable après assemblage du boîtier sur la carte.2. Housing according to claim 1, characterized in that the grid (14) defines a spacer whose thickness is determined according to the diameter of the balls (13i) and their maximum acceptable height after assembly of the housing on the card.
3. Boîtier selon l'une quelconque des revendications 1 et 2, caractérisé en ce que la grille (14) définit une grille de positionnement pour les billes (13i) qu'elle contient.3. Housing according to any one of claims 1 and 2, characterized in that the grid (14) defines a positioning grid for the balls (13i) it contains.
4. Boîtier selon la revendication 3, caractérisé en ce que la grille (14) définit une deuxième cavité (18) plus large que la première cavité (2) dans laquelle est fixée le circuit intégré (3), et dont l'ouverture est délimitée par la zone de connexion (Zc) du circuit intégré (3) sur le boîtier.4. Housing according to claim 3, characterized in that the grid (14) defines a second cavity (18) wider than the first cavity (2) in which the integrated circuit (3) is fixed, and the opening of which is delimited by the connection zone (Zc) of the integrated circuit (3) on the box.
5. Boîtier selon la revendication 4, caractérisé en ce que la deuxième cavité (18) contient un matériau (17) d'enrobage recouvrant complètement la face active (10) du circuit intégré (3) et ses connexions (11 i) au boîtier. 5. Housing according to claim 4, characterized in that the second cavity (18) contains a coating material (17) completely covering the active face (10) of the integrated circuit (3) and its connections (11 i) to the housing .
6. Boîtier selon la revendication 5, caractérisé en ce que la grille (14) définit un obstacle ente la zone de connexion (Zc) du circuit intégré (3) sur le boîtier et le réseau de billes (13i).6. Housing according to claim 5, characterized in that the grid (14) defines an obstacle between the connection area (Zc) of the integrated circuit (3) on the housing and the array of balls (13i).
7. Boîtier selon l'une quelconque des revendications 1 à 6, caractérisé en ce que la grille (14) est rapportée par collage au moment de l'assemblage du boîtier.7. Housing according to any one of claims 1 to 6, characterized in that the grid (14) is attached by gluing at the time of assembly of the housing.
8. Boîtier selon l'une quelconque des revendications 1 à 6, caractérisé en ce que la grille (14) est intégrée à la structure du boîtier lors de sa fabrication. 8. Housing according to any one of claims 1 to 6, characterized in that the grid (14) is integrated into the structure of the housing during its manufacture.
PCT/FR2000/001201 1999-05-10 2000-05-04 Pbga package with integrated ball grid WO2000068991A1 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP00925385A EP1099253A1 (en) 1999-05-10 2000-05-04 Pbga package with integrated ball grid
JP2000617492A JP3520049B2 (en) 1999-05-10 2000-05-04 PBGA package incorporating ball grid
US09/743,061 US6384471B1 (en) 1999-05-10 2000-05-04 Pbga package with integrated ball grid

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR99/05930 1999-05-10
FR9905930A FR2793606B1 (en) 1999-05-10 1999-05-10 PBGA HOUSING WITH INTEGRATED BILLING GRILLE

Publications (1)

Publication Number Publication Date
WO2000068991A1 true WO2000068991A1 (en) 2000-11-16

Family

ID=9545407

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/FR2000/001201 WO2000068991A1 (en) 1999-05-10 2000-05-04 Pbga package with integrated ball grid

Country Status (4)

Country Link
EP (1) EP1099253A1 (en)
JP (1) JP3520049B2 (en)
FR (1) FR2793606B1 (en)
WO (1) WO2000068991A1 (en)

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888293A (en) * 1994-09-19 1996-04-02 Mitsui High Tec Inc Semiconductor mounting device and mounting method for semiconductor device using the same
JPH0897314A (en) * 1994-09-28 1996-04-12 Dainippon Printing Co Ltd Surface mounting type semiconductor device
JPH08250835A (en) * 1995-03-10 1996-09-27 Nec Corp Method for mounting lsi package having metallic bump
JPH10112472A (en) * 1996-10-07 1998-04-28 Toshiba Corp Semiconductor device and its manufacture
JPH10256424A (en) * 1997-03-12 1998-09-25 Toshiba Corp Package for semiconductor element
US5883438A (en) * 1995-09-22 1999-03-16 Lg Semicon Co., Ltd. Interconnection structure for attaching a semiconductor to substrate

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5397921A (en) 1993-09-03 1995-03-14 Advanced Semiconductor Assembly Technology Tab grid array

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0888293A (en) * 1994-09-19 1996-04-02 Mitsui High Tec Inc Semiconductor mounting device and mounting method for semiconductor device using the same
JPH0897314A (en) * 1994-09-28 1996-04-12 Dainippon Printing Co Ltd Surface mounting type semiconductor device
JPH08250835A (en) * 1995-03-10 1996-09-27 Nec Corp Method for mounting lsi package having metallic bump
US5883438A (en) * 1995-09-22 1999-03-16 Lg Semicon Co., Ltd. Interconnection structure for attaching a semiconductor to substrate
JPH10112472A (en) * 1996-10-07 1998-04-28 Toshiba Corp Semiconductor device and its manufacture
JPH10256424A (en) * 1997-03-12 1998-09-25 Toshiba Corp Package for semiconductor element

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 08 30 August 1996 (1996-08-30) *
PATENT ABSTRACTS OF JAPAN vol. 1997, no. 01 31 January 1997 (1997-01-31) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 09 31 July 1998 (1998-07-31) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 14 31 December 1998 (1998-12-31) *

Also Published As

Publication number Publication date
JP2002544670A (en) 2002-12-24
EP1099253A1 (en) 2001-05-16
FR2793606A1 (en) 2000-11-17
FR2793606B1 (en) 2003-06-13
JP3520049B2 (en) 2004-04-19

Similar Documents

Publication Publication Date Title
EP0321340B1 (en) Electronic-component support, especially for a memory card, and product so obtained
US7374969B2 (en) Semiconductor package with conductive molding compound and manufacturing method thereof
FR2621173A1 (en) HIGH DENSITY INTEGRATED CIRCUIT BOX
FR2700416A1 (en) Semiconductor device having a semiconductor element on a mounting element.
EP0424262B1 (en) Portable electronics with connectable components
EP0682365A1 (en) Three-dimensional interconnection of electronic component housings using printed circuits
EP3089211B1 (en) Method for packaging an electronic circuit
FR2747509A1 (en) Semiconductor integrated circuit mounting assembly
FR2651373A1 (en) SEMICONDUCTOR DEVICE WITH RESIN HOUSING.
FR2720190A1 (en) Method for connecting the output pads of an integrated circuit chip, and multi-chip module thus obtained.
EP0593330A1 (en) 3D-interconnection method for electronic component housings and resulting 3D component
FR2645681A1 (en) Vertical interconnection device for integrated-circuit chips and its method of manufacture
JPH11191603A (en) Semiconductor integrated circuit and its manufacture
EP1864326B1 (en) Low- thickness electronic module comprising stacked electronic packages provided with connection balls
WO2000068991A1 (en) Pbga package with integrated ball grid
FR2629667A1 (en) Printed-circuit device
FR2520932A1 (en) INTEGRATED CIRCUIT BOX MOUNTING BRACKET, WITH DISTRIBUTED OUTPUT CONNECTIONS ON THE PERIMETER OF THE HOUSING
FR2758908A1 (en) Low cost surface-mountable microwave package
FR2758935A1 (en) Multiple layer casing for high frequency microelectronic circuit
EP0484853A1 (en) A method for protecting the electronic components of a circuit against the radiations and device using the same
US6384471B1 (en) Pbga package with integrated ball grid
WO2018002368A1 (en) Electronic device comprising an integrated bank of passive components
FR2877537A1 (en) Microelectronic box for e.g. radar, has upper and lower stages with printed circuits that along with intermediate structure are made of organic material, and channels interconnected with circuits` connection points to interconnect stages
EP2772936B1 (en) Method of wire bonding parallel bond wires aswell as a reshaping process of the same, and the related apparatus
FR2996055A1 (en) ELECTRIC CIRCUIT AND METHOD FOR PRODUCING THE SAME

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

WWE Wipo information: entry into national phase

Ref document number: 2000925385

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 09743061

Country of ref document: US

ENP Entry into the national phase

Ref country code: JP

Ref document number: 2000 617492

Kind code of ref document: A

Format of ref document f/p: F

121 Ep: the epo has been informed by wipo that ep was designated in this application
WWP Wipo information: published in national office

Ref document number: 2000925385

Country of ref document: EP