WO2000068781B1 - Switching method in a multi-threaded processor - Google Patents

Switching method in a multi-threaded processor

Info

Publication number
WO2000068781B1
WO2000068781B1 PCT/US2000/013094 US0013094W WO0068781B1 WO 2000068781 B1 WO2000068781 B1 WO 2000068781B1 US 0013094 W US0013094 W US 0013094W WO 0068781 B1 WO0068781 B1 WO 0068781B1
Authority
WO
WIPO (PCT)
Prior art keywords
thread
pipeline
threads
executing
execution threads
Prior art date
Application number
PCT/US2000/013094
Other languages
French (fr)
Other versions
WO2000068781A2 (en
WO2000068781A3 (en
WO2000068781A9 (en
Inventor
William N Joy
Marc Tremblay
Gary Lauterbach
Joseph I Chamdani
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to DE60002200T priority Critical patent/DE60002200T2/en
Priority to EP00932370A priority patent/EP1185929B1/en
Publication of WO2000068781A2 publication Critical patent/WO2000068781A2/en
Publication of WO2000068781A3 publication Critical patent/WO2000068781A3/en
Publication of WO2000068781B1 publication Critical patent/WO2000068781B1/en
Publication of WO2000068781A9 publication Critical patent/WO2000068781A9/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3842—Speculative instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling

Abstract

A processor (300) includes logic for attaining a very fast exception handling functionality while executing non-threaded programs by invoking a multithreaded-type functionality in response to an exception condition. The procesor, while operating in multithreaded conditions or while executing non-threaded programs, progresses through multiple machine states during execution. The very fast exception handling logic includes connection of an exception signal line to thread select logic, causing an exception signal to evoke a switch in thread and machine state. The switch in thread and machine state causes the processor to enter and to exit the exception handler immediately, without waiting to drain the pipeline or queues and without the inherent timing penalty of the operating system's software saving and restoring of registers.

Claims

AMENDED CLAIMS
[received by the International Bureau on 9 March 2001 (09 03 01), original claim 1 amended, remaining claims unchanged (4 pages)]
1 1 A method of operating a processor composing
2 selecting a thread from among a plurality of execution threads (122, 124, 126, 128),
3 other threads being nonselected threads,
4 activating a machine state (310, 312) for the selected execution thread,
5 executing the selected execution thread in a shared pipeline (314), the shared pipeline
6 including a plurality of pulse-based high-speed flip-flops (400) that generate
7 multiple thread paths without using multiplexers to select from among the
8 plurality of execution threads; and
9 freezing nonselected threads in the shared pipeline without executing
1 2 A method according to Claim 1 further comprising
2 allocating a load store unit (316, 318) to individual threads of the plurality of
3 execution threads; and
-4 accessing the allocated load/store units according to the executing thread.
1 3. A method according to either Claim 1 or Claim 2 further comprising:
-2 shaπng a data storage unit (320) among the plurality of execution threads.
1 4. A method according to any of Claims 1 -3 further comprising
2 shaπng an instruction control logic (330) among the plurality of execution threads.
1 5. A method according to any of Claims 1-4 further comprising
2 shaπng an external cache control unit (322) among the plurality of execution threads.
1 6. A method of operating a processor according to any of Claims 1-5 further
2 compπsing:
3 running one or more program applications concurrently,
4 executing a plurality of execution threads m a multiple-thread pipeline including a
5 plurality of multiple-bit flip-flops that hold the plurality of execution threads,
6 the execution threads for executing issued instructions for the program
7 applications,
8 switching the execution threads m the multiple-thread pipeline including:
-51 - freezing an active state in the pipeline; activating a previously idle thread in the pipeline while holding the state of the newly frozen thread m the pipeline; and subsequently resuming execution of the frozen thread at the precise state of the frozen thread immediately pπor to the thread switch
7. A method of operating a processor according to any of Claims 1-5 further compπsmg- running one or more program applications concurrently, executing a plurality of execution threads m a multiple-thread pipeline including a plurality of multiple-bit flip-flops that hold the plurality of execution threads, the execution threads for executing issued instructions for the program applications, the executing operation including holding a plurality of threads in the multiple-thread pipeline simultaneously including an active thread and one or more inactive threads; receiving notification of a stall condition; m response to receipt of the stall condition, stalling the active thread immediately including immediately deactivating a currently active thread and activating a currently inactive thread while the state of the threads in the multiple-thread pipeline remains the same.
8. A method of operating a processor according to any of Claims 1-5 further compπsmg. running a non-threaded program application, executing the non-threaded program m a multiple-thread pipeline including a plurality of multiple-bit flip-flops that are capable of holding a plurality of execution threads; switching context in a fast context switching operation including executing a first context in a first thread pathway in the multiple-thread pipeline; receiving an exception condition signal; in response to receipt of the exception condition signal, stalling the first context immediately including immediately deactivating the first context and activating an exception handler context while the state of the contexts in the multiple-thread pipeline remains the same.
-52-
9. A method according to Claim 8 wherein: the exception handler context is activated without operating system penalty.
10. A method according to Claim 8 wherein: the exception handler context is activated in hardware without mcurπng operating system speed penalty of software save/restore operations.
11. A method according to any of Claims 1-10 wherein. the multiple-thread pipeline includes a plurality of pulse-based high-speed flip-flops (400), the pulse-based high-speed flip-flops having a latch structure coupled to a plurality of select-bus lines, the select-bus lines selecting an active thread from among the plurality of execution threads
12. A method according to any of Claims 1-1 1 wherein executing an execution thread in a multiple-thread pipeline includes. latching data in pulse-based high-speed flip-flops; and selecting an active thread from among the plurality of execution threads using select- bus lines.
13. A method according to any of Claims 1-12 further comprising- detecting a cache miss; generating a cache miss stall signal in response to the cache miss stall, and freezing an active state m the pipeline m response to the cache miss stall signal.
14. A method according to any of Claims 1-13 further comprising. issuing instructions for the program applications m-order.
15. A method according to any of Claims 1-14 further compπsmg issuing instructions for the program applications m-order; and managing a machine state of the individual execution threads separately and independently.
16. A method according to any of Claims 1-15 further compπsmg: loading data from a storage and stoπng data to a storage via a plurality of load/store units that are individually allocated to individual threads m the multrple- thread pipeline.
17. A method according to any of Claims 1-16 further comprising: concurrently executing a plurality of execution threads in a plurality of multiple- thread pipelines so that the processor executes the one or more program applications with vertical threading and horizontal threading.
-54-
PCT/US2000/013094 1999-05-11 2000-05-10 Switching method in a multi-threaded processor WO2000068781A2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
DE60002200T DE60002200T2 (en) 1999-05-11 2000-05-10 SWITCHING METHOD IN A MULTITHREAD PROCESSOR
EP00932370A EP1185929B1 (en) 1999-05-11 2000-05-10 Switching method in a multi-threaded processor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/309,735 US6507862B1 (en) 1999-05-11 1999-05-11 Switching method in a multi-threaded processor
US09/309,735 1999-05-11

Publications (4)

Publication Number Publication Date
WO2000068781A2 WO2000068781A2 (en) 2000-11-16
WO2000068781A3 WO2000068781A3 (en) 2001-07-19
WO2000068781B1 true WO2000068781B1 (en) 2002-04-18
WO2000068781A9 WO2000068781A9 (en) 2002-05-16

Family

ID=23199454

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/013094 WO2000068781A2 (en) 1999-05-11 2000-05-10 Switching method in a multi-threaded processor

Country Status (4)

Country Link
US (3) US6507862B1 (en)
EP (1) EP1185929B1 (en)
DE (1) DE60002200T2 (en)
WO (1) WO2000068781A2 (en)

Families Citing this family (138)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6385715B1 (en) * 1996-11-13 2002-05-07 Intel Corporation Multi-threading for a processor utilizing a replay queue
US6826749B2 (en) * 1998-12-08 2004-11-30 Nazomi Communications, Inc. Java hardware accelerator using thread manager
US6507862B1 (en) * 1999-05-11 2003-01-14 Sun Microsystems, Inc. Switching method in a multi-threaded processor
US6542991B1 (en) 1999-05-11 2003-04-01 Sun Microsystems, Inc. Multiple-thread processor with single-thread interface shared among threads
US6668317B1 (en) * 1999-08-31 2003-12-23 Intel Corporation Microengine for parallel processor architecture
US6983350B1 (en) * 1999-08-31 2006-01-03 Intel Corporation SDRAM controller for parallel processor architecture
US6532509B1 (en) 1999-12-22 2003-03-11 Intel Corporation Arbitrating command requests in a parallel multi-threaded processing system
US6694380B1 (en) 1999-12-27 2004-02-17 Intel Corporation Mapping requests from a processing unit that uses memory-mapped input-output space
US6661794B1 (en) * 1999-12-29 2003-12-09 Intel Corporation Method and apparatus for gigabit packet assignment for multithreaded packet processing
US6931641B1 (en) * 2000-04-04 2005-08-16 International Business Machines Corporation Controller for multiple instruction thread processors
US7140018B1 (en) * 2000-06-20 2006-11-21 International Business Machines Corporation Method of using a distinct flow of computational control as a reusable abstract data object
US6420903B1 (en) * 2000-08-14 2002-07-16 Sun Microsystems, Inc. High speed multiple-bit flip-flop
US6920515B2 (en) * 2001-03-29 2005-07-19 Intel Corporation Early exception detection
US7320065B2 (en) 2001-04-26 2008-01-15 Eleven Engineering Incorporated Multithread embedded processor with input/output capability
US20020184290A1 (en) * 2001-05-31 2002-12-05 International Business Machines Corporation Run queue optimization with hardware multithreading for affinity
US7752423B2 (en) * 2001-06-28 2010-07-06 Intel Corporation Avoiding execution of instructions in a second processor by committing results obtained from speculative execution of the instructions in a first processor
WO2003044688A2 (en) * 2001-11-19 2003-05-30 Igor Anatolievich Abrosimov Latency tolerant processing equipment
US20030225816A1 (en) * 2002-06-03 2003-12-04 Morrow Michael W. Architecture to support multiple concurrent threads of execution on an arm-compatible processor
US7471688B2 (en) * 2002-06-18 2008-12-30 Intel Corporation Scheduling system for transmission of cells to ATM virtual circuits and DSL ports
US20040034759A1 (en) * 2002-08-16 2004-02-19 Lexra, Inc. Multi-threaded pipeline with context issue rules
US7577816B2 (en) * 2003-08-18 2009-08-18 Cray Inc. Remote translation mechanism for a multinode system
US20040103248A1 (en) * 2002-10-08 2004-05-27 Hass David T. Advanced telecommunications processor
US8478811B2 (en) * 2002-10-08 2013-07-02 Netlogic Microsystems, Inc. Advanced processor with credit based scheme for optimal packet flow in a multi-processor system on a chip
US20050044324A1 (en) * 2002-10-08 2005-02-24 Abbas Rashid Advanced processor with mechanism for maximizing resource usage in an in-order pipeline with multiple threads
US7334086B2 (en) * 2002-10-08 2008-02-19 Rmi Corporation Advanced processor with system on a chip interconnect technology
US7461213B2 (en) * 2002-10-08 2008-12-02 Rmi Corporation Advanced processor system using request, data, snoop, and response rings
US9088474B2 (en) * 2002-10-08 2015-07-21 Broadcom Corporation Advanced processor with interfacing messaging network to a CPU
US20050033889A1 (en) * 2002-10-08 2005-02-10 Hass David T. Advanced processor with interrupt delivery mechanism for multi-threaded multi-CPU system on a chip
US7961723B2 (en) * 2002-10-08 2011-06-14 Netlogic Microsystems, Inc. Advanced processor with mechanism for enforcing ordering between information sent on two independent networks
US8015567B2 (en) * 2002-10-08 2011-09-06 Netlogic Microsystems, Inc. Advanced processor with mechanism for packet distribution at high line rate
US8176298B2 (en) 2002-10-08 2012-05-08 Netlogic Microsystems, Inc. Multi-core multi-threaded processing systems with instruction reordering in an in-order pipeline
US7924828B2 (en) * 2002-10-08 2011-04-12 Netlogic Microsystems, Inc. Advanced processor with mechanism for fast packet queuing operations
US7984268B2 (en) * 2002-10-08 2011-07-19 Netlogic Microsystems, Inc. Advanced processor scheduling in a multithreaded system
US7346757B2 (en) * 2002-10-08 2008-03-18 Rmi Corporation Advanced processor translation lookaside buffer management in a multithreaded system
US7627721B2 (en) * 2002-10-08 2009-12-01 Rmi Corporation Advanced processor with cache coherency
US8037224B2 (en) 2002-10-08 2011-10-11 Netlogic Microsystems, Inc. Delegating network processor operations to star topology serial bus interfaces
US7433307B2 (en) * 2002-11-05 2008-10-07 Intel Corporation Flow control in a network environment
US7310710B1 (en) * 2003-03-11 2007-12-18 Marvell International Ltd. Register file with integrated routing to execution units for multi-threaded processors
US6981113B2 (en) * 2003-04-21 2005-12-27 Intel Corporation Storage registers for a processor pipeline
US7441245B2 (en) * 2003-08-14 2008-10-21 Intel Corporation Phasing for a multi-threaded network processor
US7735088B1 (en) * 2003-08-18 2010-06-08 Cray Inc. Scheduling synchronization of programs running as streams on multiple processors
US7743223B2 (en) 2003-08-18 2010-06-22 Cray Inc. Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system
US8307194B1 (en) 2003-08-18 2012-11-06 Cray Inc. Relaxed memory consistency model
US7614056B1 (en) 2003-09-12 2009-11-03 Sun Microsystems, Inc. Processor specific dispatching in a heterogeneous configuration
DE10353268B3 (en) * 2003-11-14 2005-07-28 Infineon Technologies Ag Parallel multi-thread processor with divided contexts has thread control unit that generates multiplexed control signals for switching standard processor body units to context memories to minimize multi-thread processor blocking probability
US7360064B1 (en) 2003-12-10 2008-04-15 Cisco Technology, Inc. Thread interleaving in a multithreaded embedded processor
US7441101B1 (en) 2003-12-10 2008-10-21 Cisco Technology, Inc. Thread-aware instruction fetching in a multithreaded embedded processor
US20050132363A1 (en) * 2003-12-16 2005-06-16 Vijay Tewari Method, apparatus and system for optimizing context switching between virtual machines
US7206922B1 (en) * 2003-12-30 2007-04-17 Cisco Systems, Inc. Instruction memory hierarchy for an embedded processor
US7263599B2 (en) * 2004-02-06 2007-08-28 Infineon Technologies Thread ID in a multithreaded processor
US9189230B2 (en) * 2004-03-31 2015-11-17 Intel Corporation Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution
US7523330B2 (en) * 2004-06-30 2009-04-21 Sun Microsystems, Inc. Thread-based clock enabling in a multi-threaded processor
US7747771B1 (en) 2004-06-30 2010-06-29 Oracle America, Inc. Register access protocol in a multihreaded multi-core processor
US7941642B1 (en) 2004-06-30 2011-05-10 Oracle America, Inc. Method for selecting between divide instructions associated with respective threads in a multi-threaded processor
US8095778B1 (en) 2004-06-30 2012-01-10 Open Computing Trust I & II Method and system for sharing functional units of a multithreaded processor
US7890734B2 (en) * 2004-06-30 2011-02-15 Open Computing Trust I & II Mechanism for selecting instructions for execution in a multithreaded processor
US7370243B1 (en) 2004-06-30 2008-05-06 Sun Microsystems, Inc. Precise error handling in a fine grain multithreaded multicore processor
US7178005B1 (en) 2004-06-30 2007-02-13 Sun Microsystems, Inc. Efficient implementation of timers in a multithreaded processor
US7478225B1 (en) 2004-06-30 2009-01-13 Sun Microsystems, Inc. Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor
US7343474B1 (en) 2004-06-30 2008-03-11 Sun Microsystems, Inc. Minimal address state in a fine grain multithreaded processor
US7702887B1 (en) 2004-06-30 2010-04-20 Sun Microsystems, Inc. Performance instrumentation in a fine grain multithreaded multicore processor
US7330988B2 (en) * 2004-06-30 2008-02-12 Sun Microsystems, Inc. Method and apparatus for power throttling in a multi-thread processor
US7533248B1 (en) 2004-06-30 2009-05-12 Sun Microsystems, Inc. Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor
US8225034B1 (en) 2004-06-30 2012-07-17 Oracle America, Inc. Hybrid instruction buffer
US7861063B1 (en) 2004-06-30 2010-12-28 Oracle America, Inc. Delay slot handling in a processor
US7437538B1 (en) 2004-06-30 2008-10-14 Sun Microsystems, Inc. Apparatus and method for reducing execution latency of floating point operations having special case operands
US7401206B2 (en) * 2004-06-30 2008-07-15 Sun Microsystems, Inc. Apparatus and method for fine-grained multithreading in a multipipelined processor core
US7185178B1 (en) 2004-06-30 2007-02-27 Sun Microsystems, Inc. Fetch speculation in a multithreaded processor
US7426630B1 (en) 2004-06-30 2008-09-16 Sun Microsystems, Inc. Arbitration of window swap operations
US7373489B1 (en) 2004-06-30 2008-05-13 Sun Microsystems, Inc. Apparatus and method for floating-point exception prediction and recovery
US7434000B1 (en) 2004-06-30 2008-10-07 Sun Microsystems, Inc. Handling duplicate cache misses in a multithreaded/multi-core processor
US7676655B2 (en) * 2004-06-30 2010-03-09 Sun Microsystems, Inc. Single bit control of threads in a multithreaded multicore processor
US7543132B1 (en) * 2004-06-30 2009-06-02 Sun Microsystems, Inc. Optimizing hardware TLB reload performance in a highly-threaded processor with multiple page sizes
US7774393B1 (en) 2004-06-30 2010-08-10 Oracle America, Inc. Apparatus and method for integer to floating-point format conversion
US7383403B1 (en) 2004-06-30 2008-06-03 Sun Microsystems, Inc. Concurrent bypass to instruction buffers in a fine grain multithreaded processor
US7353364B1 (en) 2004-06-30 2008-04-01 Sun Microsystems, Inc. Apparatus and method for sharing a functional unit execution resource among a plurality of functional units
US7216216B1 (en) 2004-06-30 2007-05-08 Sun Microsystems, Inc. Register window management using first pipeline to change current window and second pipeline to read operand from old window and write operand to new window
US7890735B2 (en) * 2004-08-30 2011-02-15 Texas Instruments Incorporated Multi-threading processors, integrated circuit devices, systems, and processes of operation and manufacture
US7634774B2 (en) * 2004-09-13 2009-12-15 Integrated Device Technology, Inc. System and method of scheduling computing threads
US7827555B2 (en) * 2004-09-13 2010-11-02 Integrated Device Technology, Inc. Scheduler for a multiprocessing computing system
US7765547B2 (en) * 2004-11-24 2010-07-27 Maxim Integrated Products, Inc. Hardware multithreading systems with state registers having thread profiling data
US8037250B1 (en) 2004-12-09 2011-10-11 Oracle America, Inc. Arbitrating cache misses in a multithreaded/multi-core processor
US9606821B2 (en) 2004-12-17 2017-03-28 Intel Corporation Virtual environment manager for creating and managing virtual machine environments
US7937709B2 (en) 2004-12-29 2011-05-03 Intel Corporation Synchronizing multiple threads efficiently
DE102005009083B4 (en) * 2005-02-28 2007-05-10 Infineon Technologies Ag Multithread processor with a synchronization unit and method of operating such
US7882505B2 (en) * 2005-03-25 2011-02-01 Oracle America, Inc. Method and apparatus for switching between per-thread and per-processor resource pools in multi-threaded programs
US20080134196A1 (en) * 2005-05-19 2008-06-05 Intel Corporation Apparatus, System, and Method of a Memory Arrangement for Speculative Multithreading
US7308565B2 (en) * 2005-06-15 2007-12-11 Seiko Epson Corporation Saving/restoring task state data from/to device controller host interface upon command from host processor to handle task interruptions
US7398371B2 (en) * 2005-06-23 2008-07-08 Qualcomm Incorporated Shared translation look-aside buffer and method
US20070014240A1 (en) * 2005-07-12 2007-01-18 Alok Kumar Using locks to coordinate processing of packets in a flow
US7823158B2 (en) * 2005-08-18 2010-10-26 International Business Machines Corporation Adaptive scheduling and management of work processing in a target context in resource contention
US20070101325A1 (en) * 2005-10-19 2007-05-03 Juraj Bystricky System and method for utilizing a remote memory to perform an interface save/restore procedure
US7502913B2 (en) * 2006-06-16 2009-03-10 Microsoft Corporation Switch prefetch in a multicore computer chip
US7454596B2 (en) * 2006-06-29 2008-11-18 Intel Corporation Method and apparatus for partitioned pipelined fetching of multiple execution threads
US7952184B2 (en) * 2006-08-31 2011-05-31 Micron Technology, Inc. Distributed semiconductor device methods, apparatus, and systems
US7754532B2 (en) * 2006-10-19 2010-07-13 Micron Technology, Inc. High density chip packages, methods of forming, and systems including same
US7493436B2 (en) * 2006-10-26 2009-02-17 International Business Machines Corporation Interrupt handling using simultaneous multi-threading
US20080229026A1 (en) 2007-03-15 2008-09-18 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for concurrently checking availability of data in extending memories
US7958323B1 (en) 2007-05-09 2011-06-07 Marvell Israel (M.I.S.L.) Ltd. Multithreading implementation for flops and register files
EP2159690A4 (en) * 2007-06-20 2010-09-01 Fujitsu Ltd Information processing unit and method for controlling register
US8250254B2 (en) * 2007-07-31 2012-08-21 Intel Corporation Offloading input/output (I/O) virtualization operations to a processor
US8261284B2 (en) * 2007-09-13 2012-09-04 Microsoft Corporation Fast context switching using virtual cpus
US8131941B2 (en) * 2007-09-21 2012-03-06 Mips Technologies, Inc. Support for multiple coherence domains
US20090089510A1 (en) * 2007-09-28 2009-04-02 Mips Technologies, Inc. Speculative read in a cache coherent microprocessor
US8392663B2 (en) * 2007-12-12 2013-03-05 Mips Technologies, Inc. Coherent instruction cache utilizing cache-op execution resources
US20090165004A1 (en) * 2007-12-21 2009-06-25 Jaideep Moses Resource-aware application scheduling
US9596324B2 (en) * 2008-02-08 2017-03-14 Broadcom Corporation System and method for parsing and allocating a plurality of packets to processor core threads
US20090248988A1 (en) * 2008-03-28 2009-10-01 Mips Technologies, Inc. Mechanism for maintaining consistency of data written by io devices
US7921195B2 (en) * 2008-06-09 2011-04-05 International Business Machines Corporation Optimizing service processing based on business information, operational intelligence, and self-learning
WO2010025074A1 (en) * 2008-08-28 2010-03-04 Sandbridge Technologies, Inc. Latch-based implementation of a register file for a multi-threaded processor
US20100115494A1 (en) * 2008-11-03 2010-05-06 Gorton Jr Richard C System for dynamic program profiling
US8024719B2 (en) 2008-11-03 2011-09-20 Advanced Micro Devices, Inc. Bounded hash table sorting in a dynamic program profiling system
US8478948B2 (en) * 2008-12-04 2013-07-02 Oracle America, Inc. Method and system for efficient tracing and profiling of memory accesses during program execution
US8386753B2 (en) * 2009-04-14 2013-02-26 International Business Machines Corporation Completion arbitration for more than two threads based on resource limitations
US8397088B1 (en) 2009-07-21 2013-03-12 The Research Foundation Of State University Of New York Apparatus and method for efficient estimation of the energy dissipation of processor based systems
US9658877B2 (en) 2010-08-23 2017-05-23 Empire Technology Development Llc Context switching using a context controller and on-chip context cache
US8869167B2 (en) 2011-05-19 2014-10-21 International Business Machines Corporation Application hibernation
US8966232B2 (en) * 2012-02-10 2015-02-24 Freescale Semiconductor, Inc. Data processing system operable in single and multi-thread modes and having multiple caches and method of operation
US9063906B2 (en) * 2012-09-27 2015-06-23 International Business Machines Corporation Thread sparing between cores in a multi-threaded processor
US9336057B2 (en) 2012-12-21 2016-05-10 Microsoft Technology Licensing, Llc Assigning jobs to heterogeneous processing modules
CN104657204B (en) * 2013-11-22 2018-05-04 华为技术有限公司 short task processing method, device and operating system
CN104899093B (en) * 2014-03-04 2018-06-05 华为技术有限公司 Data processing method, device and system
US9552223B2 (en) * 2014-09-30 2017-01-24 International Business Machines Corporation Post-return asynchronous code execution
US9996354B2 (en) * 2015-01-09 2018-06-12 International Business Machines Corporation Instruction stream tracing of multi-threaded processors
JP5996691B2 (en) * 2015-02-19 2016-09-21 株式会社シミュラティオ File transfer method and file transfer program
US10318356B2 (en) 2016-03-31 2019-06-11 International Business Machines Corporation Operation of a multi-slice processor implementing a hardware level transfer of an execution thread
US10706101B2 (en) 2016-04-14 2020-07-07 Advanced Micro Devices, Inc. Bucketized hash tables with remap entries
CN106844029B (en) * 2017-01-19 2020-06-30 努比亚技术有限公司 Self-management Android process freezing and unfreezing device and method
US10325341B2 (en) * 2017-04-21 2019-06-18 Intel Corporation Handling pipeline submissions across many compute units
US10229061B2 (en) 2017-07-14 2019-03-12 International Business Machines Corporation Method and arrangement for saving cache power
US10860618B2 (en) 2017-09-25 2020-12-08 Splunk Inc. Low-latency streaming analytics
US10997180B2 (en) 2018-01-31 2021-05-04 Splunk Inc. Dynamic query processor for streaming and batch queries
US10936585B1 (en) 2018-10-31 2021-03-02 Splunk Inc. Unified data processing across streaming and indexed data sets
US11238048B1 (en) 2019-07-16 2022-02-01 Splunk Inc. Guided creation interface for streaming data processing pipelines
US11614923B2 (en) 2020-04-30 2023-03-28 Splunk Inc. Dual textual/graphical programming interfaces for streaming data processing pipelines
US20220245156A1 (en) 2021-01-29 2022-08-04 Splunk Inc. Routing data between processing pipelines via a user defined data stream
US11687487B1 (en) * 2021-03-11 2023-06-27 Splunk Inc. Text files updates to an active processing pipeline
US11663219B1 (en) 2021-04-23 2023-05-30 Splunk Inc. Determining a set of parameter values for a processing pipeline

Family Cites Families (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3728692A (en) * 1971-08-31 1973-04-17 Ibm Instruction selection in a two-program counter instruction unit
JPH06105460B2 (en) 1988-06-07 1994-12-21 富士通株式会社 Multiprocessor processor switching device
GB2234613B (en) 1989-08-03 1993-07-07 Sun Microsystems Inc Method and apparatus for switching context of state elements in a microprocessor
US5255211A (en) 1990-02-22 1993-10-19 Redmond Productions, Inc. Methods and apparatus for generating and processing synthetic and absolute real time environments
US5452452A (en) 1990-06-11 1995-09-19 Cray Research, Inc. System having integrated dispatcher for self scheduling processors to execute multiple types of processes
US5357617A (en) * 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
JP2823767B2 (en) * 1992-02-03 1998-11-11 松下電器産業株式会社 Register file
US5404469A (en) * 1992-02-25 1995-04-04 Industrial Technology Research Institute Multi-threaded microprocessor architecture utilizing static interleaving
US5442756A (en) * 1992-07-31 1995-08-15 Intel Corporation Branch prediction and resolution apparatus for a superscalar computer processor
GB9223226D0 (en) 1992-11-05 1992-12-16 Algotronix Ltd Improved configurable cellular array (cal ii)
US5684993A (en) * 1993-01-04 1997-11-04 Microsoft Corporation Segregation of thread-specific information from shared task information
JP2748822B2 (en) * 1993-07-05 1998-05-13 日本電気株式会社 Information processing device
US5584023A (en) 1993-12-27 1996-12-10 Hsu; Mike S. C. Computer system including a transparent and secure file transform mechanism
JP3676411B2 (en) 1994-01-21 2005-07-27 サン・マイクロシステムズ・インコーポレイテッド Register file device and register file access method
US5742806A (en) 1994-01-31 1998-04-21 Sun Microsystems, Inc. Apparatus and method for decomposing database queries for database management system including multiprocessor digital data processing system
US5692193A (en) 1994-03-31 1997-11-25 Nec Research Institute, Inc. Software architecture for control of highly parallel computer systems
US5761285A (en) 1994-06-01 1998-06-02 Davox Corporation Universal telephony application client that is configurable from a profile for a telphone call campaign
JP2677202B2 (en) * 1994-08-12 1997-11-17 日本電気株式会社 Microprocessor
JP3569014B2 (en) * 1994-11-25 2004-09-22 富士通株式会社 Processor and processing method supporting multiple contexts
US5752027A (en) 1994-11-30 1998-05-12 Dun & Bradstreet Software Services, Inc. Apparatus and process for creating and accessing a database centric object
US5724565A (en) * 1995-02-03 1998-03-03 International Business Machines Corporation Method and system for processing first and second sets of instructions by first and second types of processing systems
EP0729097A1 (en) * 1995-02-07 1996-08-28 Sun Microsystems, Inc. Method and apparatus for run-time memory access checking and memory leak detection of a multi-threaded program
US5704054A (en) * 1995-05-09 1997-12-30 Yale University Counterflow pipeline processor architecture for semi-custom application specific IC's
JPH08320797A (en) * 1995-05-24 1996-12-03 Fuji Xerox Co Ltd Program control system
US5828880A (en) * 1995-07-06 1998-10-27 Sun Microsystems, Inc. Pipeline system and method for multiprocessor applications in which each of a plurality of threads execute all steps of a process characterized by normal and parallel steps on a respective datum
JP3661235B2 (en) * 1995-08-28 2005-06-15 株式会社日立製作所 Shared memory system, parallel processor and memory LSI
US5860138A (en) * 1995-10-02 1999-01-12 International Business Machines Corporation Processor with compiler-allocated, variable length intermediate storage
US5701432A (en) * 1995-10-13 1997-12-23 Sun Microsystems, Inc. Multi-threaded processing system having a cache that is commonly accessible to each thread
JP3348367B2 (en) * 1995-12-06 2002-11-20 富士通株式会社 Multiple access method and multiple access cache memory device
US5809415A (en) 1995-12-11 1998-09-15 Unwired Planet, Inc. Method and architecture for an interactive two-way data communication network
US5778247A (en) 1996-03-06 1998-07-07 Sun Microsystems, Inc. Multi-pipeline microprocessor with data precision mode indicator
US6148395A (en) * 1996-05-17 2000-11-14 Texas Instruments Incorporated Shared floating-point unit in a single chip multiprocessor
US5881277A (en) * 1996-06-13 1999-03-09 Texas Instruments Incorporated Pipelined microprocessor with branch misprediction cache circuits, systems and methods
US5933627A (en) * 1996-07-01 1999-08-03 Sun Microsystems Thread switch on blocked load or store using instruction thread field
JP3139392B2 (en) * 1996-10-11 2001-02-26 日本電気株式会社 Parallel processing system
US5887166A (en) * 1996-12-16 1999-03-23 International Business Machines Corporation Method and system for constructing a program including a navigation instruction
US5913925A (en) * 1996-12-16 1999-06-22 International Business Machines Corporation Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order
WO1998043193A2 (en) * 1997-03-21 1998-10-01 University Of Maryland Spawn-join instruction set architecture for providing explicit multithreading
US5875461A (en) * 1997-04-03 1999-02-23 Sun Microsystems, Inc. Method of synchronizing one of the objects with one of the threads at a time
US6058466A (en) * 1997-06-24 2000-05-02 Sun Microsystems, Inc. System for allocation of execution resources amongst multiple executing processes
US5890008A (en) * 1997-06-25 1999-03-30 Sun Microsystems, Inc. Method for dynamically reconfiguring a processor
US6076157A (en) 1997-10-23 2000-06-13 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6105051A (en) * 1997-10-23 2000-08-15 International Business Machines Corporation Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor
US6061710A (en) * 1997-10-29 2000-05-09 International Business Machines Corporation Multithreaded processor incorporating a thread latch register for interrupt service new pending threads
US6298431B1 (en) * 1997-12-31 2001-10-02 Intel Corporation Banked shadowed register file
US6205519B1 (en) * 1998-05-27 2001-03-20 Hewlett Packard Company Cache management for a multi-threaded processor
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US6507862B1 (en) * 1999-05-11 2003-01-14 Sun Microsystems, Inc. Switching method in a multi-threaded processor
US6420903B1 (en) * 2000-08-14 2002-07-16 Sun Microsystems, Inc. High speed multiple-bit flip-flop

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