WO2000068778A3 - Multiple-thread processor with single-thread interface shared among threads - Google Patents

Multiple-thread processor with single-thread interface shared among threads Download PDF

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Publication number
WO2000068778A3
WO2000068778A3 PCT/US2000/012800 US0012800W WO0068778A3 WO 2000068778 A3 WO2000068778 A3 WO 2000068778A3 US 0012800 W US0012800 W US 0012800W WO 0068778 A3 WO0068778 A3 WO 0068778A3
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WO
WIPO (PCT)
Prior art keywords
cache
processor
thread
tid
threads
Prior art date
Application number
PCT/US2000/012800
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French (fr)
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WO2000068778A2 (en
WO2000068778B1 (en
WO2000068778A9 (en
Inventor
William N Joy
Marc Tremblay
Gary Lauterbach
Joseph I Chamdani
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Sun Microsystems Inc
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Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of WO2000068778A2 publication Critical patent/WO2000068778A2/en
Publication of WO2000068778A3 publication Critical patent/WO2000068778A3/en
Publication of WO2000068778B1 publication Critical patent/WO2000068778B1/en
Publication of WO2000068778A9 publication Critical patent/WO2000068778A9/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30141—Implementation provisions of register files, e.g. ports
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file
    • G06F9/30123—Organisation of register space, e.g. banked or distributed register file according to context, e.g. thread buffers
    • G06F9/30127—Register windows
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system

Abstract

A processor includes logic (612) for tagging a thread identifier (TID) for usage with processor blocks that are not stalled. Pertinent non-stalling blocks include caches, translation look-aside buffers (TLB) (1258, 1220), a load buffer asynchronous interface, an external memory management unit (MMU) interface (320, 330), and others. A processor (300) includes a cache that is segregated into a plurality of N cache parts. Cache segregation avoids interference, 'pollution', or 'cross-talk' between threads. One technique for cache segregation utilizes logic for storing and communicating thread identification (TID) bits. The cache utilizes cache indexing logic. For example, the TID bits can be inserted at the most significant bits of the cache index.
PCT/US2000/012800 1999-05-11 2000-05-09 Multiple-thread processor with single-thread interface shared among threads WO2000068778A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/309,734 1999-05-11
US09/309,734 US6542991B1 (en) 1999-05-11 1999-05-11 Multiple-thread processor with single-thread interface shared among threads

Publications (4)

Publication Number Publication Date
WO2000068778A2 WO2000068778A2 (en) 2000-11-16
WO2000068778A3 true WO2000068778A3 (en) 2001-08-09
WO2000068778B1 WO2000068778B1 (en) 2001-10-04
WO2000068778A9 WO2000068778A9 (en) 2002-04-04

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2000/012800 WO2000068778A2 (en) 1999-05-11 2000-05-09 Multiple-thread processor with single-thread interface shared among threads

Country Status (2)

Country Link
US (4) US6542991B1 (en)
WO (1) WO2000068778A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
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US8032737B2 (en) 2006-08-14 2011-10-04 Marvell World Trade Ltd. Methods and apparatus for handling switching among threads within a multithread processor

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