WO2000064229A1 - Contact module, as for a smart card, and method for making same - Google Patents
Contact module, as for a smart card, and method for making same Download PDFInfo
- Publication number
- WO2000064229A1 WO2000064229A1 PCT/US2000/009144 US0009144W WO0064229A1 WO 2000064229 A1 WO2000064229 A1 WO 2000064229A1 US 0009144 W US0009144 W US 0009144W WO 0064229 A1 WO0064229 A1 WO 0064229A1
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- WO
- WIPO (PCT)
- Prior art keywords
- electrically
- adhesive
- metal
- contacts
- conductive vias
- Prior art date
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
- B32B37/14—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers
- B32B37/16—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with all layers existing as coherent layers before laminating
- B32B37/20—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by the properties of the layers with all layers existing as coherent layers before laminating involving the assembly of continuous webs only
- B32B37/203—One or more of the layers being plastic
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B3/00—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar form; Layered products having particular features of form
- B32B3/02—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar form; Layered products having particular features of form characterised by features of form at particular places, e.g. in edge regions
- B32B3/08—Layered products comprising a layer with external or internal discontinuities or unevennesses, or a layer of non-planar form; Layered products having particular features of form characterised by features of form at particular places, e.g. in edge regions characterised by added members at particular parts
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B33/00—Layered products characterised by particular properties or particular surface features, e.g. particular surface coatings; Layered products designed for particular purposes not covered by another single class
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
- B32B7/04—Interconnection of layers
- B32B7/12—Interconnection of layers using interposed adhesives or interposed materials with bonding properties
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07743—External electrical contacts
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07745—Mounting details of integrated circuit chips
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- G—PHYSICS
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- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2208—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems
- H01Q1/2225—Supports; Mounting means by structural association with other equipment or articles associated with components used in interrogation type services, i.e. in systems for information exchange between an interrogator/reader and a tag/transponder, e.g. in Radio Frequency Identification [RFID] systems used in active tags, i.e. provided with its own power source or in passive tags, i.e. deriving power from RF signal
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- H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
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- H01Q7/00—Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop
- H01Q7/005—Loop antennas with a substantially uniform current distribution around the loop and having a directional radiation pattern in a plane perpendicular to the plane of the loop with variable reactance for tuning the antenna
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
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- H05K3/4069—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
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- H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
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- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
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- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1453—Applying the circuit pattern before another process, e.g. before filling of vias with conductive paste, before making printed resistors
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/423—Plated through-holes or plated via connections characterised by electroplating method
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- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49146—Assembling to base an electrical component, e.g., capacitor, etc. with encapsulating, e.g., potting, etc.
Definitions
- the present invention relates to a module and, in particular, to a module including an electronic device, and to a method for making same.
- a module including an electronic device
- a method for making same As credit cards, phone cards, identification tags and badges, and other forms of identification devices and other commercial objects have become more sophisticated to offer greater capabilities and access to more services, the need for such objects to include more than just a stripe of magnetic material into which information is encoded has been recognized. Not only is the need recognized to store more information than can be encoded in a magnetic stripe, but also the need to include in the object electronic circuitry to receive, process and output information.
- the circuitry includes a microprocessor or a memory, or both.
- Information is provided to the card and is received from the card in the form of electronic signals by a card reader which typically includes electronic circuitry to verify or identify the information provided by the card in relation to the information provided to the card. For example, where the card is utilized as an access badge, the card reader signals the badge to provide identification information, and if the information provided matches information stored in the card reader to identify an authorized badge, then the card reader authorizes access, such as by releasing an electrical lock.
- a card may be utilized as a substitute for money.
- the card reader such as a point-of-sale terminal, cash register or automated teller machine, first verifies the identity of the money card as authorized to conduct a transaction and then queries the card as to the value of money it represents. If the card reader determines that the value of money represented by the card is sufficient to complete the transaction, then the card reader may subtract the value of the transaction and transmit to the money card the remaining value which is stored in memory in the card. The card reader may also, if the money card is a credit card, communicate with the bank or other institution that issued the card to make appropriate account entries.
- Conventional cards such as card 10 of FIGURE 1, are made of a plastic material and have a cavity 32 therein into which a module 20 including the contacts 26 and the electronic circuitry 24 is inserted.
- the module 20 includes a conventional printed wiring circuit board 22 having the contacts 26 on one surface thereof and connections 28 to the electronic circuitry 24 on the opposite surface thereof.
- the contacts 26 are typically formed by etching the copper conductive sheets on the opposing surfaces of an insulating substrate 22, such as an FR4 or other circuit board material, and forming connections between the opposing surfaces by drilling holes through the circuit board substrate and then filling the holes with conductive material, such as by plating the holes with copper.
- the individual circuit boards must be separated and cut to size , such as by routing, before electronic circuitry 24 is attached thereto.
- Electronic circuitry 24 is attached to circuit board 22 and connections 26 thereto are made by wire bonding (as illustrated) or by flip-chip interconnections. Finally, a glob of encapsulant 18 is applied to cover electronic circuitry 24 and may be ground flat to obtain a controlled height dimension with respect to circuit board 22.
- conventional module 20 requires many separate operations, such as masking, etching, drilling, plating, routing, soldering, attaching, wire bonding, encapsulating and grinding, each of which adds undesirable processing time and cost to the manufacture of module 20. Further, much of the processing must be performed on each individual circuit board 22 separately, adding further handling and cost. Conventionally, module 20 resides in a cavity 32 of a card blank 30.
- Circuit board 22 of conventional module 20 is larger than is the electronic circuitry 24 thereon and the cavity 32 in the card blank 30 has an opening of like size and shape to that of circuit board 22.
- the main portion 34 of cavity 32 is smaller than the circuit board 22 and larger than the electronic circuitry 24 so as to form a shoulder 36 upon which circuit board 22 rests to properly position module 20 with respect to card 10.
- card blank 30 is formed of at least three layers of plastic material laminated together.
- the first layer 40 has a hole that defines the opening into which circuit board 22 is positioned and is of like thickness to circuit board 22.
- the second layer 42 has a hole that defines the volume in which electronic circuitry 24 resides, and is at least as thick as the maximum height of electronic circuitry 24 and encapsulant 18.
- the third layer 44 forms the bottom of cavity 32 and is of sufficient thickness to protect electronic circuitry 24.
- the present invention comprises a pattern of metal contacts having a first and a second surface, a layer of dielectric adhesive on the first surface of the pattern of metal contacts and having at least two holes therethrough to the first surface of the metal contacts, at least two electrically-conductive vias substantially filling the holes in the dielectric adhesive layer and contacting the first surface of the metal contacts, each conductive via having an end distal from the first surface of the metal contacts, and at least one electronic device having electrical contacts connected to the distal end of the conductive vias.
- a method of making a module including an electronic device comprises: providing a sheet of electrical contact material having first and second surfaces; providing an electronic device having a pattern of contacts thereon; forming a pattern of electrically-conductive vias on the first surface of the sheet of electrical contact material, the pattern of electrically-conductive vias corresponding to the pattern of contacts of the electronic device; applying a layer of dielectric adhesive on the first surface of the sheet of electrical material except in locations corresponding to the electrically- conductive vias; patterning the sheet of electrical material to define a pattern of electrical contacts thereon, wherein ones of the electrical contacts are associated with at least corresponding ones of the electrically-conductive vias; and attaching the electronic device with the contacts of the electronic device electrically connected to corresponding electrically-conductive vias.
- FIGURE 1 is an exploded partial cross-sectional side view of a conventional contact module card
- FIGURES 2 - 3 are plan views of a metal layer employed in the module of FIGURE 6 in accordance with the present invention.
- FIGURES 4 - 6 are side cross-sectional views further illustrating the fabrication of the module of FIGURE 6 in accordance with the present invention.
- FIGURES 7 and 8 are side cross-sectional views of further arrangements of the module of FIGURE 6 in accordance with the present invention.
- FIGURES 9, 10 and 11 are plan views illustrating the fabrication of a plurality of modules as in FIGURE 6 or FIGURE 7 as a panel of modules;
- FIGURES 10A and FIGURE 11 A are enlarged views of respective portions of FIGURES 10 and 11;
- FIGURE 12 is a plan view of an exemplary package in which the modules of
- FIGURES 6, 7 and 8 may be stored
- FIGURE 13 is a side cross-sectional view of a further arrangement of the module of FIGURE 6 in accordance with the present invention.
- FIGURE 14 is an exploded side cross-sectional view of the module of FIGURE 13 in an article in accordance with the present invention.
- module 100 is arranged such that insofar as is practical the steps of the processing generally add structure to what has been thus far made and to reduce the number of steps in which material is removed. Moreover, the arrangement of contact module 100 lends itself to the convenient fabrication of a plurality of modules contemporaneously on a single panel, wherein the panel need not be separated into individual modules until at or near the final operation of the fabrication, thereby to reduce the handling and processing of modules individually and to eliminate the cost thereof.
- FIGURE 2 is a plan view of a metal layer 110 employed in the module 100 in accordance with the present invention.
- Metal layer 110 is a thin sheet or foil of electrically conductive metal, such as a metal foil conventionally utilized to form lead frames for semiconductor integrated circuits or utilized in laminating printed wiring circuit boards. Suitable materials include copper, alloy 42, aluminum, nickel, kovar, and combinations and alloys thereof, beryllium copper, brass and other copper-based alloys, iron-based alloys, and other suitable metals, and laminates thereof.
- Metal layer 110 is later formed, for example, by photo-etching, to provide the external electrical contacts 114 of module 100, as described below, for transmitting and receiving electrical signals to and/or from a conventional card reader.
- FIGURE 3 is a plan view and FIGURE 4 is a side cross-sectional view of the metal layer 110 on which is applied a layer 120 of a dielectric material having suitable electrical insulating (i.e. dielectric) properties and suitable mechanical strength, rigidity and stability.
- Dielectric layer 120 is preferably a thermoplastic or thermosetting adhesive that is either deposited on metal layer 110 as a liquid or paste and is then dried or B-staged, i.e. is heated for a period of time to evaporate solvent or to form partial polymeric cross-links, or both, or is a sheet of B-staged thermoplastic or thermosetting adhesive that is laminated to metal layer 110.
- dielectric layer 120 is applied by screen printing, stenciling, roll coating, , mask printing, ink-jet printing, laminating or other suitable method.
- a pattern of via holes 130 in dielectric layer 120 expose a pattern of sites of metal layer 110 corresponding to contacts to be formed therein.
- the pattern of via holes 130 correspond to the pattern of contacts 142 of an electronic device 140 that electrically connect to the external contacts of module 100 formed of metal layer 110, as described below.
- the via holes 130 may be formed by the screen, stencil, mask or other printing device, or may be present in the sheet of B-staged adhesive as laminated to metal layer 110, or, alternatively, may be subsequently formed, as by laser drilling, plasma etching, photo- etching, or other suitable method.
- FIGURE 5 is a side cross-sectional view further illustrating the fabrication of the module 100.
- metal is shown plated or otherwise deposited onto metal layer 110 through via holes 130 to form via contacts (or via conductors) 132, e.g., 132a, 132b, that substantially fill via holes 130, and preferably extend slightly beyond the surface of dielectric layer 120.
- Via conductors 132a, 132b are preferably formed of the same metal as is metal layer 110. It is noted that the depositing dielectric layer
- via conductors 132a, 132b can be performed in orders other than that just described.
- holes in a patterned photoresist deposited on metal layer 110 may be utilized to define the size and locations of via conductors 132a, 132b into which metal is then plated or otherwise deposited onto metal layer 110 to form via conductors 132a, 132b.
- the photoresist is removed and the dielectric layer 120 is applied, in like manner to that described above.
- dielectric layer 130 provides mechanical strength for and supports metal layer 110 and via conductors 132a, 132b.
- Metal layer 110 is patterned to form a pattern of electrical contacts 114, e.g., 114a, 114b that are electrically isolated from each other by gaps 116 and that are electrically connected to at least one of via conductors 132a, 132b, 134. Patterning of metal layer 110 is preferably by conventional photo- or chemical etching as is employed in the manufacture of printed wiring circuit boards, for example, or by other suitable methods.
- metal layer 110 is of a metal that may oxidize or otherwise not maintain good electrical conductivity, such as copper or aluminum
- a layer of an oxidation resistant metal such as nickel, tin, silver, gold, platinum, palladium, nickel- palladium, nickel-gold or other precious metal, or a combination or alloy thereof, is applied as layer 112 on contacts 114a, 114b and as layers 134a, 134b on via contacts 132a, 132b, respectively.
- FIGURE 6 is a side cross-sectional view further illustrating the fabrication of the module 100 in accordance with the present invention.
- An electronic device 140 such as a semiconductor die, an integrated circuit or a network of resistive, inductive and/or capacitive elements, or the like, is attached to metal layer 110 and dielectric layer 120.
- electronic device 140 is attached in a flip-chip manner, i.e. a number of contact pads 140, e.g., 142a, 142b, thereon are electrically connected to corresponding ones of via conductors 132a, 132b.
- the locations of the contact pads 142a, 142b of electronic device 140 and of via conductors 132a, 132b correspond so that electrical connections therebetween may be made by bumps 144 of a suitable electrically-conductive material, for example, solder, electrically-conductive adhesive or other electrically-conductive polymer, which also mechanically attach electronic device 140 thereto.
- the electrically-conductive adhesive is a flexible adhesive, i.e. an adhesive having a modulus of elasticity that is less than about 35,000 kg/m 2 (about 500,000 psi) or having the ability to withstand at least 30% elongation before failure, as may be the dielectric adhesive.
- a dielectric underfill 146 preferably of an electrically-insulating adhesive
- Bumps 144 of electrically- conductive adhesive or solder may be deposited onto via conductors 132a, 132b or may be deposited onto the contact pads 142a, 142b of electronic device 140, for example, by screen printing, mask printing, stencil printing, ink jet printing or other suitable manner.
- Bumps 144 and underfill 146 may be applied as a preformed membrane of the insulating underfill 146 material having the desired pattern of conductive material 144 formed therein, for example, as described in U.S. Patent
- contacts 142 of electronic device 140 which are often of aluminum, are coated with a layer of an oxidation resistant metal, such as nickel, tin, silver, gold, platinum, palladium, nickel-palladium, nickel-gold or other precious metal, or a combination or alloy thereof.
- an oxidation resistant metal such as nickel, tin, silver, gold, platinum, palladium, nickel-palladium, nickel-gold or other precious metal, or a combination or alloy thereof.
- FIGURE 7 is a side cross-sectional view of an arrangement of module 100 of FIGURE 6 including an encapsulating material 150.
- Encapsulating material 150 surrounds electronic device 140 to seal at least the region in which electrical contacts 132a, 132b, 142a, 142b and connections 144 reside, thereby to provide resistance to the intrusion of moisture, chemicals and other contaminants.
- encapsulating material 150 preferably covers electronic device 140 and is a high-flow adhesive that can also provide the means for attaching module 100' to a next level article with which it is to be assembled for use, such as a "smart card", credit card, money card identification tag or badge, or the like. Any adhesive with leveling ability to form a flat surface is generally suitable.
- One suitable encapsulating adhesive is a type MB7060 thermoplastic adhesive available from Al Technology located in Princeton, New Jersey, which has the beneficial property of a low melt-flow temperature of about 70 °C which is compatible with the polyvinyl chloride, polyester and other plastic materials of which such next-level articles are typically made.
- Encapsulating adhesive 150 is preferably applied to a panel of a plurality of modules 100 before they are singulated or separated into individual modules.
- FIGURE 8 is a side cross-sectional view of an alternative embodiment 100' of module 100 of FIGURE 6 in which electrical connections to electronic device 140 are made by conventional wire bonds 143a, 143b rather than by conductive adhesive bumps 144.
- Electronic device 140 is attached to metal layer 110 and dielectric layer
- a conventional die-attach adhesive 148 typically an electrically-conductive adhesive, with its contact pads 142a, 142b exposed. Electrical connections between contact pads 142a, 142b of electronic device 140 and conductive vias 132a, 132b, respectively, are made by conventional wire bonds 143a, 143b formed by wire bonding fine wires of gold or aluminum. Electronic device 140 and wire bonds 143a,
- module 143 b may be encapsulated by conventional glob-top or other molded encapsulating dielectric material 152.
- module 100' may be encapsulated by a high melt flow encapsulating material 150 of like type to that described in relation to FIGURE 7, whether or not the conventional encapsulation 152 is employed.
- the total thickness T of module 100 is the combination of the thicknesses of the metal layer 110, dielectric layer 120, electronic device 140 and encapsulating adhesive 150, and is typically about 375 - 625 ⁇ m (about 15 - 25 mils).
- FIGURES 9, 9A, 10, 10A and 11 are plan views illustrating the fabrication of a plurality of modules 100 as in FIGURE 6 or FIGURE 7 as a panel of modules 100, and the method therefor.
- a typical module 100, 100' intended for use in a next level article such as a "smart card", credit card, money card identification tag or badge, or the like
- the materials employed need only withstand the temperature range to which such commercial article is expected to be exposed, for example, -40 °C to +85 °C.
- a panel 200 that is about 25 cm by 25 cm (about 10 inches by 10 inches) may be employed to contemporaneously fabricate an 18 by 20 array of 360 modules.
- Other sizes of panels may also be employed, such as an about 25 cm by 50 cm (about 10 inch by 20 inch) panel, or an about 50 cm by 50 cm (about 20 inch by 20 inch) panel, as may be convenient.
- Panel 200 has a set of at least two, and preferably more than two, alignment holes 202, for example, a set of alignment holes 202a, 202b, 202c, 202d, for registering the various layers of material and or masks, screens, stencils and the like utilized in the fabrication of modules 100, 100'.
- Dielectric layer 120 is preferably stenciled or screen printed onto the metal panel 200, for example, utilizing the stencil or mask panel 300 shown in FIGURE 10 which includes an 18 by 20 array of repeating patterns 304 of openings 330 corresponding to via holes 130.
- Dielectric layer 120 can also be applied by other conventional methods, such as film lamination, liquid spinning, paste screening and paste draw down methods.
- Stencil 300 includes a set of relational alignment holes
- FIGURE 10A An expanded view of a portion of FIGURE 10 is shown in FIGURE 10A in which ones of the pattern 304 of openings 330 are visible. The relative positions of the set of alignment holes 302, the patterns 304 of openings
- Dielectric layer 120 is preferably of a material that is relatively high in viscosity and thixotropic index, and should preferably contain at least 50% solids so that layer 120 may be deposited with suitable thickness.
- dielectric layer 120 typically has a wet thickness of about 150 ⁇ m (about 6 mils) corresponding to a dry thickness after B-staging of about 100 ⁇ (about 4 mils).
- thermoplastic and thermosetting adhesives may be employed for dielectric layer 120, and should preferably have good rigidity and toughness, for example, as exhibited by adhesives having a modulus of elasticity over about 35,000 kg/m 2 (about 500,000 psi) and an elongation in the range of 3 - 30% when cured.
- Suitable adhesives will not be adversely affected by exposure to the etching and plating chemicals and other chemicals, and to the process environments, utilized in processing operations subsequent to application of the adhesives, whether the adhesive is in its dried or B- staged state or in its cured state at the time of such exposure.
- Suitable adhesives for dielectric layer 130 includes types LESP7670-SC or LESP7450-SC fast-curing thermosetting epoxy adhesive in liquid form, available from Al Technology located in
- thermosetting epoxy adhesives in paste form, and types LESP7675 and ESP7675 thermosetting epoxy adhesives.
- Screened dielectric layer 120 is dried (or B-staged) at an elevated temperature of about 60 - 80 °C to remove the solvent from the deposited adhesive, and is then cured at an elevated temperature in the range of about 80 -150 °C. Curing is typically performed at a temperature of about 100 °C for about 60 minutes, but may be performed at a relatively low temperature of about 80 °C for several hours, or at a relatively higher temperature of about 150 °C for a few minutes. Via holes 130 in dielectric layer 120 typically are of about 50 - 500 ⁇ m (about
- 10A may be utilized in forming dielectric layer 120 either by directly printing dielectric adhesive onto metal layer 110 or by printing dielectric adhesive onto a sheet of release liner, B-staging the adhesive to dryness, and then transferring the sheet of dielectric material 120 and laminating it to metal layer 110 in registration predetermined by the positional relationship of the alignment holes 202 and 302 of metal sheet 200 and of dielectric layer 120, respectively.
- FIGURE 11 shows a mask pattern 400 for an 18 by 20 array of repeating patterns 414 of contacts 1 14, each of which is in predetermined positional relationship with alignment holes 402, i.e. 402a, 402b, 402c, 402d, and fiducial marks 406, i.e. 406a, 406b, 406c.
- the relative positions of the set of alignment holes 402, the patterns 414 of contacts 114 and the fiducial marks 406 are in the same predetermined positional relationship as are alignment holes 302, patterns 304 and fiducial marks 306 of stencil 300.
- a detail view of the pattern 414 of contacts 114 is shown in the expanded view of a portion of stencil 300 of FIGURE 11 A.
- the generally rectangular pattern 414 often contacts 114 is about 11 mm by 12.5 mm (about 0.435 inch by 0.492 inch) with gaps 116 of about 0.25 mm (about 0.01 inch) between the contacts 114, which is the pattern of International Standard ISO-7816-2 entitled "Identification Cards — Integrated Circuit(s) Cards With Contacts” issued by the International Organization for Standardization, and available in the United States from the American National Standards Institute (ANSI) located in New York, New York.
- the panel of modules 100 may now be excised or singulated into individual modules 100 of the sort shown in FIGURE 6, or may be further processed by applying a suitable insulating adhesive 150 to overcoat and/or surround electronic device 140 to obtain a panel of modules 100 of the sort shown in FIGURE 7.
- a suitable insulating adhesive 150 Any adhesive having suitable leveling characteristics to provide a relatively flat surface may be employed.
- One suitable adhesive is type MB7060 or MB7060-W thermoplastic electrically- insulating adhesive available from Al Technology, which has high flow at a melt temperature of about 65 - 75 °C and bonds well to common card materials such as
- Encapsulating adhesive 150 may be applied by conventional methods such as roll coating screen printing, stenciling and the like, or may be applied by laminating a sheet of dried or B-staged adhesive to the panel of modules 100.
- the thickness of the adhesive layer 150 is about the same as the height of electronic device 140, typically about 250 - 500 ⁇ m (about 10 - 20 mils) to form a panel of modules 100 having a slightly greater thickness, typically about 350 -600 ⁇ m (about 14 - 24 mils).
- modules 100, 100' fabricated as described have a substantially planar adhesive layer 150 surface that is substantially parallel to the plane in which contacts 114 lie, modules
- the panel of modules 100 is singulated into separate individual modules 100 by any suitable and convenient method, such as die cutting or other cutting device, or by laser cutting, stamping and rotary die cutting.
- the adhesive employed in layer 120 is a high-strength adhesive, it is preferred that the high-strength adhesive be only dried or B-staged during the fabrication of the panel and that the panel be singulated into individual modules prior to curing the adhesive.
- panels of modules 100 may be processed in continuous fashion by abutting the panels and providing sprocket drive holes therein and a sprocket drive mechanism or by forming modules 100 on a continuous web or strip of dielectric substrate 120 material or metal foil 200.
- dielectric adhesive is applied, electroplating and photo-etching is performed, conductive adhesive is deposited continuously as the panels, web or strip, as the case may be, passes respective stations performing such operations. Any of the following three processes may be utilized to the end of making a circuit substrate of module 100, 100'.
- a first photoresist or other suitable masking resin is applied, selectively exposed as through a mask to form selective cross-links, and developed to define the pattern of contact pads 114 of the individual modules for subsequent metallization.
- a layer 112 of nickel, or other suitable passivating metal is deposited onto contacts 114 and onto the via sites at the bottoms of via holes 130, typically to a thickness of a few microns (i.e. micrometers) such as by electrolytic or electroless plating.
- the plating of the nickel onto the via sites should be of sufficient thickness to fill via holes 130 with metal so as to be at or slightly above the surface of dielectric layer 120, thereby forming via conductors 132.
- This may be by plating nickel to the necessary thickness, or by plating copper onto the via sites, such as by electrolytic plating, to fill via holes 130 with metal to form via conductors 132 and then plating a layer 134 of nickel thereon.
- the nickel layers 112, 134 on contacts 114 and via conductors 132 are finished with a flash or electroplate of gold or palladium or other precious metal for reduced electrical resistance, unless satisfactory electrical contact can be obtained and maintained with the nickel layer 112, 134 alone.
- the first photoresist is then stripped away and a second photoresist is applied to metal layer 110 to cover the contacts 114, and is exposed and developed to define the areas of metal layer 110 to be etched away to provide gaps 116 between contacts 114.
- the exposed vias 132, 134 extending from dielectric layer 130 may also be masked.
- Metal layer 110 is then etched or stripped chemically to leave the pattern of contacts 114.
- the first photoresist may be left in place until after the photo-etching of metal layer 110, and then both the first and second photoresists maybe removed.
- a module 100, 100' circuit substrate of metal layer 110 and dielectric layer 120 having larger contacts 114 on one side thereof for making contact with a card reader and having smaller contacts 132,
- a photoresist is applied to metal layer 110 to cover the areas of metal layer 110 that will be contacts 114, and is exposed and developed to define the metal to be etched away to provide gaps 116 between contacts 114.
- the exposed via holes 130 in dielectric layer 130 may also be masked to prevent etching of the via sites at the bottom thereof on metal layer 110.
- metal layer 110 is then etched or stripped chemically to leave the pattern of contacts 114 and then the photoresist is stripped away.
- a layer 112 of nickel, or other suitable passivating metal is deposited onto contacts 114 and onto the via sites at the bottoms of via holes 130, typically to a thickness of a few microns (i.e.
- the plating of the nickel onto the via sites should be of sufficient thickness to fill via holes 130 with metal so as to be at or slightly above the surface of dielectric layer 120, thereby forming via conductors 132.
- This may be by plating nickel to the necessary thickness, or by plating copper onto the via sites, such as by electrolytic plating, to fill via holes 130 with metal forming via conductors 132 and then plating a layer 134 of nickel thereon.
- the nickel layers 112, 134 on contacts 114 and via conductors 132 are finished with a flash of gold or palladium or other precious metal for reduced electrical resistance, unless satisfactory electrical contact can be obtained and maintained with the nickel layer 112, 134 alone.
- via conductors 132 are built up of deposited copper
- the nickel finish 112, 134 on contacts 114 and on via contacts 132 may be deposited at the same time and after the copper is deposited.
- a module 100, 100' circuit substrate of metal layer 110 and dielectric layer 120 having larger contacts 114 on one side thereof for making contact with a card reader and having smaller contacts 132, 134 on the other side thereof for making connection to an electronic device 140 is provided.
- a photoresist or other suitable masking resin is applied to exposed metal layer 110, but is not exposed or developed at this time. Copper is then plated onto the via sites at the bottom of via holes 130 of sufficient thickness to fill via holes 130 with copper so as to be at or slightly above the surface of dielectric layer 120, thereby forming via conductors 132.
- the photoresist is then exposed and developed to define the pattern of contact pads 114 of an individual module, i.e. to define the areas of metal layer 110 that will remain to provide contacts 114.
- a layer 112, 134 of nickel, or other suitable passivating metal, is deposited onto contacts 114 and onto via conductors 132, typically to a thickness of a few microns (i.e.
- the nickel layers 112, 134 on contacts 114 and via conductors 132 are finished with a flash or electroplate of gold or palladium or other precious metal for reduced electrical resistance, unless satisfactory electrical contact can be obtained and maintained with the nickel layer alone.
- the photoresist is then stripped away and a suitable solution is applied to preferentially etch metal layer 110 chemically to remove the uncovered copper areas, but leave the pattern of contacts 114 which are protected by the nickel or nickel/gold layers that are unaffected by the preferential etching solution.
- a second photoresist can be applied, exposed and developed to protect contacts 114 and via conductors 132, 134 against etching.
- a module 100, 100' circuit substrate of metal layer 110 and dielectric layer 120 having larger contacts 114 on one side thereof for making contact with a card reader and having smaller contacts 132, 134 on the other side thereof for making connection to an electronic device 140 is provided.
- via conductors 132, 134 may be built up of an electrically- conductive adhesive deposited onto metal layer 110, preferably over a thin layer of nickel, gold or other suitable passivating metal deposited on the via sites on metal layer 110, for example, at the bottoms of via holes 130.
- Connecting bumps 144 are preferably directly deposited as by screen or mask printing onto the contact pads 142 of electronic device 140 or onto the contacts 114 of the circuit substrate of module 100, 100'.
- the preferred material is a flexible electrically-conductive adhesive having a high thixotropic index which facilitates precise deposition.
- Suitable electrically-conductive adhesives include types PSS8090 and PSS8150 thermoplastic polymer adhesives and type ESS8450 thermosetting polymer adhesives in paste form, also available from Al Technology.
- Connecting adhesive bumps 144 are printed with a wet thickness of about 50 - 100 ⁇ m (about 2-4 mils), and electronic device 140 may be attached thereto while the adhesive is still wet.
- the adhesive is then dried at an elevated temperature of about 60 - 80 °C for about 30 - 60 minutes to form a satisfactory electrical and mechanical connection and bond between contacts 142 of electronic device 140 and via contacts 132, 134 of module 100, 100'.
- bumps 144 may be solder bumps.
- an underfill of a low viscosity, non-thixotropic, and therefore, high flow, adhesive may be employed.
- Suitable underfill adhesives include type MEE7650 flexible thermosetting insulating adhesive and type MEE7660 high-strength thermosetting adhesive available from Al Technology, which are cured at a temperature of about 80 - 150 °C similar to the type LESP7675 adhesive employed in dielectric layer 120 as described above.
- module 100, 100' is suitable for utilization in many different kinds and types of next-level articles, such as smart cards, identification tags, credit and money cards and the like made by conventional and new methods.
- suitable articles include, for example, those described in U.S. Patent Application Serial Number 09/ (AI-TECH- 11 ) entitled ""Article Having An Embedded
- Completed modules 100, 100' may, for convenience, be stored in a waffle package 500 shown in FIGURE 12 which has an 18 by 20 array of receptacles 504 each of a size to receive a module 100, 100'.
- package 500 includes a set of relational alignment holes 502, preferably in like positional relationship to the alignment holes 202, 302 and 402 of metal panel 200, via stencil 300 and contact stencil 400, respectively.
- FIGURE 13 is a side cross-sectional view of a module 100" including plural electronic devices 140, 170, 180, 190 connected by conductors 160, but otherwise similar to contact module 100 of FIGURE 6 in construction and materials, in accordance with the present invention.
- Electronic devices 140, 170, 180, 190 may be integrated circuits, diodes, transistors, resistors, capacitors, inductors, or networks of such components, or any combination thereof.
- Contacts 114a, 114b, dielectric layer 120, conductive vias 142a, 142b and electronic device 140 are as described above.
- conductive vias 147, 147 and 149 are built up on the metal layer 110 by depositing electrically-conductive adhesive (e.g., types ESS8450 and PSS8150 available from Al Technology) or building up metal (e.g., copper, nickel or aluminum) thereon and are provided for connecting electronic devices 170, 180, 190, respectively, in circuit, and are fabricated substantially contemporaneously with conductive vias 142a, 142b.
- electrically-conductive adhesive e.g., types ESS8450 and PSS8150 available from Al Technology
- building up metal e.g., copper, nickel or aluminum
- metal layer 110 When metal layer 110 is removed as by photo-etching to leave the pattern of contacts 114a, 114b, the metal of layer 110 proximate conductive vias 147, 148, 149 is substantially removed leaving conductive vias 147, 148, 149 flush with the surface of dielectric layer 120 or projecting slightly therefrom.
- a layer of oxidation-resistant nickel-gold is deposited relatively heavily on the exposed portions of contacts 114a, 114b, and relatively lightly on the exposed portions of conductive vias 132a, 132b, 147. 148, 149.
- Conductors 160 are preferably conductive adhesive (such as type PSS8150 or type ESS8450) deposited on dielectric layer 120 (such as type ESP7450 insulating adhesive) and contacting conductive vias 132a, 132b, 147, 148, 149 for connecting them in circuit.
- the respective contacts of electronic devices 140, 170, 180, 190 are attached to conductive vias 132a, 132b, 147, 148, 149 by bumps 144, 174, 184, 194 of conductive material such as solder and electrically-conductive adhesive, which may be applied either to the ends of vias 123a, 132b, 147, 148, 149 or to the contacts of electronic devices 140, 170, 180, 190.
- solder bumps or conductive adhesive bumps, or both may be employed on a given module 100", and in fact it may be preferable to employ flexible conductive adhesive bumps for connecting an integrated circuit device and solder bumps for connecting resistors, capacitors, and the like.
- Conductive bumps 144, 174, 184, 194 may be about 70 ⁇ m (about 3 mils) diameter, or other suitable size. Suitable underfill may be utilized between devices 140, 170, 180, 190, if desired, to increase the strength of the bonding of devices 140, 170, 180, 190 to dielectric layer 120.
- solder bumps can be employed with conductive vias and conductors formed of electrically-conductive adhesive that have been plated with a suitable metal, such as nickel, gold, nickel-gold and the like, as well as with metal conductive vias. Further, suitable insulating underfill may be utilized to strengthen the attachment of one or more of electronic devices 140, 170, 180, 190 as desired.
- FIGURE 14 is an exploded side cross-sectional view of the contact module 100"of FIGURE 13 included in an article 600.
- Module 100" is laminated between two card blanks 610, 620 where article 600 is to be utilized as a credit card, debit card, smart card or the like, and may be laminated only to card blank 610 where it is to be utilized as an identification tag or the like.
- card blank 610 includes a thin layer 612 of high melt-flowable adhesive (e.g., an about 25 ⁇ m thick (about 1 mil thick) layer of type MB7060 or type MB7100 adhesive) that serves to bond card blank 610 to module 100".
- high melt-flowable adhesive e.g., an about 25 ⁇ m thick (about 1 mil thick) layer of type MB7060 or type MB7100 adhesive
- Card blank 610 is of like thickness to contacts 114a, 114b, for example, about 75 m (about 3 mils) each, and has an aperture 614 therethrough into which contacts 114a, 114b fit so as to be exposed and substantially flush with or extending slightly above the surface of card blank 610.
- Dielectric layer 120 is preferably also of like thickness thereto.
- Module 100" is coated with a layer 150 of high melt-flowable adhesive (e.g., also of type MB7060 or type MB7100 adhesive) that is of sufficient thickness to encapsulate electronic devices 140, 170, 180, 190 to dielectric substrate 120 and also serves to attach card blank 620 to module 100".
- high melt-flowable adhesive e.g., also of type MB7060 or type MB7100 adhesive
- Card blank 620 is typically of like thickness to card blank 610 and contacts 114a, 114b, for example, about 75 ⁇ m (about 3 mils).
- Card blanks 610, 620 are of conventional materials, for example, of PVC or polyester, and the like.
- the thickness of adhesive layer 150 is selected not only to cover electronic devices 140, 170, 180, 190, but to establish the overall thickness of article 600 at a desired dimension, such as the 0.785 mm (about 31 mil) thickness of standard credit cards, smart cards and the like.
- a desired dimension such as the 0.785 mm (about 31 mil) thickness of standard credit cards, smart cards and the like.
- an about 535- m (about 21-mil) thick layer 150 combines with the three 75- ⁇ m (3-mil) thicknesses of card blanks 610, 620 and of dielectric layer 120, plus the 25- m (1-mil) thick adhesive layer 612, for an overall thickness of about 0.785 mm (about 31 mils).
- these thicknesses are compatible with the height of electronic devices 140. 170, 180, 190, which are about 500 ⁇ m (about 20 mils) or less.
- each device should preferably be about 400 - 450 ⁇ m (about 16 - 18 mils) or less when connected by solder bumps and about 450 - 500 ⁇ m (about 18 - 20 mils) when connected by conductive adhesive bumps, which bumps are typically of 70- ⁇ m (3-mil) diameter.
- a typical 405- ⁇ m (16-mil) thick electronic device attached by 75- ⁇ m (3-mil)conductive bumps has a height of about 480 ⁇ m (19 mils).
- conductive vias could be formed by depositing a pattern of electrically-conductive adhesive onto metal contacts 114, either before or after dielectric adhesive layer 120 is deposited thereon, as by screen printing, stencil printing, mask printing or other suitable method.
- electroless and electrolytic plating electroless and electrolytic plating (electroplating) is preferred, other deposition methods such as chemical plating, immersion coating and the like may be utilized.
Abstract
A module (100), such as a contact module for embedding an electronic device into a credit card, smart card, identification tag or other article, comprises a pattern of metal contacts (114a, 114b) having a first and a second surface and electrically conductive vias (132a, 132b) built up on the first surface of the metal contacts (114a, 114b). A layer of dielectric adhesive (120) on the first surface of the pattern of metal contacts (114a, 114b) surrounds the electrically conductive vias (132a, 132b) except the ends open (134a, 134b) thereof distal from the metal contacts (114a, 114b). An electronic device (140) has electrical contacts (142a, 142b) connected to the exposed ends (134a, 134b) of the conductive vias (132a, 132b), as by wire bonds or by flip-chip type connections (144).
Description
- i -
CONTACTMODULE,AS FORASMART CARD, ANDMETHODFORMAKING SAME
This Application claims the benefit of U.S. Provisional Application Serial Number 60/ 129,497 filed April 15, 1999, of U.S. Provisional Application Serial Number 60/ 131,377 filed April 28, 1999, of U.S. Provisional Application Serial Number 60/ 134,656 filed May 18, 1999, of U.S. Provisional Application Serial Number 60/ 141 ,344 filed June 28, 1999, and of U.S. Patent Application Serial
Number 09/412,052 filed on October 4, 1999.
The present invention relates to a module and, in particular, to a module including an electronic device, and to a method for making same. As credit cards, phone cards, identification tags and badges, and other forms of identification devices and other commercial objects have become more sophisticated to offer greater capabilities and access to more services, the need for such objects to include more than just a stripe of magnetic material into which information is encoded has been recognized. Not only is the need recognized to store more information than can be encoded in a magnetic stripe, but also the need to include in the object electronic circuitry to receive, process and output information.
Conventionally, electronic circuitry in the form of semiconductor integrated circuits has been embedded into cards, tags and badges to receive, process and output information. Typically, the circuitry includes a microprocessor or a memory, or both. Information is provided to the card and is received from the card in the form of electronic signals by a card reader which typically includes electronic circuitry to verify or identify the information provided by the card in relation to the information provided to the card. For example, where the card is utilized as an access badge, the card reader signals the badge to provide identification information, and if the information provided matches information stored in the card reader to identify an authorized badge, then the card reader authorizes access, such as by releasing an
electrical lock. In a more complex application, a card may be utilized as a substitute for money. The card reader, such as a point-of-sale terminal, cash register or automated teller machine, first verifies the identity of the money card as authorized to conduct a transaction and then queries the card as to the value of money it represents. If the card reader determines that the value of money represented by the card is sufficient to complete the transaction, then the card reader may subtract the value of the transaction and transmit to the money card the remaining value which is stored in memory in the card. The card reader may also, if the money card is a credit card, communicate with the bank or other institution that issued the card to make appropriate account entries.
Irrespective of the details of how a particular card, tag or badge functions, information in the form of electrical signals must be transmitted between the card, tag or badge and the card reader. Conventionally, this is accomplished by electrical contacts in predetermined locations on the card coming into electrical contact with corresponding contacts in the card reader to complete an electrical circuit.
Conventional cards, such as card 10 of FIGURE 1, are made of a plastic material and have a cavity 32 therein into which a module 20 including the contacts 26 and the electronic circuitry 24 is inserted. The module 20 includes a conventional printed wiring circuit board 22 having the contacts 26 on one surface thereof and connections 28 to the electronic circuitry 24 on the opposite surface thereof. The contacts 26 are typically formed by etching the copper conductive sheets on the opposing surfaces of an insulating substrate 22, such as an FR4 or other circuit board material, and forming connections between the opposing surfaces by drilling holes through the circuit board substrate and then filling the holes with conductive material, such as by plating the holes with copper. The individual circuit boards must be separated and cut to size , such as by routing, before electronic circuitry 24 is attached thereto. Electronic circuitry 24 is attached to circuit board 22 and connections 26 thereto are made by wire bonding (as illustrated) or by flip-chip interconnections. Finally, a glob of encapsulant 18 is applied to cover electronic circuitry 24 and may be ground flat to obtain a controlled height dimension with respect to circuit board 22. Thus, conventional module 20 requires many separate operations, such as masking, etching,
drilling, plating, routing, soldering, attaching, wire bonding, encapsulating and grinding, each of which adds undesirable processing time and cost to the manufacture of module 20. Further, much of the processing must be performed on each individual circuit board 22 separately, adding further handling and cost. Conventionally, module 20 resides in a cavity 32 of a card blank 30. Circuit board 22 of conventional module 20 is larger than is the electronic circuitry 24 thereon and the cavity 32 in the card blank 30 has an opening of like size and shape to that of circuit board 22. The main portion 34 of cavity 32 is smaller than the circuit board 22 and larger than the electronic circuitry 24 so as to form a shoulder 36 upon which circuit board 22 rests to properly position module 20 with respect to card 10. Module
20 is attached to card blank 30 by adhesive dispensed into cavity 32, the amount of which must be precisely controlled to bond to encapsulant 18 or to electronic circuitry 24 and circuit board 22, or by adhesive dispensed onto shoulder 26 to bond circuit board 22 thereto. Conventionally, card blank 30 is formed of at least three layers of plastic material laminated together. The first layer 40 has a hole that defines the opening into which circuit board 22 is positioned and is of like thickness to circuit board 22. The second layer 42 has a hole that defines the volume in which electronic circuitry 24 resides, and is at least as thick as the maximum height of electronic circuitry 24 and encapsulant 18. The third layer 44 forms the bottom of cavity 32 and is of sufficient thickness to protect electronic circuitry 24. Each of the many operations, the three- layer lamination, adhesive dispensing and module placement, all undesirably add to the complexity and cost of card 10.
Unfortunately, even when conventional card 10 is manufactured using automated equipment, the many different operations required each add to the cost of card 10 and so it is relatively expensive to manufacture.
Accordingly, there is a need for a module that is much simpler and less costly to manufacture, and it would also be advantageous if the simplified module also allowed simplification of the card blank and assembly. To this end, the present invention comprises a pattern of metal contacts having a first and a second surface, a layer of dielectric adhesive on the first surface of the
pattern of metal contacts and having at least two holes therethrough to the first surface of the metal contacts, at least two electrically-conductive vias substantially filling the holes in the dielectric adhesive layer and contacting the first surface of the metal contacts, each conductive via having an end distal from the first surface of the metal contacts, and at least one electronic device having electrical contacts connected to the distal end of the conductive vias.
According to another aspect of the present invention, a method of making a module including an electronic device comprises: providing a sheet of electrical contact material having first and second surfaces; providing an electronic device having a pattern of contacts thereon; forming a pattern of electrically-conductive vias on the first surface of the sheet of electrical contact material, the pattern of electrically-conductive vias corresponding to the pattern of contacts of the electronic device; applying a layer of dielectric adhesive on the first surface of the sheet of electrical material except in locations corresponding to the electrically- conductive vias; patterning the sheet of electrical material to define a pattern of electrical contacts thereon, wherein ones of the electrical contacts are associated with at least corresponding ones of the electrically-conductive vias; and attaching the electronic device with the contacts of the electronic device electrically connected to corresponding electrically-conductive vias.
BRIEF DESCRIPTION OF THE DRAWING
The detailed description of the preferred embodiments of the present invention will be more easily and better understood when read in conjunction with the FIGURES of the Drawing which include:
FIGURE 1 is an exploded partial cross-sectional side view of a conventional contact module card;
FIGURES 2 - 3 are plan views of a metal layer employed in the module of
FIGURE 6 in accordance with the present invention;
FIGURES 4 - 6 are side cross-sectional views further illustrating the fabrication of the module of FIGURE 6 in accordance with the present invention;
FIGURES 7 and 8 are side cross-sectional views of further arrangements of the module of FIGURE 6 in accordance with the present invention;
FIGURES 9, 10 and 11 are plan views illustrating the fabrication of a plurality of modules as in FIGURE 6 or FIGURE 7 as a panel of modules;
FIGURES 10A and FIGURE 11 A are enlarged views of respective portions of FIGURES 10 and 11; FIGURE 12 is a plan view of an exemplary package in which the modules of
FIGURES 6, 7 and 8 may be stored;
FIGURE 13 is a side cross-sectional view of a further arrangement of the module of FIGURE 6 in accordance with the present invention; and
FIGURE 14 is an exploded side cross-sectional view of the module of FIGURE 13 in an article in accordance with the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT In a contact module 100 according to the present invention, module 100 is arranged such that insofar as is practical the steps of the processing generally add structure to what has been thus far made and to reduce the number of steps in which material is removed. Moreover, the arrangement of contact module 100 lends itself to the convenient fabrication of a plurality of modules contemporaneously on a single panel, wherein the panel need not be separated into individual modules until at or near the final operation of the fabrication, thereby to reduce the handling and processing of modules individually and to eliminate the cost thereof.
FIGURE 2 is a plan view of a metal layer 110 employed in the module 100 in accordance with the present invention. Metal layer 110 is a thin sheet or foil of electrically conductive metal, such as a metal foil conventionally utilized to form lead frames for semiconductor integrated circuits or utilized in laminating printed wiring circuit boards. Suitable materials include copper, alloy 42, aluminum, nickel, kovar, and combinations and alloys thereof, beryllium copper, brass and other copper-based
alloys, iron-based alloys, and other suitable metals, and laminates thereof. Metal layer 110 is later formed, for example, by photo-etching, to provide the external electrical contacts 114 of module 100, as described below, for transmitting and receiving electrical signals to and/or from a conventional card reader. FIGURE 3 is a plan view and FIGURE 4 is a side cross-sectional view of the metal layer 110 on which is applied a layer 120 of a dielectric material having suitable electrical insulating (i.e. dielectric) properties and suitable mechanical strength, rigidity and stability. Dielectric layer 120 is preferably a thermoplastic or thermosetting adhesive that is either deposited on metal layer 110 as a liquid or paste and is then dried or B-staged, i.e. is heated for a period of time to evaporate solvent or to form partial polymeric cross-links, or both, or is a sheet of B-staged thermoplastic or thermosetting adhesive that is laminated to metal layer 110. Preferably, dielectric layer 120 is applied by screen printing, stenciling, roll coating, , mask printing, ink-jet printing, laminating or other suitable method. A pattern of via holes 130 in dielectric layer 120 expose a pattern of sites of metal layer 110 corresponding to contacts to be formed therein. Preferably, the pattern of via holes 130 correspond to the pattern of contacts 142 of an electronic device 140 that electrically connect to the external contacts of module 100 formed of metal layer 110, as described below. The via holes 130 may be formed by the screen, stencil, mask or other printing device, or may be present in the sheet of B-staged adhesive as laminated to metal layer 110, or, alternatively, may be subsequently formed, as by laser drilling, plasma etching, photo- etching, or other suitable method. While an exemplary pattern of via holes 130 and via conductors 132 are illustrated, it is understood that other patterns, and greater or lesser numbers of via holes 130 and via conductors 132, may also be employed. FIGURE 5 is a side cross-sectional view further illustrating the fabrication of the module 100. Therein, metal is shown plated or otherwise deposited onto metal layer 110 through via holes 130 to form via contacts (or via conductors) 132, e.g., 132a, 132b, that substantially fill via holes 130, and preferably extend slightly beyond the surface of dielectric layer 120. Via conductors 132a, 132b are preferably formed of the same metal as is metal layer 110. It is noted that the depositing dielectric layer
120 and forming via conductors 132a, 132b can be performed in orders other than that
just described. For example, holes in a patterned photoresist deposited on metal layer 110 may be utilized to define the size and locations of via conductors 132a, 132b into which metal is then plated or otherwise deposited onto metal layer 110 to form via conductors 132a, 132b. After via conductors 132a, 132b are formed, the photoresist is removed and the dielectric layer 120 is applied, in like manner to that described above. In any case, dielectric layer 130 provides mechanical strength for and supports metal layer 110 and via conductors 132a, 132b.
Metal layer 110 is patterned to form a pattern of electrical contacts 114, e.g., 114a, 114b that are electrically isolated from each other by gaps 116 and that are electrically connected to at least one of via conductors 132a, 132b, 134. Patterning of metal layer 110 is preferably by conventional photo- or chemical etching as is employed in the manufacture of printed wiring circuit boards, for example, or by other suitable methods. Where metal layer 110 is of a metal that may oxidize or otherwise not maintain good electrical conductivity, such as copper or aluminum, a layer of an oxidation resistant metal, such as nickel, tin, silver, gold, platinum, palladium, nickel- palladium, nickel-gold or other precious metal, or a combination or alloy thereof, is applied as layer 112 on contacts 114a, 114b and as layers 134a, 134b on via contacts 132a, 132b, respectively.
FIGURE 6 is a side cross-sectional view further illustrating the fabrication of the module 100 in accordance with the present invention. An electronic device 140, such as a semiconductor die, an integrated circuit or a network of resistive, inductive and/or capacitive elements, or the like, is attached to metal layer 110 and dielectric layer 120. Preferably, electronic device 140 is attached in a flip-chip manner, i.e. a number of contact pads 140, e.g., 142a, 142b, thereon are electrically connected to corresponding ones of via conductors 132a, 132b. Also preferably, the locations of the contact pads 142a, 142b of electronic device 140 and of via conductors 132a, 132b correspond so that electrical connections therebetween may be made by bumps 144 of a suitable electrically-conductive material, for example, solder, electrically-conductive adhesive or other electrically-conductive polymer, which also mechanically attach electronic device 140 thereto. Preferably, the electrically-conductive adhesive is a flexible adhesive, i.e. an adhesive having a modulus of elasticity that is less than about
35,000 kg/m2 (about 500,000 psi) or having the ability to withstand at least 30% elongation before failure, as may be the dielectric adhesive. Where greater mechanical strength or support is desired, a dielectric underfill 146, preferably of an electrically-insulating adhesive, may be employed. Bumps 144 of electrically- conductive adhesive or solder may be deposited onto via conductors 132a, 132b or may be deposited onto the contact pads 142a, 142b of electronic device 140, for example, by screen printing, mask printing, stencil printing, ink jet printing or other suitable manner. Bumps 144 and underfill 146 may be applied as a preformed membrane of the insulating underfill 146 material having the desired pattern of conductive material 144 formed therein, for example, as described in U.S. Patent
Application 09/226,543 entitled "Flexible Adhesive Membrane and Electronic Device Employing Same" filed January 7, 1999, which is hereby incorporated herein by reference in its entirety. Also preferably, contacts 142 of electronic device 140, which are often of aluminum, are coated with a layer of an oxidation resistant metal, such as nickel, tin, silver, gold, platinum, palladium, nickel-palladium, nickel-gold or other precious metal, or a combination or alloy thereof.
FIGURE 7 is a side cross-sectional view of an arrangement of module 100 of FIGURE 6 including an encapsulating material 150. Encapsulating material 150 surrounds electronic device 140 to seal at least the region in which electrical contacts 132a, 132b, 142a, 142b and connections 144 reside, thereby to provide resistance to the intrusion of moisture, chemicals and other contaminants. Preferably, encapsulating material 150 preferably covers electronic device 140 and is a high-flow adhesive that can also provide the means for attaching module 100' to a next level article with which it is to be assembled for use, such as a "smart card", credit card, money card identification tag or badge, or the like. Any adhesive with leveling ability to form a flat surface is generally suitable. One suitable encapsulating adhesive is a type MB7060 thermoplastic adhesive available from Al Technology located in Princeton, New Jersey, which has the beneficial property of a low melt-flow temperature of about 70 °C which is compatible with the polyvinyl chloride, polyester and other plastic materials of which such next-level articles are typically made.
Encapsulating adhesive 150 is preferably applied to a panel of a plurality of modules
100 before they are singulated or separated into individual modules.
FIGURE 8 is a side cross-sectional view of an alternative embodiment 100' of module 100 of FIGURE 6 in which electrical connections to electronic device 140 are made by conventional wire bonds 143a, 143b rather than by conductive adhesive bumps 144. Electronic device 140 is attached to metal layer 110 and dielectric layer
120 by a conventional die-attach adhesive 148, typically an electrically-conductive adhesive, with its contact pads 142a, 142b exposed. Electrical connections between contact pads 142a, 142b of electronic device 140 and conductive vias 132a, 132b, respectively, are made by conventional wire bonds 143a, 143b formed by wire bonding fine wires of gold or aluminum. Electronic device 140 and wire bonds 143a,
143 b may be encapsulated by conventional glob-top or other molded encapsulating dielectric material 152. Optionally, or alternatively, module 100' may be encapsulated by a high melt flow encapsulating material 150 of like type to that described in relation to FIGURE 7, whether or not the conventional encapsulation 152 is employed. The total thickness T of module 100 is the combination of the thicknesses of the metal layer 110, dielectric layer 120, electronic device 140 and encapsulating adhesive 150, and is typically about 375 - 625 μm (about 15 - 25 mils).
FIGURES 9, 9A, 10, 10A and 11 are plan views illustrating the fabrication of a plurality of modules 100 as in FIGURE 6 or FIGURE 7 as a panel of modules 100, and the method therefor. In a typical module 100, 100' intended for use in a next level article such as a "smart card", credit card, money card identification tag or badge, or the like, the materials employed need only withstand the temperature range to which such commercial article is expected to be exposed, for example, -40 °C to +85 °C. Thus, the effects of differences in the coefficients of thermal expansion of the various materials utilized in such commercial articles is of less concern due to the limited temperature range than is the case for articles to be exposed to more extreme temperatures, such as the -55 °C to +150 °C range specified for certain aerospace and military articles.
As shown if FIGURE 9, a sheet 200 of copper foil of about 25 - 75 μm (about 1 -3 mils) thickness, and of the same type as that used for conventional printed circuit board wiring fabricated on conventional FR4 material, is typically provided as metal
layer 110 for a plurality of modules 100, 100' to be formed in an array on a panel 200 of material. Typically, a panel 200 that is about 25 cm by 25 cm (about 10 inches by 10 inches) may be employed to contemporaneously fabricate an 18 by 20 array of 360 modules. Other sizes of panels may also be employed, such as an about 25 cm by 50 cm (about 10 inch by 20 inch) panel, or an about 50 cm by 50 cm (about 20 inch by 20 inch) panel, as may be convenient. Panel 200 has a set of at least two, and preferably more than two, alignment holes 202, for example, a set of alignment holes 202a, 202b, 202c, 202d, for registering the various layers of material and or masks, screens, stencils and the like utilized in the fabrication of modules 100, 100'. Dielectric layer 120 is preferably stenciled or screen printed onto the metal panel 200, for example, utilizing the stencil or mask panel 300 shown in FIGURE 10 which includes an 18 by 20 array of repeating patterns 304 of openings 330 corresponding to via holes 130. Dielectric layer 120 can also be applied by other conventional methods, such as film lamination, liquid spinning, paste screening and paste draw down methods. Stencil 300 includes a set of relational alignment holes
302, i.e. 302a, 302b, 302c, 302d, in the exact same pattern as are alignment holes 202 of metal panel 200 and a set of fiducial marks 306, i.e. 306a, 306b, 306c, for further facilitating alignment of stencil 300. An expanded view of a portion of FIGURE 10 is shown in FIGURE 10A in which ones of the pattern 304 of openings 330 are visible. The relative positions of the set of alignment holes 302, the patterns 304 of openings
330 and the fiducial marks 306 are in a predetermined positional relationship. Dielectric layer 120 is preferably of a material that is relatively high in viscosity and thixotropic index, and should preferably contain at least 50% solids so that layer 120 may be deposited with suitable thickness. For example, dielectric layer 120 typically has a wet thickness of about 150 μm (about 6 mils) corresponding to a dry thickness after B-staging of about 100 μ (about 4 mils). Both thermoplastic and thermosetting adhesives may be employed for dielectric layer 120, and should preferably have good rigidity and toughness, for example, as exhibited by adhesives having a modulus of elasticity over about 35,000 kg/m2 (about 500,000 psi) and an elongation in the range of 3 - 30% when cured. Suitable adhesives will not be adversely affected by exposure to the etching and plating chemicals and other
chemicals, and to the process environments, utilized in processing operations subsequent to application of the adhesives, whether the adhesive is in its dried or B- staged state or in its cured state at the time of such exposure. Suitable adhesives for dielectric layer 130 includes types LESP7670-SC or LESP7450-SC fast-curing thermosetting epoxy adhesive in liquid form, available from Al Technology located in
Princeton, New Jersey, also available as types ESP7670-SC and ESP7450-SC fast- curing thermosetting epoxy adhesives in paste form, and types LESP7675 and ESP7675 thermosetting epoxy adhesives.
Screened dielectric layer 120 is dried (or B-staged) at an elevated temperature of about 60 - 80 °C to remove the solvent from the deposited adhesive, and is then cured at an elevated temperature in the range of about 80 -150 °C. Curing is typically performed at a temperature of about 100 °C for about 60 minutes, but may be performed at a relatively low temperature of about 80 °C for several hours, or at a relatively higher temperature of about 150 °C for a few minutes. Via holes 130 in dielectric layer 120 typically are of about 50 - 500μm (about
2 - 20 mils) diameter, and more usually of about 125 - 250 μm (about 5 - 10 mils) diameter, and are formed in the screen printing of dielectric layer 120 or, where layer 120 is laminated to copper layer 110, are formed by die cutting, laser drilling photo- etching or other suitable method, either before or after the lamination of metal layer 110 and dielectric layer 120. A stencil or mask 300 as shown in FIGURES 10 and
10A may be utilized in forming dielectric layer 120 either by directly printing dielectric adhesive onto metal layer 110 or by printing dielectric adhesive onto a sheet of release liner, B-staging the adhesive to dryness, and then transferring the sheet of dielectric material 120 and laminating it to metal layer 110 in registration predetermined by the positional relationship of the alignment holes 202 and 302 of metal sheet 200 and of dielectric layer 120, respectively.
Copper is plated onto the exposed sites on copper layer 110 that are at the bottoms of via holes 130 to build up via conductors 132, and copper layer 110 is patterned to create gaps that define the external contacts 114 of module 100, 100'. FIGURE 11 shows a mask pattern 400 for an 18 by 20 array of repeating patterns 414 of contacts 1 14, each of which is in predetermined positional relationship with
alignment holes 402, i.e. 402a, 402b, 402c, 402d, and fiducial marks 406, i.e. 406a, 406b, 406c. The relative positions of the set of alignment holes 402, the patterns 414 of contacts 114 and the fiducial marks 406 are in the same predetermined positional relationship as are alignment holes 302, patterns 304 and fiducial marks 306 of stencil 300. In the expanded view of a portion of stencil 300 of FIGURE 11 A is shown a detail view of the pattern 414 of contacts 114. The generally rectangular pattern 414 often contacts 114 is about 11 mm by 12.5 mm (about 0.435 inch by 0.492 inch) with gaps 116 of about 0.25 mm (about 0.01 inch) between the contacts 114, which is the pattern of International Standard ISO-7816-2 entitled "Identification Cards — Integrated Circuit(s) Cards With Contacts" issued by the International Organization for Standardization, and available in the United States from the American National Standards Institute (ANSI) located in New York, New York.
The panel of modules 100 may now be excised or singulated into individual modules 100 of the sort shown in FIGURE 6, or may be further processed by applying a suitable insulating adhesive 150 to overcoat and/or surround electronic device 140 to obtain a panel of modules 100 of the sort shown in FIGURE 7. Any adhesive having suitable leveling characteristics to provide a relatively flat surface may be employed. One suitable adhesive is type MB7060 or MB7060-W thermoplastic electrically- insulating adhesive available from Al Technology, which has high flow at a melt temperature of about 65 - 75 °C and bonds well to common card materials such as
PVC with good resistance and insensitivity to moisture. Encapsulating adhesive 150 may be applied by conventional methods such as roll coating screen printing, stenciling and the like, or may be applied by laminating a sheet of dried or B-staged adhesive to the panel of modules 100. Typically, the thickness of the adhesive layer 150 is about the same as the height of electronic device 140, typically about 250 - 500 μm (about 10 - 20 mils) to form a panel of modules 100 having a slightly greater thickness, typically about 350 -600 μm (about 14 - 24 mils). However, a slightly greater yet thickness of adhesive 150, typically about 250 - 500 μm (about 10 - 20 mils) thicker than the height of electronic device 140, is desirable so as to cover electronic device 140 with encapsulating adhesive 150 where such adhesive is to be employed to also secure module 100 into the next level article. It is noted that this
latter arrangement offers the advantage that a simple single-level cavity is suitable to receive and hold module 100, rather the more complex and more expensive multilevel cavity that is required for conventional modules. In addition, although modules 100, 100' fabricated as described have a substantially planar adhesive layer 150 surface that is substantially parallel to the plane in which contacts 114 lie, modules
100, 100 may be employed even where such planarity and parallelism is lacking because the high melt flow characteristic of adhesive layer 150 tends to level out imperfections and tolerances when modules 100, 100' are inserted into cavities of the next-level articles in which they are utilized. The panel of modules 100 is singulated into separate individual modules 100 by any suitable and convenient method, such as die cutting or other cutting device, or by laser cutting, stamping and rotary die cutting. Where the adhesive employed in layer 120 is a high-strength adhesive, it is preferred that the high-strength adhesive be only dried or B-staged during the fabrication of the panel and that the panel be singulated into individual modules prior to curing the adhesive. This is desirable because the adhesive is much easier to cut before curing and is much more difficult to cut after curing which increases its strength many times, e.g., more than 100 times for a high-strength adhesive such as Al Technology type ESP7670-SC or LESP7670-SC. Al Technology types ESP7675 or LESP7675 may also be utilized. In the example of FIGURES 9 - 11 , an exemplary pattern of eight via holes
130 and via conductors 132 arranged in two rows of four via holes 130 each are shown, and an exemplary pattern 414 often contacts 114 are shown, only eight of which contacts 114 have via conductors 132 associated therewith, i.e. the eight via conductors 132 are associated with the two rows of four contacts 114 along the longer edges of pattern 414 and the two central contacts 414 along the shorter edges thereof are not connected in this example. It is understood that greater and lesser numbers of contacts and other patterns of contacts, and greater or lesser numbers of via holes 130 and via conductors 132 and other patterns thereof, may also be employed.
In addition, panels of modules 100 may be processed in continuous fashion by abutting the panels and providing sprocket drive holes therein and a sprocket drive mechanism or by forming modules 100 on a continuous web or strip of dielectric
substrate 120 material or metal foil 200. In such case, dielectric adhesive is applied, electroplating and photo-etching is performed, conductive adhesive is deposited continuously as the panels, web or strip, as the case may be, passes respective stations performing such operations. Any of the following three processes may be utilized to the end of making a circuit substrate of module 100, 100'. In a first of the processes, a first photoresist or other suitable masking resin is applied, selectively exposed as through a mask to form selective cross-links, and developed to define the pattern of contact pads 114 of the individual modules for subsequent metallization. A layer 112 of nickel, or other suitable passivating metal, is deposited onto contacts 114 and onto the via sites at the bottoms of via holes 130, typically to a thickness of a few microns (i.e. micrometers) such as by electrolytic or electroless plating. In addition, the plating of the nickel onto the via sites should be of sufficient thickness to fill via holes 130 with metal so as to be at or slightly above the surface of dielectric layer 120, thereby forming via conductors 132. This may be by plating nickel to the necessary thickness, or by plating copper onto the via sites, such as by electrolytic plating, to fill via holes 130 with metal to form via conductors 132 and then plating a layer 134 of nickel thereon. Preferably the nickel layers 112, 134 on contacts 114 and via conductors 132 are finished with a flash or electroplate of gold or palladium or other precious metal for reduced electrical resistance, unless satisfactory electrical contact can be obtained and maintained with the nickel layer 112, 134 alone. The first photoresist is then stripped away and a second photoresist is applied to metal layer 110 to cover the contacts 114, and is exposed and developed to define the areas of metal layer 110 to be etched away to provide gaps 116 between contacts 114. The exposed vias 132, 134 extending from dielectric layer 130 may also be masked. Metal layer 110 is then etched or stripped chemically to leave the pattern of contacts 114. Alternatively, the first photoresist may be left in place until after the photo-etching of metal layer 110, and then both the first and second photoresists maybe removed. Thus, a module 100, 100' circuit substrate of metal layer 110 and dielectric layer 120 having larger contacts 114 on one side thereof for making contact with a card reader and having smaller contacts 132,
134 on the other side thereof for making connection to an electronic device 140 is
provided.
In a second of the processes, a photoresist is applied to metal layer 110 to cover the areas of metal layer 110 that will be contacts 114, and is exposed and developed to define the metal to be etched away to provide gaps 116 between contacts 114. The exposed via holes 130 in dielectric layer 130 may also be masked to prevent etching of the via sites at the bottom thereof on metal layer 110. After the photoresist is exposed and developed, metal layer 110 is then etched or stripped chemically to leave the pattern of contacts 114 and then the photoresist is stripped away. A layer 112 of nickel, or other suitable passivating metal, is deposited onto contacts 114 and onto the via sites at the bottoms of via holes 130, typically to a thickness of a few microns (i.e. micrometers) such as by electrolytic or electroless plating. In addition, the plating of the nickel onto the via sites should be of sufficient thickness to fill via holes 130 with metal so as to be at or slightly above the surface of dielectric layer 120, thereby forming via conductors 132. This may be by plating nickel to the necessary thickness, or by plating copper onto the via sites, such as by electrolytic plating, to fill via holes 130 with metal forming via conductors 132 and then plating a layer 134 of nickel thereon. Preferably the nickel layers 112, 134 on contacts 114 and via conductors 132 are finished with a flash of gold or palladium or other precious metal for reduced electrical resistance, unless satisfactory electrical contact can be obtained and maintained with the nickel layer 112, 134 alone. It is noted that where via conductors 132 are built up of deposited copper, the nickel finish 112, 134 on contacts 114 and on via contacts 132 may be deposited at the same time and after the copper is deposited. Thus, a module 100, 100' circuit substrate of metal layer 110 and dielectric layer 120 having larger contacts 114 on one side thereof for making contact with a card reader and having smaller contacts 132, 134 on the other side thereof for making connection to an electronic device 140 is provided.
In a third of the processes, a photoresist or other suitable masking resin is applied to exposed metal layer 110, but is not exposed or developed at this time. Copper is then plated onto the via sites at the bottom of via holes 130 of sufficient thickness to fill via holes 130 with copper so as to be at or slightly above the surface of dielectric layer 120, thereby forming via conductors 132. The photoresist is then
exposed and developed to define the pattern of contact pads 114 of an individual module, i.e. to define the areas of metal layer 110 that will remain to provide contacts 114. A layer 112, 134 of nickel, or other suitable passivating metal, is deposited onto contacts 114 and onto via conductors 132, typically to a thickness of a few microns (i.e. micrometers) such as by electrolytic or electroless plating. Preferably the nickel layers 112, 134 on contacts 114 and via conductors 132 are finished with a flash or electroplate of gold or palladium or other precious metal for reduced electrical resistance, unless satisfactory electrical contact can be obtained and maintained with the nickel layer alone. The photoresist is then stripped away and a suitable solution is applied to preferentially etch metal layer 110 chemically to remove the uncovered copper areas, but leave the pattern of contacts 114 which are protected by the nickel or nickel/gold layers that are unaffected by the preferential etching solution. Alternatively, a second photoresist can be applied, exposed and developed to protect contacts 114 and via conductors 132, 134 against etching. Thus, a module 100, 100' circuit substrate of metal layer 110 and dielectric layer 120 having larger contacts 114 on one side thereof for making contact with a card reader and having smaller contacts 132, 134 on the other side thereof for making connection to an electronic device 140 is provided.
Alternatively, via conductors 132, 134 may be built up of an electrically- conductive adhesive deposited onto metal layer 110, preferably over a thin layer of nickel, gold or other suitable passivating metal deposited on the via sites on metal layer 110, for example, at the bottoms of via holes 130.
Connecting bumps 144 are preferably directly deposited as by screen or mask printing onto the contact pads 142 of electronic device 140 or onto the contacts 114 of the circuit substrate of module 100, 100'. The preferred material is a flexible electrically-conductive adhesive having a high thixotropic index which facilitates precise deposition. Suitable electrically-conductive adhesives include types PSS8090 and PSS8150 thermoplastic polymer adhesives and type ESS8450 thermosetting polymer adhesives in paste form, also available from Al Technology. Connecting adhesive bumps 144 are printed with a wet thickness of about 50 - 100 μm (about 2-4 mils), and electronic device 140 may be attached thereto while the adhesive is still
wet. The adhesive is then dried at an elevated temperature of about 60 - 80 °C for about 30 - 60 minutes to form a satisfactory electrical and mechanical connection and bond between contacts 142 of electronic device 140 and via contacts 132, 134 of module 100, 100'. Alternatively, bumps 144 may be solder bumps. To further strengthen the attachment of electronic device 140, an underfill of a low viscosity, non-thixotropic, and therefore, high flow, adhesive may be employed. Suitable underfill adhesives include type MEE7650 flexible thermosetting insulating adhesive and type MEE7660 high-strength thermosetting adhesive available from Al Technology, which are cured at a temperature of about 80 - 150 °C similar to the type LESP7675 adhesive employed in dielectric layer 120 as described above.
It is noted that module 100, 100' is suitable for utilization in many different kinds and types of next-level articles, such as smart cards, identification tags, credit and money cards and the like made by conventional and new methods. Such suitable articles include, for example, those described in U.S. Patent Application Serial Number 09/ (AI-TECH- 11 ) entitled ""Article Having An Embedded
Electronic Device, And Method Of Making Same" and in U.S. Patent Application
Serial Number 09/ (AI-TECH- 14) entitled "Wireless Article Including A
Plural-Turn Antenna" both of which being filed by Kevin K-T Chung on even date herewith, which applications are hereby incorporated herein by reference in their entireties.
Completed modules 100, 100' may, for convenience, be stored in a waffle package 500 shown in FIGURE 12 which has an 18 by 20 array of receptacles 504 each of a size to receive a module 100, 100'. For facilitating automated operations, such as pick-and-place equipment picking modules 100, 100' from receptacles 504 of waffle package 500 and placing them into proper position on cards, tags or other next- level articles, package 500 includes a set of relational alignment holes 502, preferably in like positional relationship to the alignment holes 202, 302 and 402 of metal panel 200, via stencil 300 and contact stencil 400, respectively.
FIGURE 13 is a side cross-sectional view of a module 100" including plural electronic devices 140, 170, 180, 190 connected by conductors 160, but otherwise similar to contact module 100 of FIGURE 6 in construction and materials, in
accordance with the present invention. Electronic devices 140, 170, 180, 190 may be integrated circuits, diodes, transistors, resistors, capacitors, inductors, or networks of such components, or any combination thereof. Contacts 114a, 114b, dielectric layer 120, conductive vias 142a, 142b and electronic device 140 are as described above. In like manner to conductive vias 142a, 142b, conductive vias 147, 147 and 149 are built up on the metal layer 110 by depositing electrically-conductive adhesive (e.g., types ESS8450 and PSS8150 available from Al Technology) or building up metal (e.g., copper, nickel or aluminum) thereon and are provided for connecting electronic devices 170, 180, 190, respectively, in circuit, and are fabricated substantially contemporaneously with conductive vias 142a, 142b. When metal layer 110 is removed as by photo-etching to leave the pattern of contacts 114a, 114b, the metal of layer 110 proximate conductive vias 147, 148, 149 is substantially removed leaving conductive vias 147, 148, 149 flush with the surface of dielectric layer 120 or projecting slightly therefrom. A layer of oxidation-resistant nickel-gold is deposited relatively heavily on the exposed portions of contacts 114a, 114b, and relatively lightly on the exposed portions of conductive vias 132a, 132b, 147. 148, 149.
Conductors 160 are preferably conductive adhesive (such as type PSS8150 or type ESS8450) deposited on dielectric layer 120 (such as type ESP7450 insulating adhesive) and contacting conductive vias 132a, 132b, 147, 148, 149 for connecting them in circuit. The respective contacts of electronic devices 140, 170, 180, 190 are attached to conductive vias 132a, 132b, 147, 148, 149 by bumps 144, 174, 184, 194 of conductive material such as solder and electrically-conductive adhesive, which may be applied either to the ends of vias 123a, 132b, 147, 148, 149 or to the contacts of electronic devices 140, 170, 180, 190. It is noted that either solder bumps or conductive adhesive bumps, or both, may be employed on a given module 100", and in fact it may be preferable to employ flexible conductive adhesive bumps for connecting an integrated circuit device and solder bumps for connecting resistors, capacitors, and the like. Conductive bumps 144, 174, 184, 194 may be about 70 μm (about 3 mils) diameter, or other suitable size. Suitable underfill may be utilized between devices 140, 170, 180, 190, if desired, to increase the strength of the bonding of devices 140, 170, 180, 190 to dielectric layer 120.
It is further noted that solder bumps can be employed with conductive vias and conductors formed of electrically-conductive adhesive that have been plated with a suitable metal, such as nickel, gold, nickel-gold and the like, as well as with metal conductive vias. Further, suitable insulating underfill may be utilized to strengthen the attachment of one or more of electronic devices 140, 170, 180, 190 as desired.
FIGURE 14 is an exploded side cross-sectional view of the contact module 100"of FIGURE 13 included in an article 600. Module 100" is laminated between two card blanks 610, 620 where article 600 is to be utilized as a credit card, debit card, smart card or the like, and may be laminated only to card blank 610 where it is to be utilized as an identification tag or the like. In either case, card blank 610 includes a thin layer 612 of high melt-flowable adhesive (e.g., an about 25μm thick (about 1 mil thick) layer of type MB7060 or type MB7100 adhesive) that serves to bond card blank 610 to module 100". Card blank 610 is of like thickness to contacts 114a, 114b, for example, about 75 m (about 3 mils) each, and has an aperture 614 therethrough into which contacts 114a, 114b fit so as to be exposed and substantially flush with or extending slightly above the surface of card blank 610. Dielectric layer 120 is preferably also of like thickness thereto. Module 100" is coated with a layer 150 of high melt-flowable adhesive (e.g., also of type MB7060 or type MB7100 adhesive) that is of sufficient thickness to encapsulate electronic devices 140, 170, 180, 190 to dielectric substrate 120 and also serves to attach card blank 620 to module 100". Card blank 620 is typically of like thickness to card blank 610 and contacts 114a, 114b, for example, about 75 μm (about 3 mils). Card blanks 610, 620 are of conventional materials, for example, of PVC or polyester, and the like.
The thickness of adhesive layer 150 is selected not only to cover electronic devices 140, 170, 180, 190, but to establish the overall thickness of article 600 at a desired dimension, such as the 0.785 mm (about 31 mil) thickness of standard credit cards, smart cards and the like. Thus an about 535- m (about 21-mil) thick layer 150 combines with the three 75-μm (3-mil) thicknesses of card blanks 610, 620 and of dielectric layer 120, plus the 25- m (1-mil) thick adhesive layer 612, for an overall thickness of about 0.785 mm (about 31 mils). Conveniently, these thicknesses are compatible with the height of electronic devices 140. 170, 180, 190, which are about
500 μm (about 20 mils) or less. The mounted height of each device should preferably be about 400 - 450 μm (about 16 - 18 mils) or less when connected by solder bumps and about 450 - 500 μm (about 18 - 20 mils) when connected by conductive adhesive bumps, which bumps are typically of 70-μm (3-mil) diameter. For example, a typical 405-μm (16-mil) thick electronic device attached by 75-μm (3-mil)conductive bumps has a height of about 480 μm (19 mils).
While the present invention has been described in terms of the foregoing exemplary embodiments, variations within the scope and spirit of the present invention as defined by the claims following will be apparent to those skilled in the art. For example, conductive vias could be formed by depositing a pattern of electrically-conductive adhesive onto metal contacts 114, either before or after dielectric adhesive layer 120 is deposited thereon, as by screen printing, stencil printing, mask printing or other suitable method. In addition, although electroless and electrolytic plating (electroplating) is preferred, other deposition methods such as chemical plating, immersion coating and the like may be utilized.
Claims
1. A module comprising: a pattern of metal contacts having a first and a second surface; a layer of dielectric adhesive on the first surface of said pattern of metal contacts and having at least two holes therethrough to the first surface of said metal contacts; at least two electrically-conductive vias substantially filling the holes in said dielectric adhesive layer and contacting the first surface of the metal contacts, each conductive via having an end distal from the first surface of said metal contacts; and at least one electronic device having electrical contacts connected to the distal end of said conductive vias.
2. The module of claim 1 wherein said conductive vias comprise metal deposited onto said metal contacts.
3. The module of claim 2 wherein said conductive vias and said metal contacts are formed of the same metal.
4. The module of claim 3 wherein said metal is selected from the group consisting of copper, aluminum, nickel, kovar, alloy 42, beryllium copper, brass, copper-based alloys, iron-based alloys, and combinations and alloys thereof, and laminates thereof.
5. The module of claim 4 further comprising a metal coating on the second surface of said metal contacts and on the distal end of said conductive vias, wherein said metal coating includes at least one of nickel, tin, silver, gold, platinum, palladium, nickel-palladium, nickel-gold, a combination thereof, and an alloy thereof.
6. The module of claim 2 wherein said metal of said conductive via is deposited by one of chemical plating, immersion coating, electrolytic plating, and electroless plating.
7. The module of claim 1 wherein said conductive vias comprise electrically- conductive adhesive deposited onto said metal contacts.
8. The module of claim 1 wherein said conductive vias are formed in said holes in said layer of dielectric adhesive.
9. The module of claim 1 wherein said electrically-conductive adhesive is a flexible adhesive.
10. The module of claim 1 wherein the contacts of said electronic device are connected to said conductive vias by a connection selected from the group consisting of electrically-conductive adhesive, solder and wire bonding.
11. The module of claim 1 wherein said electronic device is attached to said dielectric adhesive layer by an insulating adhesive underfill.
12. The module of claim 1 wherein said electronic device is encapsulated on said dielectric adhesive layer by a high melt flow adhesive.
13. The module of claim 1 wherein said electronic device is attached to said dielectric adhesive layer by an insulating adhesive underfill and is encapsulated on said dielectric adhesive layer by a high melt flow adhesive.
14. The module of claim 1 wherein said dielectric adhesive is a flexible dielectric adhesive. 64229
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15. A contact module including at least one electronic device comprising: a metal layer having a first and a second surface, said metal layer having opemngs therethrough defining a pattern of at least two metal contacts; a layer of dielectric adhesive on the first surface of said metal layer, said dielectric adhesive layer having at least two holes therethrough each to the first surface of one of said two metal contacts, respectively; at least two electrically-conductive vias substantially filling the two holes of said dielectric adhesive layer and contacting the respective first surfaces of the at least two metal contacts, each electrically-conductive via having an end distal from said metal layer; and means for connecting at least two contacts of the at least one electronic device each to a respective distal end of one of said electrically-conductive vias.
16. The contact module of claim 15 wherein said electrically-conductive vias comprise metal deposited onto said metal layer.
17. The contact module of claim 16 wherein said electrically-conductive vias and said metal layer are of the same metal selected from the group consisting of copper, aluminum, nickel, kovar, alloy 42, beryllium copper, brass, copper- based alloys, iron-based alloys, and combinations and alloys thereof, and laminates thereof.
18. The contact module of claim 16 wherein said deposited metal of said electrically-conductive vias is deposited by one of chemical plating, immersion coating, electrolytic plating, and electroless plating.
19. The contact module of claim 15 wherein said electrically-conductive vias comprise electrically-conductive adhesive deposited onto said metal layer. 64229
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20. The contact module of claim 15 further comprising a metal coating on the second surface of said metal contacts and on the distal end of said electrically- conductive vias, said metal coating including at least one of nickel, tin, silver, gold, platinum, palladium, nickel-palladium, nickel-gold, a combination thereof, and an alloy thereof.
21. The contact module of claim 15 wherein said electrically-conductive vias are formed in the holes in said layer of dielectric adhesive by depositing electrically-conductive adhesive therein.
22. The contact module of claim 15 wherein said electrically-conductive vias are formed in the holes in said layer of dielectric adhesive by depositing metal onto the first surface of said metal contacts therein.
23. The contact module of claim 15 wherein said means for connecting includes connections selected from the group consisting of electrically-conductive adhesive, solder and wire bonding.
24. The contact module of claim 15 further comprising an insulating adhesive underfill attaching said at least one electronic device to said dielectric adhesive layer.
25. The contact module of claim 15 further comprising a high melt flow adhesive encapsulating said electronic device on said dielectric adhesive layer.
26. The contact module of claim 15 further comprising an insulating adhesive underfill attaching said electronic device to said dielectric adhesive layer and a high melt flow adhesive encapsulating said electronic device on said dielectric adhesive layer. 64229
- 25 -
27. A method of making a module including an electronic device comprising: providing a sheet of electrical contact material having first and second surfaces; providing an electronic device having a pattern of contacts thereon; forming a pattern of electrically-conductive vias on the first surface of the sheet of electrical contact material, the pattern of electrically-conductive vias corresponding to the pattern of contacts of the electronic device; applying a layer of dielectric adhesive on the first surface of the sheet of electrical material except in locations corresponding to the electrically- conductive vias; patterning the sheet of electrical material to define a pattern of electrical contacts thereon, wherein ones of the electrical contacts are associated with at least corresponding ones of the electrically-conductive vias; and attaching the electronic device with the contacts of the electronic device electrically connected to corresponding electrically-conductive vias.
28. The method of claim 27 further comprising encapsulating the electronic device to the layer of dielectric adhesive.
29. The method of claim 28 wherein said encapsulating includes applying a high melt flow adhesive by one of roll coating, screen printing, stenciling and laminating.
30. The method of claim 27 wherein said forming a pattern of electrically- conductive vias precedes said applying a layer of dielectric adhesive.
31. The method of claim 27 wherein said applying a layer of dielectric adhesive precedes said forming a pattern of electrically-conductive vias. 64229
- 26 -
32. The method of claim 27 wherein said forming a pattern of electrically- conductive vias precedes said patterning the sheet of electrical contact material.
33. The method of claim 27 wherein said patterning the sheet of electrical contact material precedes said forming a pattern of electrically-conductive vias.
34. The method of claim 27 wherein said forming a pattern of electrically- conductive vias includes building up metal vias on the first surface of the sheet of electrical contact material.
35. The method of claim 34 wherein said building up includes one of chemical plating, immersion coating, electrolytic plating, and electroless plating.
36. The method of claim 27 wherein said forming a pattern of electrically- conductive vias includes depositing electrically-conductive adhesive vias on the first surface of the sheet of electrical contact material.
37. The method of claim 36 wherein said depositing includes one of roll coating, screen printing, stenciling, mask printing, ink-jet printing and laminating.
38. The method of claim 27 wherein said applying a layer of dielectric adhesive includes applying an electrically-insulating adhesive by one of roll coating, screen printing, stenciling and laminating.
39. The method of claim 27 wherein said patterning the sheet of electrical contact material includes patterning a photoresist on the sheet of electrical contact material and etching the sheet of electrical contact material. 64229
- 27 -
40. The method of claim 27 further comprising coating at least one of the pattern of electrical contacts and the electrically-conductive vias with a metal including at least one of nickel, tin, silver, gold, platinum, palladium, nickel- palladium, nickel-gold, a combination thereof, and an alloy thereof.
41. The method of claim 27 wherein said attaching the electronic device includes applying an electrically-conductive adhesive to the electrically-conductive vias or to the contacts of the electronic device, and positioning the electronic device with corresponding ones of the electrically-conductive vias and contacts of the electronic device joined together by the electrically-conductive adhesive.
42. The article formed by the method of claim 27.
Applications Claiming Priority (10)
Application Number | Priority Date | Filing Date | Title |
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US12949799P | 1999-04-15 | 1999-04-15 | |
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US13465699P | 1999-05-18 | 1999-05-18 | |
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US14134499P | 1999-06-28 | 1999-06-28 | |
US60/141,344 | 1999-06-28 | ||
US09/412,052 | 1999-10-04 | ||
US09/412,052 US6288905B1 (en) | 1999-04-15 | 1999-10-04 | Contact module, as for a smart card, and method for making same |
Publications (1)
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WO2000064229A1 true WO2000064229A1 (en) | 2000-10-26 |
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Family Applications (1)
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PCT/US2000/009144 WO2000064229A1 (en) | 1999-04-15 | 2000-04-06 | Contact module, as for a smart card, and method for making same |
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US (1) | US6288905B1 (en) |
WO (1) | WO2000064229A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7578053B2 (en) | 2004-12-03 | 2009-08-25 | Hallys Corporation | Interposer bonding device |
US8025086B2 (en) | 2005-04-06 | 2011-09-27 | Hallys Corporation | Electronic component manufacturing apparatus |
US8373067B2 (en) | 2007-07-30 | 2013-02-12 | Pilkington Automotive Deutschland Gmbh | Electrical connector |
EP2731058A1 (en) * | 2012-11-13 | 2014-05-14 | Gemalto SA | Method for manufacturing a module with an electronic chip protected against electrostatic charges |
CN104102941A (en) * | 2013-04-11 | 2014-10-15 | 德昌电机(深圳)有限公司 | Smart card, identity identification card, bank card, smart card touch panel and surface anti-oxidation method |
Families Citing this family (75)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6429120B1 (en) | 2000-01-18 | 2002-08-06 | Micron Technology, Inc. | Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals |
US6914196B2 (en) * | 1998-01-09 | 2005-07-05 | Samsung Electronics Co., Ltd. | Reel-deployed printed circuit board |
US6509590B1 (en) * | 1998-07-20 | 2003-01-21 | Micron Technology, Inc. | Aluminum-beryllium alloys for air bridges |
KR20000057810A (en) * | 1999-01-28 | 2000-09-25 | 가나이 쓰토무 | Semiconductor device |
JP2000332369A (en) * | 1999-05-25 | 2000-11-30 | Mitsui Mining & Smelting Co Ltd | Printed-circuit board and its manufacture |
SE515856C2 (en) * | 1999-05-19 | 2001-10-22 | Ericsson Telefon Ab L M | Carrier for electronic components |
US6492717B1 (en) * | 1999-08-03 | 2002-12-10 | Motorola, Inc. | Smart card module and method of assembling the same |
FI112288B (en) * | 2000-01-17 | 2003-11-14 | Rafsec Oy | Procedure for producing an input path for smart labels |
US6420262B1 (en) | 2000-01-18 | 2002-07-16 | Micron Technology, Inc. | Structures and methods to enhance copper metallization |
US6581828B1 (en) * | 2000-02-10 | 2003-06-24 | Ncr Corporation | Electronic price label and assembly method |
FI112287B (en) * | 2000-03-31 | 2003-11-14 | Rafsec Oy | Procedure for producing product sensor and product sensor |
EP1225538B1 (en) * | 2000-05-12 | 2006-09-13 | Dai Nippon Printing Co., Ltd. | Noncontact data carrier |
FI111881B (en) * | 2000-06-06 | 2003-09-30 | Rafsec Oy | A smart card web and a method for making it |
US6734534B1 (en) | 2000-08-16 | 2004-05-11 | Intel Corporation | Microelectronic substrate with integrated devices |
US20020020898A1 (en) * | 2000-08-16 | 2002-02-21 | Vu Quat T. | Microelectronic substrates with integrated devices |
US6762502B1 (en) * | 2000-08-31 | 2004-07-13 | Micron Technology, Inc. | Semiconductor device packages including a plurality of layers substantially encapsulating leads thereof |
JP2002109491A (en) * | 2000-09-29 | 2002-04-12 | Sony Corp | Ic card and method for preparing the same |
US20020070443A1 (en) * | 2000-12-08 | 2002-06-13 | Xiao-Chun Mu | Microelectronic package having an integrated heat sink and build-up layers |
FI112121B (en) * | 2000-12-11 | 2003-10-31 | Rafsec Oy | Smart sticker web, process for making it, process for making a carrier web, and component of a smart sticker on a smart sticker web |
FI111039B (en) * | 2001-04-06 | 2003-05-15 | Rafsec Oy | Smart card and procedure for its preparation |
FI112550B (en) * | 2001-05-31 | 2003-12-15 | Rafsec Oy | Smart label and smart label path |
FI117331B (en) * | 2001-07-04 | 2006-09-15 | Rafsec Oy | Method of manufacturing an injection molded product |
US6604686B1 (en) * | 2001-10-09 | 2003-08-12 | Vahid Taban | High speed system for embedding wire antennas in an array of smart cards |
FI119401B (en) * | 2001-12-21 | 2008-10-31 | Upm Raflatac Oy | Smart label web and process for its manufacture |
TW584950B (en) | 2001-12-31 | 2004-04-21 | Megic Corp | Chip packaging structure and process thereof |
US6673698B1 (en) | 2002-01-19 | 2004-01-06 | Megic Corporation | Thin film semiconductor package utilizing a glass substrate with composite polymer/metal interconnect layers |
TW517361B (en) * | 2001-12-31 | 2003-01-11 | Megic Corp | Chip package structure and its manufacture process |
TW544882B (en) | 2001-12-31 | 2003-08-01 | Megic Corp | Chip package structure and process thereof |
TW503496B (en) | 2001-12-31 | 2002-09-21 | Megic Corp | Chip packaging structure and manufacturing process of the same |
US6969914B2 (en) * | 2002-08-29 | 2005-11-29 | Micron Technology, Inc. | Electronic device package |
US20040135828A1 (en) * | 2003-01-15 | 2004-07-15 | Schmitt Stephen E. | Printer and method for printing an item with a high durability and/or resolution image |
US6981767B2 (en) * | 2003-01-15 | 2006-01-03 | Ssgii, Inc. | Printed item having an image with a high durability and/or resolution |
TW556452B (en) * | 2003-01-30 | 2003-10-01 | Phoenix Prec Technology Corp | Integrated storage plate with embedded passive components and method for fabricating electronic device with the plate |
US6921860B2 (en) | 2003-03-18 | 2005-07-26 | Micron Technology, Inc. | Microelectronic component assemblies having exposed contacts |
FI20031341A (en) | 2003-09-18 | 2005-03-19 | Imbera Electronics Oy | Method for manufacturing an electronic module |
US7459781B2 (en) * | 2003-12-03 | 2008-12-02 | Wen-Kun Yang | Fan out type wafer level package structure and method of the same |
US7045472B2 (en) * | 2004-04-28 | 2006-05-16 | International Business Machines Corporation | Method and apparatus for selectively altering dielectric properties of localized semiconductor device regions |
US7255782B2 (en) * | 2004-04-30 | 2007-08-14 | Kenneth Crouse | Selective catalytic activation of non-conductive substrates |
US20050241951A1 (en) * | 2004-04-30 | 2005-11-03 | Kenneth Crouse | Selective catalytic activation of non-conductive substrates |
KR100690960B1 (en) * | 2004-06-24 | 2007-03-09 | 삼성전자주식회사 | Manufacturing method having screen printing process for semiconductor chip package |
US8695881B2 (en) * | 2004-06-30 | 2014-04-15 | Nxp B.V. | Chip card for insertion into a holder |
US7541265B2 (en) * | 2005-01-10 | 2009-06-02 | Endicott Interconnect Technologies, Inc. | Capacitor material for use in circuitized substrates, circuitized substrate utilizing same, method of making said circuitized substrate, and information handling system utilizing said circuitized substrate |
US7743963B1 (en) | 2005-03-01 | 2010-06-29 | Amerasia International Technology, Inc. | Solderable lid or cover for an electronic circuit |
FI119714B (en) | 2005-06-16 | 2009-02-13 | Imbera Electronics Oy | Circuit board structure and method for manufacturing a circuit board structure |
TW200721426A (en) * | 2005-07-25 | 2007-06-01 | Koninkl Philips Electronics Nv | Air cavity package for flip-chip |
US7849591B2 (en) * | 2005-10-14 | 2010-12-14 | Fujikura Ltd. | Method of manufacturing a printed wiring board |
DE502005007956D1 (en) * | 2005-11-14 | 2009-10-01 | Tyco Electronics Amp Gmbh | Smartcard body, smartcard and manufacturing process |
FI20051228L (en) * | 2005-12-01 | 2007-07-27 | Zipic Oy | Component box with microcircuit |
US7551448B2 (en) * | 2006-01-31 | 2009-06-23 | Cryovac, Inc. | Electronic device having improved electrical connection |
TWI278979B (en) * | 2006-02-17 | 2007-04-11 | Taiwan Solutions Systems Corp | Chip package substrate and manufacturing method thereof |
DE102006030581B3 (en) | 2006-07-03 | 2008-02-21 | Infineon Technologies Ag | Method for producing a component |
US20080136887A1 (en) * | 2006-12-11 | 2008-06-12 | Schmitt Stephen E | Printed item having an image with a high durability and/or resolution |
US9466545B1 (en) | 2007-02-21 | 2016-10-11 | Amkor Technology, Inc. | Semiconductor package in package |
KR100891330B1 (en) * | 2007-02-21 | 2009-03-31 | 삼성전자주식회사 | Semiconductor package apparatus, Manufacturing method of the semiconductor package apparatus, Card apparatus having the semiconductor package apparatus and Manufacturing method of the card apparatus having the semiconductor package apparatus |
US20080217759A1 (en) * | 2007-03-06 | 2008-09-11 | Taiwan Solutions Systems Corp. | Chip package substrate and structure thereof |
EP2138962B1 (en) * | 2007-04-26 | 2012-01-04 | Murata Manufacturing Co. Ltd. | Wireless ic device |
US7707706B2 (en) * | 2007-06-29 | 2010-05-04 | Ruhlamat Gmbh | Method and arrangement for producing a smart card |
DE102007061161A1 (en) | 2007-12-17 | 2009-06-18 | Advanced Chip Engineering Technology Inc. | Electronic packing structure e.g. electronic three dimensional package, for manufacturing e.g. micro electronic, signal contact formed on side of structure connected with contact to form canal between contact and inner switching circuit |
US7671436B2 (en) * | 2008-05-02 | 2010-03-02 | Agere Systems Inc. | Electronic packages |
KR20090117237A (en) * | 2008-05-09 | 2009-11-12 | 삼성전기주식회사 | Electronic components embedded pcb and the method for manufacturing thereof |
DE102008041873A1 (en) * | 2008-09-08 | 2010-03-11 | Biotronik Crm Patent Ag | LTCC substrate structure and method of making the same |
US8294276B1 (en) * | 2010-05-27 | 2012-10-23 | Amkor Technology, Inc. | Semiconductor device and fabricating method thereof |
US9443185B2 (en) * | 2012-04-27 | 2016-09-13 | Vallourec Oil And Gas France | Rugged RFID tags |
JP6107195B2 (en) * | 2013-02-12 | 2017-04-05 | 日本軽金属株式会社 | Method for manufacturing aluminum conductive member |
EP2811428A1 (en) * | 2013-06-07 | 2014-12-10 | Gemalto SA | Method for manufacturing a radio frequency device with maintaining of anisotropic connection |
US20150035163A1 (en) * | 2013-08-02 | 2015-02-05 | Siliconware Precision Industries Co., Ltd. | Semiconductor package and method of fabricating the same |
USD776070S1 (en) * | 2014-03-18 | 2017-01-10 | Sony Corporation | Non-contact type data carrier |
CN108292371A (en) * | 2015-08-06 | 2018-07-17 | 薄膜电子有限公司 | Wireless tag with printed wiring column, and production and preparation method thereof |
US9721812B2 (en) * | 2015-11-20 | 2017-08-01 | International Business Machines Corporation | Optical device with precoated underfill |
CN106096703B (en) * | 2016-06-03 | 2020-08-14 | 上海伊诺尔信息电子有限公司 | Gapless contact smart card chip module, smart card and manufacturing method thereof |
CN106409698A (en) * | 2016-11-11 | 2017-02-15 | 上海伊诺尔信息技术有限公司 | Smart card module manufacture method, smart card module, smart card and strip |
CN106650903A (en) * | 2017-01-20 | 2017-05-10 | 上海伊诺尔信息技术有限公司 | All-aluminum intelligent card module and manufacturing method thereof |
US10962873B2 (en) | 2017-09-29 | 2021-03-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Extreme ultraviolet mask and method of manufacturing the same |
US10919326B2 (en) | 2018-07-03 | 2021-02-16 | Apple Inc. | Controlled ablation and surface modification for marking an electronic device |
US11106961B2 (en) * | 2019-10-09 | 2021-08-31 | Beauiiful Card Corporation | Mini smart card and method of manufacturing the same |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4874721A (en) * | 1985-11-11 | 1989-10-17 | Nec Corporation | Method of manufacturing a multichip package with increased adhesive strength |
US5073840A (en) * | 1988-10-06 | 1991-12-17 | Microlithics Corporation | Circuit board with coated metal support structure and method for making same |
US5147210A (en) * | 1988-03-03 | 1992-09-15 | Western Digital Corporation | Polymer film interconnect |
US5450290A (en) * | 1993-02-01 | 1995-09-12 | International Business Machines Corporation | Printed circuit board with aligned connections and method of making same |
US5740606A (en) * | 1995-11-03 | 1998-04-21 | Schlumberger Industries | Method of manufacturing a set of electronic modules for electronic memory cards |
US5989936A (en) * | 1994-07-07 | 1999-11-23 | Tessera, Inc. | Microelectronic assembly fabrication with terminal formation from a conductive layer |
US5994168A (en) * | 1997-02-25 | 1999-11-30 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor device |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4498122A (en) * | 1982-12-29 | 1985-02-05 | At&T Bell Laboratories | High-speed, high pin-out LSI chip package |
US4628406A (en) * | 1985-05-20 | 1986-12-09 | Tektronix, Inc. | Method of packaging integrated circuit chips, and integrated circuit package |
US5399903A (en) * | 1990-08-15 | 1995-03-21 | Lsi Logic Corporation | Semiconductor device having an universal die size inner lead layout |
US5514475A (en) * | 1993-01-22 | 1996-05-07 | Sumitomo Metal Industries, Ltd. | Heat-resistant electrical insulating layer |
JPH0722741A (en) * | 1993-07-01 | 1995-01-24 | Japan Gore Tex Inc | Coverlay film and coverlay film covering circuit board |
JPH0737049A (en) * | 1993-07-23 | 1995-02-07 | Toshiba Corp | External storage |
US5430441A (en) | 1993-10-12 | 1995-07-04 | Motorola, Inc. | Transponding tag and method |
TW272311B (en) * | 1994-01-12 | 1996-03-11 | At & T Corp | |
FR2716281B1 (en) | 1994-02-14 | 1996-05-03 | Gemplus Card Int | Method of manufacturing a contactless card. |
US5751256A (en) | 1994-03-04 | 1998-05-12 | Flexcon Company Inc. | Resonant tag labels and method of making same |
DE4416697A1 (en) | 1994-05-11 | 1995-11-16 | Giesecke & Devrient Gmbh | Data carrier with integrated circuit |
US5574470A (en) | 1994-09-30 | 1996-11-12 | Palomar Technologies Corporation | Radio frequency identification transponder apparatus and method |
US5463404A (en) | 1994-09-30 | 1995-10-31 | E-Systems, Inc. | Tuned microstrip antenna and method for tuning |
JP3474937B2 (en) * | 1994-10-07 | 2003-12-08 | 株式会社東芝 | Method of manufacturing wiring board for mounting and method of manufacturing semiconductor package |
US5677246A (en) * | 1994-11-29 | 1997-10-14 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor devices |
US6016598A (en) * | 1995-02-13 | 2000-01-25 | Akzo Nobel N.V. | Method of manufacturing a multilayer printed wire board |
US5637920A (en) * | 1995-10-04 | 1997-06-10 | Lsi Logic Corporation | High contact density ball grid array package for flip-chips |
US5906042A (en) * | 1995-10-04 | 1999-05-25 | Prolinx Labs Corporation | Method and structure to interconnect traces of two conductive layers in a printed circuit board |
FR2747812B1 (en) | 1996-04-23 | 1998-05-22 | Solaic Sa | CONTACTLESS INTEGRATED CIRCUIT CARD WITH CONDUCTIVE POLYMER ANTENNA |
US6022761A (en) * | 1996-05-28 | 2000-02-08 | Motorola, Inc. | Method for coupling substrates and structure |
US5822856A (en) * | 1996-06-28 | 1998-10-20 | International Business Machines Corporation | Manufacturing circuit board assemblies having filled vias |
US6020220A (en) * | 1996-07-09 | 2000-02-01 | Tessera, Inc. | Compliant semiconductor chip assemblies and methods of making same |
JP3683996B2 (en) * | 1996-07-30 | 2005-08-17 | 株式会社東芝 | Semiconductor device and manufacturing method thereof |
TW398163B (en) * | 1996-10-09 | 2000-07-11 | Matsushita Electric Ind Co Ltd | The plate for heat transfer substrate and manufacturing method thereof, the heat-transfer substrate using such plate and manufacturing method thereof |
US5892661A (en) | 1996-10-31 | 1999-04-06 | Motorola, Inc. | Smartcard and method of making |
US5796590A (en) * | 1996-11-05 | 1998-08-18 | Micron Electronics, Inc. | Assembly aid for mounting packaged integrated circuit devices to printed circuit boards |
US6136733A (en) * | 1997-06-13 | 2000-10-24 | International Business Machines Corporation | Method for reducing coefficient of thermal expansion in chip attach packages |
US5909050A (en) | 1997-09-15 | 1999-06-01 | Microchip Technology Incorporated | Combination inductive coil and integrated circuit semiconductor chip in a single lead frame package and method therefor |
JP3638771B2 (en) * | 1997-12-22 | 2005-04-13 | 沖電気工業株式会社 | Semiconductor device |
US6111323A (en) * | 1997-12-30 | 2000-08-29 | International Business Machines Corporation | Reworkable thermoplastic encapsulant |
-
1999
- 1999-10-04 US US09/412,052 patent/US6288905B1/en not_active Expired - Fee Related
-
2000
- 2000-04-06 WO PCT/US2000/009144 patent/WO2000064229A1/en active Application Filing
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4874721A (en) * | 1985-11-11 | 1989-10-17 | Nec Corporation | Method of manufacturing a multichip package with increased adhesive strength |
US5147210A (en) * | 1988-03-03 | 1992-09-15 | Western Digital Corporation | Polymer film interconnect |
US5073840A (en) * | 1988-10-06 | 1991-12-17 | Microlithics Corporation | Circuit board with coated metal support structure and method for making same |
US5450290A (en) * | 1993-02-01 | 1995-09-12 | International Business Machines Corporation | Printed circuit board with aligned connections and method of making same |
US5989936A (en) * | 1994-07-07 | 1999-11-23 | Tessera, Inc. | Microelectronic assembly fabrication with terminal formation from a conductive layer |
US5740606A (en) * | 1995-11-03 | 1998-04-21 | Schlumberger Industries | Method of manufacturing a set of electronic modules for electronic memory cards |
US5994168A (en) * | 1997-02-25 | 1999-11-30 | Oki Electric Industry Co., Ltd. | Method of manufacturing semiconductor device |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7578053B2 (en) | 2004-12-03 | 2009-08-25 | Hallys Corporation | Interposer bonding device |
US8025086B2 (en) | 2005-04-06 | 2011-09-27 | Hallys Corporation | Electronic component manufacturing apparatus |
US8373067B2 (en) | 2007-07-30 | 2013-02-12 | Pilkington Automotive Deutschland Gmbh | Electrical connector |
EP2731058A1 (en) * | 2012-11-13 | 2014-05-14 | Gemalto SA | Method for manufacturing a module with an electronic chip protected against electrostatic charges |
WO2014075869A1 (en) * | 2012-11-13 | 2014-05-22 | Gemalto Sa | Method for manufacturing an anti-electrostatic charge electronic chip module |
CN104102941A (en) * | 2013-04-11 | 2014-10-15 | 德昌电机(深圳)有限公司 | Smart card, identity identification card, bank card, smart card touch panel and surface anti-oxidation method |
EP2790131A1 (en) * | 2013-04-11 | 2014-10-15 | Johnson Electric S.A. | Smart card contact pad with oxidation protection |
JP2014206978A (en) * | 2013-04-11 | 2014-10-30 | ジョンソン エレクトリック ソシエテ アノニム | Contact smart card |
US9251457B2 (en) | 2013-04-11 | 2016-02-02 | Johnson Electric S.A. | Contact smart card |
US9524459B2 (en) | 2013-04-11 | 2016-12-20 | Johnson Electric S.A. | Contact smart card |
EP3270328A1 (en) * | 2013-04-11 | 2018-01-17 | Johnson Electric S.A. | Improvements in or relating to contact smart cards |
CN104102941B (en) * | 2013-04-11 | 2023-10-13 | 德昌电机(深圳)有限公司 | Smart card, identity recognition card, bank card, smart card touch plate and surface oxidation resistance method |
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