WO2000058814A1

WO2000058814A1 - Supply of power to a periheral

Info

Publication number: WO2000058814A1
Application number: PCT/GB2000/001120
Authority: WO
Inventors: Michael Martin
Original assignee: Unilever Plc; Unilever Nv; Hindustan Lever Limited
Priority date: 1999-03-31
Filing date: 2000-03-24
Publication date: 2000-10-05
Also published as: GB9907459D0; GB2348552A; AU3443700A

Abstract

Data processing apparatus for connection to a computer and operable to perform data processing functions in response to control signals from the computer, the apparatus comprising input means for receiving said signals (38, 42, 46) on a given line (42) from the computer and energising means (26, 28) for supplying electrical power for operating the apparatus, wherein the energising means is operable to derive said power from said line (42), preferably at least in part from said control signals thereon, or from the voltage applied to the data terminal ready line (48) of the computer.

Description

TITLE; SUPPLY OF POWER TO A PERIPHERAL

Field of the Invention

This invention relates to data processing apparatus, and more particularly to such apparatus which is, in use, connected to a computer and is operable to perform various data processing functions in response to control signals from the computer.

Background to the Invention

One example of such apparatus is a device for reading data from and/or writing data into a data storage device such as a solid state memory, contained in, for example, a card which is insertable into the apparatus and is interchangeable with other similar cards.

A general purpose "desk top" computer, such as a PC (i.e. a personal computer to IBM specification) has a number of different ports for connection to various peripheral devices. Some of the peripheral devices, for example keyboards, derive power from dedicated power lines provided at the relevant port of the computer. However, some of the computer ports do not include dedicated power lines so that peripheral devices, for example printers, to be connected to those ports need also to have the facility to be separately connected to a power supply. This can add to the bulk and cost of those peripheral devices.

Thus, for example, if a data reading device which can be connected to the RS232 serial interface port (a port which does not have a dedicated power line) of a PC, will also normally include a cord and plug for connection to an AC mains power supply and power rectification circuitry.

Summary of the Invention According to a first aspect of the invention, there is provided data processing apparatus for connection to a computer and operable to perform data processing functions in response to control signals from the computer, the apparatus comprising input means for receiving said signals on a given line from the computer and energising means for supplying electrical power for operating the apparatus, wherein the energising means is operable to derive said power from said line, preferably at least in part from said control signals thereon.

Since the apparatus derives the power for its operation from the control signals from a computer, it can derive operating power from the computer even if it is not connected to a computer port which includes a dedicated power supply line.

Preferably, the apparatus comprises a data reading device for reading data from and/or writing data to a data carrier. Preferably, the apparatus is adapted for use with a data carrier in the form of a solid state memory, for example an internal memory or a chip card which is removably connectable to the apparatus, so as to be interchangeable with other similar chip cards.

Preferably, the apparatus has output means for generating an output voltage signal, for reception by the computer, of positive and negative polarities.

If the apparatus is to produce such an output signal, but is for use with a computer operable to supply control signals of only one voltage polarity, then the input means of the apparatus preferably comprises a first input for said control signals and a second input for receiving from a computer connected thereto a voltage of opposite polarity from the control signals, wherein the energising means is operable to derive power for one polarity of output signal from the control signals, and power for the other polarity of output signal from the other input . Conveniently, the energising means for the apparatus includes storage means for storing electrical energy from the input control signals prior to use by the apparatus.

The storage means enables the energising means to provide a power supply which is not adversely affected by short term fluctuations in the voltage of the input control signals or interruptions in the control signals.

The storage means conveniently comprises one or more capacitors .

Preferably, the energising means is operable to derive power from an input control signal, the polarity of voltage of which fluctuates, in which case the storage means is preferably connected to the input means through diode means for preventing discharge of the storage means when the polarity of the input signal is reversed.

Preferably, the data processing means is adapted for connection to the RS232 serial port of a personal computer, the first of said inputs being adapted for connection to the transmit data line of the port, and the second input to the data terminal ready line of the port.

The data processing apparatus may include a control processor unit for reading a data carrier, such as a solid state memory device, the central processing unit having lower power requirements than the output means, in which case the energising means preferably includes a voltage regulator connected between either the input and the processor.

The invention also lies in said apparatus and a personal computer connected thereto through the computer's RS232 serial port, wherein the computer is so programmed that its data terminal ready line is always at a positive voltage whenever the data processing apparatus is being supplied with power by the computer. This feature of the programming of the computer can form part of the software interface between the computer and the data processing apparatus.

The invention also lies in data processing apparatus having connecting means for connection to an RS232 serial port of a personal computer and energising means for supplying electrical power for operating the apparatus, wherein the energising means has an input for connection to the data terminal ready line connection in the RS232 port, and is operable to derive at least some of said electrical power from the voltage applied to the data terminal ready line by the computer.

Preferably, the energising means has a further input for connection to the transmit data line terminal of the RS232 port, from which line, in use, the energising means derives power from a voltage, of opposite polarity to that on the data terminal ready line, from the control signals supplied to the apparatus by the computer.

Brief Description of the Drawings

The invention will now be described, by way of example only, with reference to the accompanying drawings in which:

Figure 1 is a perspective view of the exterior of a data card reader which constitutes an embodiment of apparatus in accordance with the invention;

Figure 2 is an exploded view of Figure 1, also showing a data card for use therewith;

Figure 3 is a schematic block diagram of the data card reader and the data card inserted therein;

Figure 4 is a circuit diagram for the arrangement shown in Figure 3 ; Figure 5 is a Register File Map of a microprocessor forming part of the data card reader;

Figure 6 illustrates the format of the type of binary signal transmitted and received by the microprocessor;

Figure 7 is a flow chart illustrating the steps involved in the serial reception of data by the microprocessor; and

Figure 8 is a flow chart illustrating the steps involved in the serial transmission of data from the microprocessor.

Detailed Description

With reference to Figures 1 and 2, a data card reader comprises a housing 1, the top of which is provided with a slot 2 for receiving a data card (in the form of a chip card having a semi-conductor memory) 4. In use, the reader can either read information from or write information into the semi-conductor memory of the chip card 4 under the control of a personal computer.

As can be seen from Figure 2 , the housing 1 has an upper part 6 and a lower part 8, and contains a frame 10 which holds the electronics for the reader, and defines an upper slot 12 into which the card 4 is inserted. The frame 10 also holds contacts for engaging terminals on the card 4 to bring the circuitry in the frame 10 into electrical contact with the memory chip of the card 4. The circuitry on the frame 10 is also connected to an LED 14 which, in the assembled reader, is visible through an aperture 16 in the upper housing portion 6 and provides an indication of the operation of the device and the correct insertion of the card.

A cord 18 connects the circuitry in the frame 10 to a connector 20 for connection to a nine-pin RS232 serial port of a PC. The data card reader derives its power and receives and sends its messages through the RS232 serial port of the computer. On request from the computer, the reader will read the information stored in the data card and download it to the computer, or will write information into the card. The computer communicates with the reader via the RS232 protocol at a baud rate of 9,600 bits per second. Three of the lines from the RS232 port, DTR, TxD and SG, are shown in Figure 3. The DTR line is the data terminal ready line, the TxD line is the line along which the computer sends control signals to the reader, and SG is the signal ground line.

With reference to Figure 3, the circuitry of the reader includes a micro-controller 22, and in this case the PIC16C54 micro-controller form Microchip. The micro-controller 22 is also connected to an RS232 to TTL (Transistor Transistor Logic) converter 24 and a TTL to RS232 converter 26, as well as to a voltage regulator 28, all of which provide an interface between the micro-controller 22 and the computer. The interface converts RS232 signals from the computer (i.e. +15 v) to TTL levels (i.e. 0 v, 5 v) required by the micro-controller 22. The interface also converts TTL signals sent by the microcontroller 22 to the computer to the equivalent RS232 signal levels .

Power for the RS232 to TTL converter 24 is supplied along the DTR line, through a protection diode 30. Power for operating the TTL to RS232 converter 26 is obtained from the DTR line and from the TxD line connected to the converter 26 through a diode 32. Capacitor means 34 functions as a buffer that stores the Peak negative voltage on the TxD line. The diode 32 prevents the capacitor means 34 from being discharged through the TxD line when the latter is at a positive voltage. The regulator 28 supplies power to the RS232 to TTL module 24, the microcontroller 22 and the chip card 4. A reservoir capacitor 36 supplies current to the regulator 28 during write operations on the chip card 4. Data which is read by the micro-controller 24 from the chip card 4 is transmitted to the computer along the RxD line 38 as shown in Figure 4, in which reference numeral 40 denotes the RS232 serial port of the computer.

The following tables indicate the voltages and currents along the lines of the serial port 40.

Supply Voltages

Supply Currents

With reference to Figure 4, the RxD line is connected to the output of an operational amplifier 38 which forms part of the module 26, and which is set up as a comparator. The inverting input of the amplifier 38 is connected to the serial signal output (RAO) of the micro-controller 22, whilst the non- inverting input receives a voltage from the voltage regulator 28 via a potential divider Rll and R12 which sets the reference voltage of the amplifier to half the TTL supply voltage. Thus, a high TTL signal level at the inverting input of the amplifier 38 causes the latter to swing to its negative voltage supply, whilst a low TTL level at the inverting input causes the operational amplifier to swing to its positive voltage supply. In use, the output of the amplifier will be minus 12 volts if the voltage on the inverting input is zero, and plus 12 volts if the voltage on the inverting input is 5 volts.

The power needed by the amplifier 38 to produce a negative output signal is derived from the voltage on the TxD line 42 along which the computer sends control signals to the microcontroller 22 through the port 40. The line 42 is connected to a pair of parallel capacitors 44 and 46 (constituting the capacitor means 34), and to the amplifier 38, through a diode 32. As can be seen from the above table, there will be a negative voltage on the TxD line when the latter is not active, or is active at logic state 1. During these times, the amplifier 38 obtains power direct from the line 42, and peak negative voltages from the line 42 are stored on the capacitors 44 and 46. When the line 42 is active and in a logic state of 0, the amplifier 38 obtains its power from the capacitors 44 and 46 (which have been charged by the voltage on the line 42), during which time discharge of the capacitors back down the line 42 is prevented by means of the diode 32.

The positive voltage output from the amplifier 38 is derived from the voltage on the data terminal ready line 48 which the computer is programmed to maintain at a positive voltage during the operation of the data card reader. The line 48 is connected to the amplifier 38, the voltage regulator 28 and the reservoir capacitor 36 through a protection diode 30.

The voltage regulator comprises an integrated circuit 50, the input of which is connected to the line 48 and to earth via a decoupling capacitor 52. The output of the circuit 50 is also connected to earth through a decoupling capacitor 54.

The output is also connected to the RS232 to TTL module 24. That module comprises a MOSFET Q2 , the gate of which is connected to the TxD line 42 through an over voltage protection network (resistor R9 and zener diode D4) . When the voltage on the TxD line is high (logic state 0) the transistor is turned on and the port acting as a serial input to the microcontroller 22 (port RAl) is pulled down to ground. With TxD low (logic state 1 or not active) , the negative voltage turns the transistor off and the serial input port RAl is pulled high.

The output of the regulator 28 is also connected directly to the micro-controller 22 (to the port Vdd thereof) , and to a reset network Ql, R8 , RIO and R13, which is operable to generate a reset signal (fed to the input/MCLR of the controller 22) on activation of the reader. The Vdd input is also connected to ground through a decoupling capacitor 56.

The micro-controller 22 is driven by a 4MHz oscillator 58 connected to the inputs Oscl and Osc2 of the micro-controller 22. The chip card 4 provides 4096 bits of serial electrically erasable and programmable read only memory (EEPROM) organised as 512 words of 8 bits each. Data is written to and read from the chip card via a two-wire I²C serial interface consisting of a data (SDA) signal and clock (SCL) signal. The SDA signal is bi-directional, and the SDA and SCL signals are driven directly by the micro-controller 22. The SDA port of the card 4 is connected to the port RBO through a pair of diodes D3 which provide antistatic protection for the chip card 4, and is also connected to the port RA3 of the micro-controller 22 via the diodes and a network of resistors R4 , R5 and R6 which prevent damaging voltage variations being applied to the microcontroller 22 in the absence of any card by always putting the port to a defined voltage in that situation.

The signal received on the port RA3 is used to determine whether or not a card is present in the reader. When a card is inserted, the voltage on the port is high, whereas a low voltage is applied to the port in the absence of any card.

As can be seen, the network of resistors R4 , R5 , R6 is also connected to the output of the voltage regulator 28, as is the voltage input port (Vcc) of the chip card 4. The latter connection is made through resistor R2 , and the port Vcc on the card 4 is also connected to ground via decoupling capacitor 60. Further discussion of the micro-controller 22 is set out below.

The micro-controller 22 provides the following facilities:

512 words (12 -bit) of Program Memory

25 words (8-bit) of Data Memory (General Purpose Registers)

7 Special Function Registers

2 Bi-directional Ports (12 lines)

1 8-bit Real Time Clock/Counter (with 8-bit prescaler)

Watchdog Timer

Power Saving Modes

2 -Level Hardware Stack

Direct, Indirect and Relative Addressing

The processor has a set of 33 instructions and is capable of executing one instruction per machine cycle (except jump instructions which take two machine cycles) . Within the chip card reader the processor is clocked such that it completes one machine cycle every lμs.

The processor memory is organised into program memory and processor control/data memory. The processor can address 512 words (12-bit) of program memory. All subroutines are limited to the first half of the program memory (i.e. the first 256 locations) . The processor can access 7 Special Function Registers and 25 words (8 -bit) of data memory. The SFR and data memory are located within the register file of the processor. The structure of the register file is shown in Figure 5. The registers fall into the categories "operational", " input/output " or "general purpose".

Initialisation Values

The following values should be used for initialisation:

Port A Data Register Address : 0x05 Bit 0 = 1

Port B Data Register Address : 0x06 Bit 1 = 1 Bit 2 = 1

TRIS Port A (I/O Control Register) Address N/A 1110 = OxOE

TRIS Port B (I/O Control Register) Address : N/A 0000 0001 = 0x01

OPTION Address : N/A --00 0111 = = 0x07 RTCC Address : 0x01 0000 0000 = = 0x00

Input/Output Registers

The I/O registers (ports) are the interface between the software and external hardware. These registers can be written and read under program control .

At reset all I/O pins are defined as input. The I/O control registers (TRISA, TRISB) described further on may be used to set the lines as outputs. As soon as a pin is defined as an output, it is switched to the level indicated by the associated register bit. The processor uses two ports Port A consists of 4 bits and Port B consists of 8 bits.

Port A Data Register Address 0x05 Read/Write

Port A is programmed via the Port A data register. Only the four low-order bits, RA0-RA3, are used. Bits 7-4 are unimplemented and read as "0"s.

Bit Input/Output Function

0 Output Serial Data to PC (Transmit Line)

1 Input Serial Data from PC (Receive Line)

2 Input Not Used

3 Input Chip Card Present Switch

(high=switch activated) (set to 1)

4..7 Undefined Not Used

Port B Data Register

Port B is programmed via the Port B data register.

Bit Input/Output Function

0 Input/Output Serial Data to and from Chip Card (SDA)

1 Input/Output Serial Clock to Chip Card (SCL)

2 Output LED (l=on, 0=off)

3..7 Input Not Used

A read instruction always reads the state of a pin, regardless of it being programmed as an input or output. If an output driver on a pin is enabled and driven high, but the external system is holding it low, a read of the port will indicate that the pin is low.

Bit manipulation instructions operate as read followed by write operations. Caution must be used when applying these instructions to the ports as the entire port is read before the bit operation is executed and the result is written back to the port. Where a port has one or more pins used as input/outputs the operation can adversely effect the contents of the port's output register. The read-modify-write instructions can be avoided for bits RBO and RBI as they have been pulled high externally. After writing a "0" to the appropriate output register bits, RBO and RBI will effectively output a "1" when set-up as inputs and output a "0" when switched to outputs.

An instruction cycle consists of four non-overlapping oscillator cycles (01, 02, 03 and 04) . Data memory is read during 02 and written during 04. When performing successive write-read operations on the same I/O port the sequence of instructions should be such to allow the pin voltage to stabilise. It is advised to separate the write and read instructions with another instruction not accessing the I/O port .

Operational Registers

The operational registers serve to control the core of the processor and also make results of certain actions available to the program.

Indirect Data Addressing Address 0x00 Read/Write

The INDF register is used to give the program indirect access to data. It is used in conjunction with the FSR register described further on. A read or write command to the INDF register is treated such that the processor selects the location of the address contained in the FSR register.

Real -Time Clock Counter Register (RTCC) Address 0x01 Read Only

The RTCC register can be compared to any location within the data memory. The contents can be continuously incremented using a clock signal derived from the controller's instruction cycle clock. Program Counter ( PC) Address 0x02 Write only

The PC generates the addresses of the locations in the program memory. With the exception of jump instructions it is normally incremented by one after an instruction has been incremented.

Status Word Register Address 0x03 Read Only

The Status Word contains the processor flags. The C, D and Z flags provide the status of arithmetic operation carried out by the ALU. The PD and TO flags indicate the reset status.

Bit Function

0 Carry Bit (C) (read only)

1 Digit Carry (D) /Half Carry Bit (read only)

2 Zero Bit (Z) (read only)

3 Power-Down Bit (PD) (read only)

4 Time-Out Bit (TO) (read only) 6..7 Not Used

File Select Register (FSR) Address 0x04 Read/Write

The FSR is used with the INDF register for indirect addressing of data.

Bit Function

0..4 File Register Address (read/write)

5..7 Not Used (read only)

General Purpose Registers

A total of 25 general purpose registers (data registers) are available to the program to store data. The data registers occupy the addresses 0x07 to OxlF of the register file.

Special Purpose Registers In addition to the above registers there are several special purpose registers:

W register Read/Write

The working register, W, may be compared with the accumulator. The W register need not always be the target destination of an operation in the ALU.

TRIS registers Write Only

The TRIS registers are used to configure the I/O pins. Each pin is represented by a configuration bit in the respective TRIS register. A "0" in the relevant bit position causes the pin to function as an output. After a reset, all bits are "1" so that all port pins behave as inputs.

OPTION register Write Only

This register is used to program the prescaler of the watchdog timer (WDT) or that of the RTCC (real time clock/counter) . The OPTION instruction is used to write data to this register. All bits of the register are set to 1 at reset.

Bit Function

0..2 Select prescaler (PSO, PS1, PS2)

3 Prescaler assignment bit (PSA) (0 = RTCC, 1 = WDT)

4 RTTC signal edge (RTE) (0 = increment on rising edge, 1 = increment on falling edge)

5 RTCC signal source (RTS) (0 = internal clock, 1 = external clock)

6..7 Not Used

Stack register

The processor has a two-level hardware push/pop stack. A CALL instruction will push the current value of stack 1 into stack 2 and then push the current program counter value, incremented by one, into stack level 1. If more than two sequential CALL'S are executed, only the most recent two return addresses are stored. A RETLW instruction will pop the contents of the stack level 1 into the program counter and then copy stack level 2 contents into level 1.

Real Time Clock/Counter

The real-time clock/counter (RTCC) is an 8-bit wide counter whose contents can be read and modified at any time. As soon as the maximum state, OxFF, is reached, the counter "wraps around" to 0x00. The counter increments every instruction cycle (i.e. lμs within the reader) . However, a prescaler with a division ratio of up to 1:256 can be assigned to the counter by writing to the OPTION register. Consequently a delay of a nominal 65ms can be realised.

Watchdog Timer

The processor incorporates a watchdog time to reset a program should a crash occur. The watchdog is primarily for safety critical applications. To save memory the watchdog timer will not be implemented in the chip card reader.

The PIC16C54 contains a configuration word mapped beyond the user program memory space. The configuration word contains the watchdog timer enable bit and is accessed through a programmer. By resetting the enable bit at the device programming stage the watchdog timer will be permanently disabled.

Indirect Addressing Mode

Indirect addressing is achieved by using the INDF register file (address 0x00) . The INDF register is not a physical register. Addressing INDF actually addresses the register whose address is contained in the file select register (FSR) . Control of External Functions

The chip card reader implements a UART function which supports a RS232C standard asynchronous interface. The processor does not include a UART in hardware on-chip therefore the function is to be performed in software by using two bits of Port A (one for reception and the other for transmission - reference 1) . The interface will operate in half duplex mode (i.e. serial reception and transmission will not occur simultaneously.

The UART is to transmit and receive ASCII mode and operate at 9600 baud. As is shown in Figure 6, the asynchronous character format comprises a start bit (active low) , a seven bit character, forced mark parity (high) and two stop bits (high) . The character data is to be transmitted with the least significant bit first. The total time frame for one bit will be approximately 104μs.

Reception

A flowchart for the serial reception of data by the microcontroller 22 is shown in Figure 7. The data receive pin (RAl) should be polled at least every 52μs (half a bit period) to detect the start bit of any serial data from the PC. Once a start bit has been found the first data bit should be clocked in after 130μs (1.25 x bit period) . Subsequent data bits for the character and the parity bit should then be clocked into the receive register at intervals of 104μs. The parity bit is to be held in the msb position.

Transmission

A flowchart for the serial transmission is shown in Figure Prior to transmission the ASCII value of the character to be sent is loaded into the transmit register along with the parity bit in the msb position. A start bit is then generated by setting the transmit data pin (RAO) low for 104μs (one bit period) . Next the transmit register is sequentially shifted out to RAO AT 104μs intervals with the Isb first. After the parity bit has been transmitted RAl is held high for a further 208μs for the transmission of the two stop bits.

It will be appreciated that the data card reader can be used to read and write a wide variety of data. In the present example, however, the reader is intended for reading data cards which store data on the human ovulation cycle, more specifically data obtained from a fertility monitoring device which, through appropriate hormone measurements, determines peak periods of fertility during the cycle. Thus, a user of the monitoring device can record data on their fertility cycle chip card, which can then be used to transfer the data to the PC of a medical professional, using the data card reader. The reader can also receive data cards which store other information, for example cards in which the occasions on which intercourse has ι occurred have been logged (to enable the medical professional to determine whether the monitor is being used correctly) .

Further information on the components of the data and reader is given in the following table.

Component types: Chipcard Reader/Programmer (Rev 1.0)

CΛ O

H

CJ H W

CΛ

W w SO w

H

W

OS

Component types : FAM Chipcard Reader Unit

Claims

1. Data processing apparatus for connection to a computer and operable to perform data processing functions in response to control signals from the computer, the apparatus comprising input means for receiving said signals on a given line from the computer and energising means for supplying electrical power for operating the apparatus, wherein the energising means is operable to derive said power from said line.

2. Apparatus according to claim 1, in which said power is derived, at least in part, from said control signals on said line.

3. Apparatus according to claim 1 or claim 2, in which the apparatus comprises a data reading device for reading data from and/or writing data to a data carrier.

4. Apparatus according to claim 3, in which the apparatus comprises a data card reader.

5. Apparatus according to any of the preceding claims, in which the apparatus has output means for generating an output voltage signal, for reception by the computer, of positive and negative polarities.

6. Apparatus according to claim 5, in which the apparatus is adapted for use with a computer operable to supply control signals of only one voltage polarity, the input means of the apparatus comprising a first input for said control signals and a second input for receiving from a computer connected thereto a voltage of opposite polarity from the control signals, wherein the energising means is operable to derive power for one polarity of output signal from the control signals, and power for the other polarity of output signal from the other input .

7. Apparatus according to any of the preceding claims, in which the energising means for the apparatus includes storage means for storing electrical energy from the input control signals prior to use by the apparatus.

8. Apparatus according to claim 7, in which the storage means comprises one or more capacitors.

9. Apparatus according to claim 7 or claim 8, in which the energising means is operable to derive power from an input control signal, the polarity of voltage of which fluctuates, the storage means being connected to the input means through diode means for preventing discharge of the storage means when the polarity of the input signal is reversed.

10. Apparatus according to any of the preceding claims, in which the apparatus is adapted for connection to the RS232 serial port of a personal computer, input means comprising first and second inputs, the first of said inputs being adapted for connection to the transmit data line of the port, and the second input to the data terminal ready line of the port.

11. Apparatus according to claim 5 or claim 6, in which the data processing apparatus includes a control processor unit for reading a data carrier, the control processor unit having lower power requirements than the output means, wherein the energising means includes a voltage regulator connected between the input and the processor.

12. Apparatus according to claim 10 and a computer connected thereto through the computer's RS232 serial port, wherein the computer is so programmed that its data terminal ready line is always at a positive voltage whenever the data processing apparatus is being supplied with power by the computer.

13. Data processing apparatus having connecting means for connection to an RS232 serial port of a computer and energising means for supplying electrical power for operating the apparatus, wherein the energising means has an input for connection to the data terminal ready line connection in the RS232 port, and is operable to derive at least some of said electrical power from the voltage applied to the data terminal ready line by the computer.

14. Apparatus according to claim 13, in which the energising means has a further input for connection to the transmit data line terminal of the RS232 port, from which line, in use, the energising means derives power from a voltage, of opposite polarity to that on the data terminal ready line, from the control signals supplied to the apparatus by the computer.

15. Data processing apparatus substantially as described herein with reference to, and as illustrated in, the accompanying drawings .