WO2000048444A3 - Packaging for a semiconductor chip - Google Patents

Packaging for a semiconductor chip Download PDF

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Publication number
WO2000048444A3
WO2000048444A3 PCT/EP2000/000678 EP0000678W WO0048444A3 WO 2000048444 A3 WO2000048444 A3 WO 2000048444A3 EP 0000678 W EP0000678 W EP 0000678W WO 0048444 A3 WO0048444 A3 WO 0048444A3
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor chip
packaging
interposer
relates
semiconductor
Prior art date
Application number
PCT/EP2000/000678
Other languages
German (de)
French (fr)
Other versions
WO2000048444A2 (en
Inventor
Joerg Ludewig
Werner Schneider
Gregor Woldt
Gerold Kloetzig
Kay Schoene
Original Assignee
Wichmann Workx Ag Information
Microelectronic Packaging Dres
Joerg Ludewig
Werner Schneider
Gregor Woldt
Gerold Kloetzig
Kay Schoene
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE29902754U external-priority patent/DE29902754U1/en
Application filed by Wichmann Workx Ag Information, Microelectronic Packaging Dres, Joerg Ludewig, Werner Schneider, Gregor Woldt, Gerold Kloetzig, Kay Schoene filed Critical Wichmann Workx Ag Information
Priority to AU22941/00A priority Critical patent/AU2294100A/en
Publication of WO2000048444A2 publication Critical patent/WO2000048444A2/en
Publication of WO2000048444A3 publication Critical patent/WO2000048444A3/en

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    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)

Abstract

The invention relates to packaging for a semiconductor chip (10), in which the semiconductor chip (10) is bonded to an interposer (20), which has a central opening (26) over a central bonding pad area (16) of the semiconductor chip (10). Wire bridges (40) passing through said central opening (26) lead from bonding pads (18) on the semiconductor chip (10) to connecting pads (36) on the interposer (20). The invention also relates to a semiconductor component and a memory module having corresponding characteristics, as well as to a method of production used notably for the production of a semiconductor component of this kind.
PCT/EP2000/000678 1999-02-16 2000-01-28 Packaging for a semiconductor chip WO2000048444A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU22941/00A AU2294100A (en) 1999-02-16 2000-01-28 Packaging for a semiconductor chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE29902754.6 1999-02-16
DE29902754U DE29902754U1 (en) 1998-02-20 1999-02-16 Package for a semiconductor chip

Publications (2)

Publication Number Publication Date
WO2000048444A2 WO2000048444A2 (en) 2000-08-24
WO2000048444A3 true WO2000048444A3 (en) 2003-05-22

Family

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Family Applications (1)

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PCT/EP2000/000678 WO2000048444A2 (en) 1999-02-16 2000-01-28 Packaging for a semiconductor chip

Country Status (2)

Country Link
AU (1) AU2294100A (en)
WO (1) WO2000048444A2 (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0428260A (en) * 1990-05-23 1992-01-30 Matsushita Electric Ind Co Ltd Method of mounting semiconductor chip
JPH07321244A (en) * 1994-05-27 1995-12-08 Matsushita Electric Ind Co Ltd Electronic part, and manufacture of electronic part
JPH09260441A (en) * 1996-03-26 1997-10-03 Mitsubishi Electric Corp Semiconductor device
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
EP0810655A2 (en) * 1996-05-29 1997-12-03 Texas Instruments Incorporated A package for a semiconductor device
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
GB2320616A (en) * 1996-12-18 1998-06-24 Hyundai Electronics Ind Semiconductor chip package
US5858815A (en) * 1996-06-21 1999-01-12 Anam Semiconductor Inc. Semiconductor package and method for fabricating the same
JPH1154537A (en) * 1997-07-31 1999-02-26 Mitsui High Tec Inc Semiconductor device and its manufacture
EP0915505A1 (en) * 1997-11-06 1999-05-12 Sharp Kabushiki Kaisha Semiconductor device package, manufacturing method thereof and circuit board therefor

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0428260A (en) * 1990-05-23 1992-01-30 Matsushita Electric Ind Co Ltd Method of mounting semiconductor chip
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
JPH07321244A (en) * 1994-05-27 1995-12-08 Matsushita Electric Ind Co Ltd Electronic part, and manufacture of electronic part
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
JPH09260441A (en) * 1996-03-26 1997-10-03 Mitsubishi Electric Corp Semiconductor device
EP0810655A2 (en) * 1996-05-29 1997-12-03 Texas Instruments Incorporated A package for a semiconductor device
US5858815A (en) * 1996-06-21 1999-01-12 Anam Semiconductor Inc. Semiconductor package and method for fabricating the same
GB2320616A (en) * 1996-12-18 1998-06-24 Hyundai Electronics Ind Semiconductor chip package
JPH1154537A (en) * 1997-07-31 1999-02-26 Mitsui High Tec Inc Semiconductor device and its manufacture
EP0915505A1 (en) * 1997-11-06 1999-05-12 Sharp Kabushiki Kaisha Semiconductor device package, manufacturing method thereof and circuit board therefor

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
AMAGAI M: "Chip scale package (CSP) solder joint reliability and modeling", 2ND 1998 IEMT/IMC SYMPOSIUM (IEEE CAT. NO.98EX225), 2ND 1998 IEMT/IMC SYMPOSIUM, TOKYO, JAPAN, 15-17 APRIL 1998, 1998, TOKYO, JAPAN, ORGANIZING COMMITTEE 1998 IEMT/IMC SYMPOSIUM, JAPAN, PAGE(S) 216 - 223, ISBN: 0-7803-5090-1, XP002136547 *
CHANCHANI R ET AL: "A NEW MINI BALL GRID ARRAY (MBGA) MULTICHIP MODULE TECHNOLOGY", INTERNATIONAL JOURNAL OF MICROCIRCUITS AND ELECTRONIC PACKAGING,US,INTERNATIONAL MICROELECTRONICS & PACKAGING SOCIETY, vol. 18, no. 3, 1 July 1995 (1995-07-01), pages 185 - 192, XP000538985, ISSN: 1063-1674 *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 196 (E - 1200) 12 May 1992 (1992-05-12) *
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 04 30 April 1996 (1996-04-30) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 02 30 January 1998 (1998-01-30) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 05 31 May 1999 (1999-05-31) *

Also Published As

Publication number Publication date
WO2000048444A2 (en) 2000-08-24
AU2294100A (en) 2000-09-04

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