WO2000048444A2 - Packaging for a semiconductor chip - Google Patents

Packaging for a semiconductor chip Download PDF

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Publication number
WO2000048444A2
WO2000048444A2 PCT/EP2000/000678 EP0000678W WO0048444A2 WO 2000048444 A2 WO2000048444 A2 WO 2000048444A2 EP 0000678 W EP0000678 W EP 0000678W WO 0048444 A2 WO0048444 A2 WO 0048444A2
Authority
WO
WIPO (PCT)
Prior art keywords
interposer
semiconductor chip
housing according
semiconductor
contact
Prior art date
Application number
PCT/EP2000/000678
Other languages
German (de)
French (fr)
Other versions
WO2000048444A3 (en
Inventor
Jörg Ludewig
Werner Schneider
Gregor Woldt
Gerold Klötzig
Kay SCHÖNE
Original Assignee
Wichmann Workx Ag Information Technology
Microelectronic Packaging Dresden Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE29902754U external-priority patent/DE29902754U1/en
Application filed by Wichmann Workx Ag Information Technology, Microelectronic Packaging Dresden Gmbh filed Critical Wichmann Workx Ag Information Technology
Priority to AU22941/00A priority Critical patent/AU2294100A/en
Publication of WO2000048444A2 publication Critical patent/WO2000048444A2/en
Publication of WO2000048444A3 publication Critical patent/WO2000048444A3/en

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    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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Definitions

  • the invention relates to the field of integrated circuits and in particular to the field of packaging technology for semiconductor chips.
  • the invention is intended for small-sized housings for tightly packed circuit arrangements.
  • these can be housings as they are usually referred to as a micro ball grid array or also as CSP (chip size packaging or chip scale packaging).
  • semiconductor components are used whose housings are as flat as possible and are intended to enable the greatest possible packing density.
  • the housing for the semiconductor chip should, if possible, also be designed in such a way that safe handling is ensured in subsequent assembly steps, for example when mounting on a printed circuit board or the like.
  • the semiconductor component should also be suitable for high frequencies in addition to the small size.
  • German utility model DE 298 03 001 U1 Several designs of a housing for a semiconductor chip are known from German utility model DE 298 03 001 U1, but all of them are provided for semiconductor chips with lateral bond island regions. The central area of the semiconductor chip is expressly called "bond island free”.
  • US Pat. No. 5,258,330 discloses a semiconductor chip arrangement in which an interposer is arranged on the semiconductor chip and covers an area on the semiconductor chip that is smaller than the area enclosed by the bond pads arranged in the edge region of the semiconductor chip.
  • the interposer itself consists of a polymer film and is provided with interconnects that end at one end in a small contact area opposite the respective bond pad. This is a complex design because the interposer consisting of a polymer film requires complex and non-standard processing. In addition, in subsequent assembly steps, appropriate tools must be gripped directly on the semiconductor chip, as a result of which this can be damaged.
  • the invention is therefore based on the object of at least partially avoiding the disadvantages of the prior art.
  • the invention is intended to create an inexpensive housing of small size which is suitable for high frequencies.
  • the occurrence of thermal-mechanical stresses should preferably be prevented.
  • the invention is to be optimized especially for use with memory chips which have a central bond island region in a manner known per se.
  • the object on which the invention is based is achieved by a housing for a semiconductor chip with the features of claim 1, a semiconductor component with the features of claim 22, a memory module with the features of claim 23 and a method for producing a semiconductor component with the features of claim 25 .
  • the dependent claims define preferred embodiments of the invention. The wording of the claims is hereby expressly included in the present description with regard to its disclosure content.
  • an interposer with a central opening is provided.
  • semiconductor chips which likewise have a centrally arranged bond island region
  • considerably shorter line lengths in particular with regard to the bond wires
  • the housing according to the invention can be designed to be very compact and, above all, flat, although adequate mechanical protection for the semiconductor chip is nevertheless made possible.
  • the thermal-mechanical stress on the semiconductor component can be significantly reduced by the invention.
  • the “front side” of a semiconductor chip is to be understood as its structured side (side with active structures). This does not exclude that the back of the semiconductor chip also has active structures.
  • central area and “central breakthrough” are to be understood here to mean an area or breakthrough that is at least on one side (and preferably on two sides or even on all four sides) a considerable distance from the side edges of the semiconductor chip.
  • the mention of a central breakthrough is not intended to exclude the existence of further breakthroughs, although only one breakthrough is provided in preferred embodiments.
  • the contact islands and / or connections for the external contact are arranged on at least or exactly two sides of the central opening. This enables a large number of connections with a small size. A particularly high mechanical stability is achieved if the interposer is glued flat to the semiconductor chip on at least two sides of the opening.
  • the semiconductor chip attached to the interposer is at least partially surrounded by a glob top (encapsulation compound) to encase it, the encapsulation compound preferably only enclosing the edges of the semiconductor chip.
  • the lateral mechanical protection of the semiconductor chip is preferably carried out exclusively by the interposer and the glob top or the sealing compound; in particular, no other circuit board is provided in which the semiconductor chip is embedded.
  • the glob top or the potting compound preferably have a considerable thickness, which decreases only slightly towards the side edge of the interposer.
  • the thickness of the glob top or the sealing compound can also be at least 75% or at least 50% of the thickness of the semiconductor chip on the side edge of the interposer.
  • the interposer is larger in terms of area than the semiconductor chip in terms of its external dimensions (ie without taking into account the at least one opening).
  • the opening can have an elongated shape and can be filled with a casting compound.
  • the through the Breakthrough wire bridges are preferably completely encased and are therefore particularly well protected against damage.
  • a solder mask or other barrier can serve as a side limitation for the sealing compound.
  • the interposer preferably consists of a conventional printed circuit board material or material with properties similar to printed circuit boards. Important criteria for the choice of material are good machinability and good properties (e.g. dimensional stability) even at higher temperatures.
  • the side facing the semiconductor chip of the interposer is preferably flat, as a result of which a good joint connection is achieved with little manufacturing effort.
  • the interposer preferably protrudes only slightly laterally beyond the semiconductor chip (for example at most 10 mm or at most 5 mm or at most 2 mm or at most 1 mm).
  • the external connections located on the interposer can be designed as spherical or hemispherical contact elements (e.g. solder balls) or as contact elements with a convex surface (e.g. polymer bump) or in the form of small solder deposits, so that the semiconductor component can be easily mounted, for example on printed circuit boards.
  • spherical or hemispherical contact elements e.g. solder balls
  • contact elements with a convex surface e.g. polymer bump
  • a heat sink can be mounted on the back of the semiconductor chip.
  • the back also has active structures, and wire bridges are led from bond pads of these active structures to the interposer.
  • Such a two-sided semiconductor chip can in particular consist of two customary, single-sided semiconductor chips which are connected (in particular glued) to one another on their rear sides.
  • the configurations with a two-sided semiconductor chip are also regarded as an independent invention, in which the positions of the bond pads on the front and back of the semiconductor chip and the corresponding opening in the interposer do not constitute any significant features.
  • a large number of semiconductor components are manufactured from an interposer plate.
  • the semiconductor components are separated and individualized only after a glob top or a sealing compound has been applied.
  • the semiconductor component according to the invention has a semiconductor chip known per se with a central bond island region and a package according to the invention.
  • the memory module according to the invention is formed using several such semiconductor components.
  • the memory module can, for example, be designed in accordance with the Intel PC SDRAM specification and / or the JEDEC specification 21-C, section 4: "Multi-Chip Memory Modules &Cards" (available at http://developer.intel.com/design/ chipsets / memory / sdram.htm or http://www.jedec.org/download/pub21/default.htm).
  • the semiconductor component according to the invention and / or the memory module and / or the production method are developed with features that correspond to the features just described and / or mentioned in the dependent device claims.
  • the memory module preferably has a printed circuit board as a carrier board for a plurality of semiconductor components, and the material of this printed circuit board corresponds to the material used for the interposers.
  • FIG. 1 is a plan view of a semiconductor device with a housing according to a first embodiment of the invention
  • FIG. 2 shows a sectional illustration of the semiconductor component shown in FIG. 1 along the line II-II,
  • FIG. 3 shows a sectional illustration similar to that in FIG. 2 in a slightly modified exemplary embodiment
  • FIG. 4 shows a plan view of an interposer plate for producing twenty-five interposers
  • 5 is an enlarged sectional view along the line V - V in Fig. 4 in a later stage of the manufacturing process
  • FIG. 6 is an exploded view of some components of the housing according to the invention in a slightly varied embodiment of the invention.
  • FIG. 7 shows a sectional illustration similar to that in FIG. 2 in a further exemplary embodiment of the invention.
  • the semiconductor component shown in FIGS. 1 and 2 has a semiconductor chip 10 with a housing according to the invention.
  • the semiconductor chip 10 has a front side 12 with active structures, for example an integrated memory field, and a rear side 14 opposite the front side.
  • the semiconductor chip 10 is provided with bonding pads 18 (pads) which are arranged centrally in a row are.
  • the bond pads 18 can also be arranged in several rows that run parallel or at right angles to one another.
  • the semiconductor chip 10 there is an interposer 20, which consists of a printed circuit board material with a flat front and rear side 22, 24.
  • the interposer 20 Above the central bond island region 16 of the semiconductor chip 10, the interposer 20 has a centrally arranged opening 26 which has the shape of an elongated gap or rectangle rounded on the two narrow sides.
  • the opening 26 does not completely separate the interposer 20. Rather, the two side areas of the interposer 20 are the are located above the bond island-free regions of the semiconductor chip 10, connected to one another by two connections on each narrow side of the opening 26.
  • the interposer 20 is used for the electrical connection of the semiconductor component to a printed circuit board and is therefore provided on its front side 22 with external connections 30 which are in the form of arrays on both sides of the opening 26 (for example in FIG Long sides of the opening 26) are arranged.
  • the external connections 30 are configured as solder balls (micro balls) which are located on contact surfaces 32.
  • polymer bumps or solder deposits can also serve as external connections 30 instead of the solder balls.
  • the contact surfaces 32 for the external connections 30 are located on the front side 22 of the interposer 20.
  • the contact surfaces 32 are connected to interconnects 34 which run to central contact islands 36.
  • the interconnects 34 are guided both on the surface and in the inner volume of the interposer 20 (only a few interconnects 34 are shown in the drawing by way of example).
  • the interposer 20 is thus designed as a multi-layer (e.g. two, four or six-layer) printed circuit board with the necessary plated-through holes.
  • the interconnects 34 are designed as copper interconnects and gold-plated on the surface in the interest of better contactability.
  • the central contact islands 36 are arranged laterally directly next to the opening 26 in the interposer 20, e.g. 1 to the right or left of the long side of the opening 26.
  • Wire bridges 40 (bonding wires) are pulled through the opening 26 from one bonding island 18 of the semiconductor chip 10 to one central contact island 36 to the right or left of the opening 26.
  • Gold or aluminum wire is used as the material for the wire bridges 40.
  • the wire bridges 40 run alternately from the row of bond pads 18 to a left or right contact pad 36, so that the risk of undesired contact and connection between two wire bridges 40 is avoided.
  • the opening 26 is arranged such that it is located exactly above the bond pads 18 and keeps an area around the row of bond pads 18 that is sufficient for the bonding process.
  • the opening 26 is filled with a potting compound 42 known per se, which also encases the wire bridges 40 and protects them against damage.
  • the potting compound 42 forms a plug which is mushroom-shaped in cross section and has a slightly convex cap (FIG. 2). So that the assembly of the semiconductor component is not hindered, the plug protrudes only slightly beyond the front side 22 of the interposer 20. For this reason, the wire bridges 40 must also be guided relatively close to the surface of the contact islands 36.
  • a solder mask 44 covers the front 22 of the interposer 20, the contact surfaces 32 and an inner region 46 being kept free.
  • the area 46 which is kept free comprises the opening 26 and the adjoining contact islands 36.
  • the solder mask 44 is significantly thicker than would be necessary for the pure function of protection against liquid solder.
  • the edges of the solder mask 44 on the area 46 which is kept free form a boundary for the sealing compound 42.
  • the plug formed by the sealing compound 42 thus has a defined shape.
  • complete coverage of the wire bridges 40 is ensured when the potting compound 42 is filled into the opening 26 and the area 46 kept free up to the upper edge of the solder mask 42.
  • another barrier is provided as a limitation for the sealing compound 42, for example a bead or a strand made of another material.
  • the thickness of the solder mask 44 at the area around the contact surfaces 32 is approximately equal to the thickness of the contact surfaces 32.
  • the transition at the boundary between the contact surfaces 32 and the solder mask 44 has only a slight difference in height (for example less than 0.2 mm or less than 0.1 mm). This measure prevents a protruding edge of the solder mask 44 from acting as a lever attachment point when the external connections 30 are subjected to a lateral load, the lever being formed exerting an increased force on the connection between the contact surfaces 32 and the external connections 30.
  • a lateral load can be caused, for example, by a different thermal expansion of the interposer 20 and a printed circuit board on which the entire semiconductor component is soldered.
  • the interconnects 34 and the contact islands 36 are significantly thinner than the contact surfaces 32 or the solder mask 44. This firstly prevents the solder mask 44 from arching up above the interconnects 34. Secondly, this leaves enough space between the tops of the contact islands 36 and the upper edge of the area 46 which is kept free for the wire bridges 40 and the casting compound 42 covering these wire bridges 40.
  • the contact surfaces 32, the interconnects 34 and the contact islands 36 are approximately the same thickness .
  • the interposer 20 has a somewhat larger area than the semiconductor chip 10 and projects on each side about 0.5 mm beyond the side edge of the semiconductor chip 10. At the angle that is formed in each case between the side wall of the semiconductor chip 10 and the projecting section of the interposer 20, there is potting compound that forms a glob top 50. In the exemplary embodiment described here, only the sides of the semiconductor chip 10 are enclosed by the glob top 50, while in alternative embodiments the glob top 50 also surrounds the semiconductor chip 10 or at least partially covers the rear side 14 thereof. By combining the (small) protrusion of the interposer 20 with the Glob Top 50, good mechanical protection is achieved with a small overall size (in particular a low overall height).
  • the glob top 50 directly on the semiconductor chip 10 is approximately as thick as the semiconductor chip 10. To the side, the thickness of the glob top 50 drops somewhat, but not significantly. This form offers a particularly good lateral protection of the semiconductor chip 10. It is achieved in that the Glob Top 50 for several semiconductor components is applied before the separation of these components using the manufacturing method described in more detail below.
  • Fig. 3 corresponds to that previously described. Only a few components are dimensioned differently. Thus, hemispherical external connections 30 are provided, and the lateral protrusion of the interposer 20 over the semiconductor chip 10 is greater. The main difference is that the thickness of the glob top 50 decreases towards the edge of the interposer 20 to practically zero.
  • FIG. 4 An exemplary embodiment of a production method is described below, with which several housings and semiconductor components according to the invention can be produced simultaneously and inexpensively. This method is based on an interposer plate 60 shown in FIG. 4, on which a plurality of (twenty-five in FIG. 4) interposers 20 are formed at a short distance from one another.
  • the interposer plate 60 is made of a circuit board-like material that is also used for typical carrier boards, e.g. one of the materials known as FR4-Epoxy or FR5-Epoxy or BT.
  • an opening 26 is machined into the interposer plate 60, for example by milling or punching.
  • the solder mask 44 is applied to the front of the interposer plate 60 for each subsequent interposer 20, the contact surfaces 32 and the region 46 being kept free.
  • a special solder resist is used in design variants, or several (preferably two) layers of lacquer are applied.
  • a semiconductor chip 10 is now glued on behind each opening 26, so that the opening 26 is located exactly above the bonding pads 18.
  • An epoxy resin known per se is used as the adhesive.
  • the electrical connection in the form of the wire bridges 40 is established by a bonding method known per se, the wire bridges 40 of each semiconductor component being pulled through the corresponding opening 26 from the bonding pads 18 to the contact pads 36.
  • the casting compound 42 is filled into each opening 26 of the interposer plate 60 and into the adjoining, kept free area 46 of the solder mask 44.
  • the wire bridges 40 are thereby completely enveloped by the potting compound 42 and thus fixed and protected.
  • the glob tops 50 are applied before or after the openings 26 are cast.
  • the same casting compound as for the openings 26 or another material can be used.
  • the glob tops 50 only enclose the edges of the semiconductor chips 10. This is sufficient for hermeticization (protection against moisture) and for mechanical protection.
  • the glob-top compound or another casting compound is filled into the spaces between the semiconductor chips 10 on the rear side of the interposer plate 60, which is still connected. The gaps are at least largely filled, so that the glob-top mass has only a slightly concave or even convex surface. This state is shown in the sectional view of FIG. 5.
  • the housings are separated by cutting the interposer plate 60 at separation areas 62 (for example by sawing or using a laser).
  • the separation regions 62 which are indicated in FIG. 4 and FIG. 5 by dashed lines, run at a short distance from the sides of the semiconductor chips 10 through the encapsulated gaps between the semiconductor chips 10. The distance mentioned determines the overhang of the interposer 20 in the finished one Component and is, for example, 0.5 mm.
  • the interposer plate 60 and the glob top mass located thereon are cut through.
  • the semiconductor components formed in this way are now individualized.
  • the external connections 30 are only now being applied to the contact surfaces 32 (for example by screen printing or a solder wave process), in the exemplary embodiment described here this step takes place before the interposer plate 60 is separated, but after the solder mask 44 has been applied.
  • the semiconductor chip 10 and the interposer 20 are shown again in a slightly modified exemplary embodiment. The latter is still part of the interposer plate 60.
  • the external connections 30 are already attached.
  • FIG. 7 The alternative embodiment shown in FIG. 7 is based on the arrangement previously described in detail.
  • This alternative is designed as a housing for half Suitable conductor chips 10, which have on their front and back 12, 14 active structures and associated bond pads 18, 19.
  • Such semiconductor chips 10 can be formed by forming the active structures on both sides on a carrier (die).
  • the semiconductor chip 10 consists of two chip elements 70, 72, which in turn are conventional semiconductor chips, each with an active side (front side) and a rear side.
  • the chip elements 70, 72 are glued together on their rear sides.
  • the interposer has 20 more
  • Conductors 74 which penetrate the interposer 20 and connect the contact surfaces 32 on the front 12 of the interposer 20 in a suitable manner with contact islands 76 on the rear of the interposer 20.
  • the contact islands 76 are arranged on the edge of the interposer 20 in the protruding area which is not covered by the semiconductor chip 10.
  • Wire bridges 78 are drawn from the contact islands 76 to contact islands 36 on the rear side 14 of the semiconductor chip 10 (front side of the chip element 72).
  • the wire bridges 78 can be located on the edge or in a central region of the rear side 14.
  • a glob top 50 or another suitable protective covering encloses the semiconductor chip 10 and the wire bridges 78.

Abstract

The invention relates to packaging for a semiconductor chip (10), in which the semiconductor chip (10) is bonded to an interposer (20), which has a central opening (26) over a central bonding pad area (16) of the semiconductor chip (10). Wire bridges (40) passing through said central opening (26) lead from bonding pads (18) on the semiconductor chip (10) to connecting pads (36) on the interposer (20). The invention also relates to a semiconductor component and a memory module having corresponding characteristics, as well as to a method of production used notably for the production of a semiconductor component of this kind.

Description

Häusung für ein HalbleiterchipPackage for a semiconductor chip
Die Erfindung betrifft das Gebiet der integrierten Schaltungen und insbesondere das Gebiet der Gehäusetechnik für Halbleiterchips. Speziell ist die Erfindung für Häusungen geringer Baugröße für dicht gepackte Schaltungsanordnungen vorgesehen. Zum Beispiel können dies Häusungen sein, wie sie üblicherweise als Micro Ball Grid Array oder auch als CSP (Chip Size Packaging bzw. Chip Scale Packaging) bezeichnet werden.The invention relates to the field of integrated circuits and in particular to the field of packaging technology for semiconductor chips. In particular, the invention is intended for small-sized housings for tightly packed circuit arrangements. For example, these can be housings as they are usually referred to as a micro ball grid array or also as CSP (chip size packaging or chip scale packaging).
Um in modernen Geräten eine große Funktionalität und Arbeitsgeschwindigkeit bei geringer Baugröße zu erreichen, werden Halbleiterbauelemente eingesetzt, deren Häusungen möglichst flach sein und eine möglichst große Packungsdichte ermöglichen sollen. Insbesondere soll bei derartigen Häusungen gewährleistet sein, daß die bei der Anwendung der mit solchen Häusungen ausgestatteten Bauelemente auftretenden thermisch-mechanischen Belastungen nicht zu einer Beschädigung derselben führen können. Darüber hinaus sollte die Häusung für das Halbleiterchip möglichst auch derart gestaltet sein, daß bei nachfolgenden Montageschritten, beispielsweise beim Montieren auf einer Leiterplatte o.dgl., ein sicheres Handling gewährleistet wird. Wichtige Aspekte sind ferner, daß das Halbleiterbauelement neben der geringen Baugröße auch für hohe Frequenzen geeignet sein soll.In order to achieve a high level of functionality and operating speed with a small size in modern devices, semiconductor components are used whose housings are as flat as possible and are intended to enable the greatest possible packing density. In particular, it should be ensured in such housings that the thermal-mechanical loads occurring when using the components equipped with such housings cannot damage the same. In addition, the housing for the semiconductor chip should, if possible, also be designed in such a way that safe handling is ensured in subsequent assembly steps, for example when mounting on a printed circuit board or the like. Important aspects are furthermore that the semiconductor component should also be suitable for high frequencies in addition to the small size.
Aus dem deutschen Gebrauchsmuster DE 298 03 001 U1 sind mehrere Ausgestaltungen einer Häusung für ein Halbleiterchip bekannt, die jedoch sämtlich für Halbleiterchips mit seitlichen Bondinselbereichen vorgesehen sind. Der zentrale Bereich des Halbleiterchips wird ausdrücklich als "bondinselfrei" gefordert.Several designs of a housing for a semiconductor chip are known from German utility model DE 298 03 001 U1, but all of them are provided for semiconductor chips with lateral bond island regions. The central area of the semiconductor chip is expressly called "bond island free".
Aus der US 5,258,330 geht eine Halbleiterchipanordnung hervor, bei der auf dem Halbleiterchip ein Interposer angeordnet ist, der eine Fläche auf dem Halbleiter- chip überdeckt, die kleiner ist als die durch die im Randbereich des Halbleiterchips angeordneten Bondinseln eingeschlossene Fläche. Der Interposer selbst besteht aus einer Polymerfolie und ist mit Leitbahnen versehen, die an einem Ende in einer kleinen Kontaktfläche gegenüber der jeweils zugeordneten Bondinsel enden. Dies ist eine aufwendige Ausgestaltung, weil der aus einer Polymerfolie bestehende Interposer eine komplexe und nicht standardgemäße Verarbeitung erfordert. Überdies muß bei nachfolgenden Montageschritten mit entsprechenden Werkzeugen unmittelbar am Halbleiterchip gefaßt werden, wodurch dieses beschädigt werden kann.US Pat. No. 5,258,330 discloses a semiconductor chip arrangement in which an interposer is arranged on the semiconductor chip and covers an area on the semiconductor chip that is smaller than the area enclosed by the bond pads arranged in the edge region of the semiconductor chip. The interposer itself consists of a polymer film and is provided with interconnects that end at one end in a small contact area opposite the respective bond pad. This is a complex design because the interposer consisting of a polymer film requires complex and non-standard processing. In addition, in subsequent assembly steps, appropriate tools must be gripped directly on the semiconductor chip, as a result of which this can be damaged.
Der Erfindung liegt deshalb die Aufgabe zugrunde, die Nachteile des Standes der Technik zumindest zum Teil zu vermeiden. Insbesondere soll durch die Erfindung eine kostengünstige Häusung geringer Baugröße geschaffen werden, die für hohe Frequenzen geeignet ist. Vorzugsweise soll dabei das Entstehen thermisch-mechanischer Spannungen verhindert werden. Insbesondere soll die Erfindung speziell für den Einsatz mit Speicherchips optimiert sein, die in an sich bekannter Weise einen zentralen Bondinselbereich aufweisen.The invention is therefore based on the object of at least partially avoiding the disadvantages of the prior art. In particular, the invention is intended to create an inexpensive housing of small size which is suitable for high frequencies. The occurrence of thermal-mechanical stresses should preferably be prevented. In particular, the invention is to be optimized especially for use with memory chips which have a central bond island region in a manner known per se.
Die der Erfindung zugrundeliegende Aufgabenstellung wird durch eine Häusung für ein Halbleiterchip mit den Merkmalen des Anspruchs 1 , ein Halbleiterbauelement mit den Merkmalen des Anspruchs 22, ein Speichermodul mit den Merkmalen des Anspruchs 23 und ein Verfahren zur Herstellung eines Halbleiterbauelements mit den Merkmalen des Anspruchs 25 gelöst. Die abhängigen Ansprüche definieren bevorzugte Ausführungsformen der Erfindung. Der Wortlaut der Ansprüche wird hiermit hinsichtlich seines Offenbarungsgehalts ausdrücklich in die vorliegende Beschreibung aufgenommen.The object on which the invention is based is achieved by a housing for a semiconductor chip with the features of claim 1, a semiconductor component with the features of claim 22, a memory module with the features of claim 23 and a method for producing a semiconductor component with the features of claim 25 . The dependent claims define preferred embodiments of the invention. The wording of the claims is hereby expressly included in the present description with regard to its disclosure content.
Bei der erfindungsgemäßen Häusung ist ein Interposer mit einem zentralen Durch- bruch vorgesehen. In Verbindung mit Halbleiterchips, die einen ebenfalls zentral angeordneten Bondinselbereich aufweisen, werden daher erheblich kürzere Leitungslängen (insbesondere hinsichtlich der Bonddrähte) möglich als im Stand der Technik. Damit verringern sich störende Kapazitäten und Induktivitäten, so daß sich das Halbleiterbauteil mit höheren Frequenzen betreiben läßt. Die erfindungs- gemäße Häusung läßt sich sehr kompakt und vor allem flach ausgestalten, wobei dennoch hinreichender mechanischer Schutz für das Halbleiterchip ermöglicht wird. Überdies kann durch die Erfindung die thermisch-mechanische Belastung des Halbleiterbauelementes bedeutend verringert werden. In der hier verwendeten Wortwahl ist unter der "Vorderseite" eines Halbleiterchips dessen strukturierte Seite (Seite mit aktiven Strukturen) zu verstehen. Dies schließt nicht aus, daß auch die Rückseite des Halbleiterchips aktive Strukturen aufweist. Unter den Begriffen "zentraler Bereich" und "zentrale Durchbruch" soll hier ein Bereich bzw. Durchbruch verstanden werden, der zumindest auf einer Seite (und vorzugsweise auf zwei Seiten oder sogar auf allen vier Seiten) einen erheblichen Abstand von den Seitenrändern des Halbleiterchips aufweist. Die Erwähnung eines zentralen Durchbruchs soll die Existenz weiterer Durchbrüche nicht ausschließen, obwohl in bevorzugten Ausführungsformen nur ein einziger Durchbruch vorgesehen ist.In the housing according to the invention, an interposer with a central opening is provided. In connection with semiconductor chips, which likewise have a centrally arranged bond island region, considerably shorter line lengths (in particular with regard to the bond wires) are therefore possible than in the prior art. This reduces disturbing capacities and inductances, so that the semiconductor component can be operated at higher frequencies. The housing according to the invention can be designed to be very compact and, above all, flat, although adequate mechanical protection for the semiconductor chip is nevertheless made possible. In addition, the thermal-mechanical stress on the semiconductor component can be significantly reduced by the invention. In the choice of words used here, the “front side” of a semiconductor chip is to be understood as its structured side (side with active structures). This does not exclude that the back of the semiconductor chip also has active structures. The terms “central area” and “central breakthrough” are to be understood here to mean an area or breakthrough that is at least on one side (and preferably on two sides or even on all four sides) a considerable distance from the side edges of the semiconductor chip. The mention of a central breakthrough is not intended to exclude the existence of further breakthroughs, although only one breakthrough is provided in preferred embodiments.
In einer bevorzugten Ausgestaltung sind die Kontaktinseln und/oder Anschlüsse für die Außenkontaktierung auf mindestens oder genau zwei Seiten des zentralen Durchbruchs angeordnet. Dies ermöglicht eine hohe Anzahl von Anschlüssen bei geringer Baugröße. Eine besonders hohe mechanische Stabilität wird erreicht, wenn der Interposer auf mindestens zwei Seiten des Durchbruchs flächig mit dem Halbleiterchip verklebt ist.In a preferred embodiment, the contact islands and / or connections for the external contact are arranged on at least or exactly two sides of the central opening. This enables a large number of connections with a small size. A particularly high mechanical stability is achieved if the interposer is glued flat to the semiconductor chip on at least two sides of the opening.
Bei einer weiteren Ausgestaltung der Erfindung ist das auf dem Interposer befe- stigte Halbleiterchip zu dessen Umhüllung zumindest teilweise von einem Glob Top (Vergußmasse) umgeben, wobei die Vergußmasse bevorzugt lediglich die Kanten des Halbleiterchips umschließt. Vorzugsweise erfolgt der seitliche mechanische Schutz des Halbleiterchips ausschließlich durch den Interposer und das Glob Top bzw. die Vergußmasse; es ist also insbesondere keine sonstige Platine vorgesehen, in die das Halbleiterchip eingebettet ist. Das Glob Top bzw. die Vergußmasse weisen vorzugsweise eine erhebliche Dicke auf, die sich zum Seitenrand des Interposers hin nur geringfügig verringert. Insbesondere kann auch am Seitenrand des Interposers die Dicke des Glob Tops bzw. der Vergußmasse noch mindestens 75 % oder mindestens 50 % der Dicke des Halbleiterchips betragen.In a further embodiment of the invention, the semiconductor chip attached to the interposer is at least partially surrounded by a glob top (encapsulation compound) to encase it, the encapsulation compound preferably only enclosing the edges of the semiconductor chip. The lateral mechanical protection of the semiconductor chip is preferably carried out exclusively by the interposer and the glob top or the sealing compound; in particular, no other circuit board is provided in which the semiconductor chip is embedded. The glob top or the potting compound preferably have a considerable thickness, which decreases only slightly towards the side edge of the interposer. In particular, the thickness of the glob top or the sealing compound can also be at least 75% or at least 50% of the thickness of the semiconductor chip on the side edge of the interposer.
In einer bevorzugten Ausführungsform ist der Interposer hinsichtlich seiner Außenabmessungen (d.h., ohne Berücksichtigung des mindestens einen Durchbruchs) flächenmäßig größer als das Halbleiterchip. Der Durchbruch kann eine langgestreckte Form aufweisen und mit einer Vergußmasse verfüllt sein. Die durch den Durchbruch geführten Drahtbrücken sind vorzugsweise vollständig eingehüllt und dadurch besonders gut gegen Beschädigung geschützt. Eine Lötstopmaske oder eine andere Barriere kann als Seitenbegrenzung für die Vergußmasse dienen.In a preferred embodiment, the interposer is larger in terms of area than the semiconductor chip in terms of its external dimensions (ie without taking into account the at least one opening). The opening can have an elongated shape and can be filled with a casting compound. The through the Breakthrough wire bridges are preferably completely encased and are therefore particularly well protected against damage. A solder mask or other barrier can serve as a side limitation for the sealing compound.
Der Interposer besteht bevorzugt aus einem üblichen Leiterplattenmaterial oder Material mit leiterplattenähnlichen Eigenschaften. Wichtige Kriterien für die Materialwahl sind eine gute mechanische Bearbeitbarkeit und gute Eigenschaften (z.B. Formstabilität) auch bei höheren Temperaturen. Die dem Halbleiterchip des Interposers zugewandte Seite ist vorzugsweise flach, wodurch eine gute Kiebeverbin- düng bei geringem Fertigungsaufwand erreicht wird. Bevorzugt ragt der Interposer seitlich nur wenig über das Halbleiterchip hinaus (z.B. höchstens 10 mm oder höchstens 5 mm oder höchstens 2 mm oder höchstens 1 mm).The interposer preferably consists of a conventional printed circuit board material or material with properties similar to printed circuit boards. Important criteria for the choice of material are good machinability and good properties (e.g. dimensional stability) even at higher temperatures. The side facing the semiconductor chip of the interposer is preferably flat, as a result of which a good joint connection is achieved with little manufacturing effort. The interposer preferably protrudes only slightly laterally beyond the semiconductor chip (for example at most 10 mm or at most 5 mm or at most 2 mm or at most 1 mm).
Die auf dem Interposer befindlichen Außenanschlüsse können als kugel- oder halbkugelförmige Kontaktelemente (z.B. Lotkugeln) oder als Kontaktelemente mit konvexer Oberfläche (z.B. Polymerhügel) oder in Form von kleinen Lotdepots ausgebildet sein, so daß damit eine einfache Montage des Halbleiterbauelements beispielsweise auf Leiterplatten ermöglicht wird.The external connections located on the interposer can be designed as spherical or hemispherical contact elements (e.g. solder balls) or as contact elements with a convex surface (e.g. polymer bump) or in the form of small solder deposits, so that the semiconductor component can be easily mounted, for example on printed circuit boards.
Auf der Rückseite des Halbleiterchips kann in manchen Ausführungsformen ein Kühlkörper montiert sein. In anderen Ausführungsformen weist die Rückseite ebenfalls aktive Strukturen auf, und Drahtbrücken sind von Bondinseln dieser aktiven Strukturen zum Interposer geführt. Ein derartiges zweiseitiges Halbleiterchip kann insbesondere aus zwei üblichen, einseitigen Halbleiterchips bestehen, die an ihren Rückseiten miteinander verbunden (insbesondere verklebt) sind. Die Ausgestaltungen mit einem zweiseitigen Halbleiterchip werden auch als eigenständige Erfindung angesehen, bei der die Positionen der Bondinseln auf der Vorder- und Rückseite des Halbleiterchips und des entsprechenden Durchbruchs im Interposer keine wesentlichen Merkmale darstellen.In some embodiments, a heat sink can be mounted on the back of the semiconductor chip. In other embodiments, the back also has active structures, and wire bridges are led from bond pads of these active structures to the interposer. Such a two-sided semiconductor chip can in particular consist of two customary, single-sided semiconductor chips which are connected (in particular glued) to one another on their rear sides. The configurations with a two-sided semiconductor chip are also regarded as an independent invention, in which the positions of the bond pads on the front and back of the semiconductor chip and the corresponding opening in the interposer do not constitute any significant features.
In bevorzugten Ausführungsformen wird eine Vielzahl von Halbleiterbauelementen aus einer Interposerplatte gefertigt. Insbesondere kann dabei vorgesehen sein, die Halbleiterbauelemente erst nach dem Aufbringen eines Glob Tops oder einer Vergußmasse zu trennen und zu individualisieren. Das erfindungsgemäße Halbleiterbauelement weist ein an sich bekanntes Halbleiterchip mit einem zentralen Bondinselbereich und eine Häusung gemäß der Erfindung auf. Das erfindungsgemäße Speichermodul ist unter Verwendung mehrerer solcher Halbleiterbauelemente gebildet. Das Speichermodul kann beispielsweise gemäß der Intel PC SDRAM Spezifikation und/oder der JEDEC-Spezifikation 21-C, Abschnitt 4: "Multi-Chip Memory Modules & Cards" ausgestaltet sein (verfügbar unter http://developer.intel.com/design/chipsets/memory/sdram.htm bzw. http://www.jedec.org/download/pub21/default.htm).In preferred embodiments, a large number of semiconductor components are manufactured from an interposer plate. In particular, it can be provided that the semiconductor components are separated and individualized only after a glob top or a sealing compound has been applied. The semiconductor component according to the invention has a semiconductor chip known per se with a central bond island region and a package according to the invention. The memory module according to the invention is formed using several such semiconductor components. The memory module can, for example, be designed in accordance with the Intel PC SDRAM specification and / or the JEDEC specification 21-C, section 4: "Multi-Chip Memory Modules &Cards" (available at http://developer.intel.com/design/ chipsets / memory / sdram.htm or http://www.jedec.org/download/pub21/default.htm).
In bevorzugten Weiterbildungen sind das erfindungsgemäße Halbleiterbauelement und/oder das Speichermodul und/oder das Herstellungsverfahren mit Merkmalen weitergebildet, die den gerade beschriebenen und/oder in den abhängigen Vorrichtungsansprüchen genannten Merkmalen entsprechen. Vorzugsweise weist das Speichermodul eine Leiterplatte als Trägerplatine für mehrere Halbleiterbauelemente auf, und das Material dieser Leiterplatte entspricht dem für die Interposer verwendeten Material.In preferred developments, the semiconductor component according to the invention and / or the memory module and / or the production method are developed with features that correspond to the features just described and / or mentioned in the dependent device claims. The memory module preferably has a printed circuit board as a carrier board for a plurality of semiconductor components, and the material of this printed circuit board corresponds to the material used for the interposers.
Weitere Merkmale, Vorteile und Aufgaben der Erfindung gehen aus der folgenden detaillierten Beschreibung mehrerer Ausführungsbeispiele und Ausführungsalternativen hervor. Es wird auf die schematischen Zeichnungen verwiesen, in denen zeigen:Further features, advantages and objects of the invention will become apparent from the following detailed description of several exemplary embodiments and alternative embodiments. Reference is made to the schematic drawings, in which:
Fig. 1 eine Draufsicht auf ein Halbleiterbauelement mit einer Häusung nach einem ersten Ausführungsbeispiel der Erfindung,1 is a plan view of a semiconductor device with a housing according to a first embodiment of the invention,
Fig. 2 eine Schnittdarstellung des in Fig. 1 gezeigten Halbleiterbauelements entlang der Linie II - II,FIG. 2 shows a sectional illustration of the semiconductor component shown in FIG. 1 along the line II-II,
Fig. 3 eine Schnittdarstellung ähnlich wie in Fig. 2 in einem leicht abgewandelten Ausführungsbeispiel,3 shows a sectional illustration similar to that in FIG. 2 in a slightly modified exemplary embodiment,
Fig. 4 eine Draufsicht auf eine Interposerplatte zur Herstellung von fünfundzwanzig Interposem, Fig. 5 eine vergrößerte Schnittdarstellung entlang der Linie V - V in Fig. 4 in einer späteren Stufe des Fertigungsprozesses,4 shows a plan view of an interposer plate for producing twenty-five interposers, 5 is an enlarged sectional view along the line V - V in Fig. 4 in a later stage of the manufacturing process,
Fig. 6 eine auseinandergezogene Darstellung einiger Bestandteile der erfindungsgemäßen Häusung in einem leicht variierten Ausführungsbeispiel der Erfindung, und6 is an exploded view of some components of the housing according to the invention in a slightly varied embodiment of the invention, and
Fig. 7 eine Schnittdarstellung ähnlich wie in Fig. 2 in einem weiteren Ausführungs- beispiel der Erfindung.7 shows a sectional illustration similar to that in FIG. 2 in a further exemplary embodiment of the invention.
Das in Fig. 1 und Fig. 2 gezeigte Halbleiterbauelement weist ein Halbleiterchip 10 mit einer erfindungsgemäßen Häusung auf. Das Halbleiterchip 10 hat eine Vorderseite 12 mit aktiven Strukturen, beispielsweise einem integrierten Speicherfeld, und eine der Vorderseite gegenüberliegende Rückseite 14. An einem zentralen Bereich 16 der Vorderseite 12 ist das Halbleiterchip 10 mit Bondinseln 18 (Pads) versehen, die zentral in einer Reihe angeordnet sind. In Ausführungsalternativen können die Bondinseln 18 auch in mehreren Reihen angeordnet sein, die parallel oder auch rechtwinklig zueinander verlaufen.The semiconductor component shown in FIGS. 1 and 2 has a semiconductor chip 10 with a housing according to the invention. The semiconductor chip 10 has a front side 12 with active structures, for example an integrated memory field, and a rear side 14 opposite the front side. At a central region 16 of the front side 12, the semiconductor chip 10 is provided with bonding pads 18 (pads) which are arranged centrally in a row are. In alternative embodiments, the bond pads 18 can also be arranged in several rows that run parallel or at right angles to one another.
Über dem Halbleiterchip 10 befindet sich ein Interposer 20, der aus einem Leiterplattenmaterial mit ebener Vorder- und Rückseite 22, 24 besteht. Das Halbleiterchip 10, genauer dessen Vorderseite 12, ist durch eine Klebeverbindung fest und flächig mit der Rückseite 24 des Interposers 20 verbunden. Dies ist aufgrund der guten thermischen Anpassung von Halbleiterchip 10 und Interposer 20 möglich. Über dem zentralen Bondinselbereich 16 des Halbleiterchips 10 weist der Interposer 20 einen zentral angeordneten Durchbruch 26 auf, der die Gestalt eines langgestreckten, an den beiden Schmalseiten abgerundeten Spalts oder Rechtecks hat.Above the semiconductor chip 10 there is an interposer 20, which consists of a printed circuit board material with a flat front and rear side 22, 24. The semiconductor chip 10, more precisely its front side 12, is firmly and flatly connected to the rear side 24 of the interposer 20 by an adhesive connection. This is possible due to the good thermal adaptation of the semiconductor chip 10 and interposer 20. Above the central bond island region 16 of the semiconductor chip 10, the interposer 20 has a centrally arranged opening 26 which has the shape of an elongated gap or rectangle rounded on the two narrow sides.
Um eine gute mechanische Stabilität und eine gute Schutzwirkung für das Halbleiterchip 20 zu gewährleisten, trennt der Durchbruch 26 den Interposer 20 nicht vollständig. Vielmehr sind die beiden Seitenbereiche des Interposers 20, die sich über den bondinselfreien Bereichen des Halbleiterchips 10 befinden, durch zwei Anbindungen an je einer Schmalseite des Durchbruchs 26 miteinander verbunden.In order to ensure good mechanical stability and a good protective effect for the semiconductor chip 20, the opening 26 does not completely separate the interposer 20. Rather, the two side areas of the interposer 20 are the are located above the bond island-free regions of the semiconductor chip 10, connected to one another by two connections on each narrow side of the opening 26.
Der Interposer 20 dient zum elektrischen Anschluß des Halbleiterbauelements an eine Leiterplatte und ist deshalb an seiner Vorderseite 22 mit Außenanschlüssen 30 versehen, die in Form von Feldern (Arrays) auf beiden Seiten des Durchbruchs 26 (also z.B. in Fig. 1 rechts bzw. links der Längsseiten des Durchbruchs 26) angeordnet sind. Die Außenanschlüsse 30 sind im hier beschriebenen Ausführungsbeispiel als Lotkugeln (Micro Balls) ausgestaltet, die sich auf Kontaktflächen 32 befinden. In Ausführungsalternativen können statt der Lotkugeln auch Polymerhügel oder Lotdepots als Außenanschlüsse 30 dienen.The interposer 20 is used for the electrical connection of the semiconductor component to a printed circuit board and is therefore provided on its front side 22 with external connections 30 which are in the form of arrays on both sides of the opening 26 (for example in FIG Long sides of the opening 26) are arranged. In the exemplary embodiment described here, the external connections 30 are configured as solder balls (micro balls) which are located on contact surfaces 32. In alternative embodiments, polymer bumps or solder deposits can also serve as external connections 30 instead of the solder balls.
Die Kontaktflächen 32 für die Außenanschlüsse 30 befinden sich an der Vorderseite 22 des Interposers 20. Die Kontaktflächen 32 sind mit Leitbahnen 34 verbun- den, die zu zentralen Kontaktinseln 36 verlaufen. Die Leitbahnen 34 sind dabei sowohl auf der Oberfläche als auch im inneren Volumen des Interposers 20 geführt (in der Zeichnung sind beispielhaft nur einige wenige Leitbahnen 34 dargestellt). Mit anderen Worten ist der Interposer 20 also als mehrlagige (z.B. zwei-, vier- oder sechslagige) Leiterplatte mit den erforderlichen Durchkontaktierungen ausgestaltet. Die Leitbahnen 34 sind im hier beschriebenen Ausführungsbeispiel als Kupferleitbahnen ausgebildet und im Interesse einer besseren Kontaktierbar- keit auf der Oberfläche vergoldet. Die zentralen Kontaktinseln 36 sind seitlich unmittelbar neben dem Durchbruch 26 im Interposer 20 angeordnet, also z.B. in Fig. 1 rechts bzw. links der Längsseite des Durchbruchs 26.The contact surfaces 32 for the external connections 30 are located on the front side 22 of the interposer 20. The contact surfaces 32 are connected to interconnects 34 which run to central contact islands 36. The interconnects 34 are guided both on the surface and in the inner volume of the interposer 20 (only a few interconnects 34 are shown in the drawing by way of example). In other words, the interposer 20 is thus designed as a multi-layer (e.g. two, four or six-layer) printed circuit board with the necessary plated-through holes. In the exemplary embodiment described here, the interconnects 34 are designed as copper interconnects and gold-plated on the surface in the interest of better contactability. The central contact islands 36 are arranged laterally directly next to the opening 26 in the interposer 20, e.g. 1 to the right or left of the long side of the opening 26.
Drahtbrücken 40 (Bonddrähte) sind durch den Durchbruch 26 von je einer Bondinsel 18 des Halbleiterchips 10 zu je einer zentralen Kontaktinsel 36 rechts oder links des Durchbruchs 26 gezogen. Als Material für die Drahtbrücken 40 dient Gold- oder Aluminiumdraht. Die Drahtbrücken 40 verlaufen dabei von der Reihe der Bondinseln 18 abwechselnd zu einer linken bzw. rechten Kontaktinsel 36, so daß die Gefahr einer unerwünschten Berührung und Verbindung zwischen zwei Drahtbrücken 40 vermieden wird. Der Durchbruch 26 ist so angeordnet, daß er sich genau über den Bondinseln 18 befindet und einen für den Bondvorgang ausreichenden Bereich um die Reihe der Bondinseln 18 freihält. Der Durchbruch 26 ist mit einer an sich bekannten Vergußmasse 42 gefüllt, die auch die Drahtbrücken 40 umhüllt und gegen Beschädigungen schützt. Die Vergußmasse 42 bildet einen im Querschnitt pilzförmigen Pfropfen mit leicht konvex gewölbter Kappe (Fig. 2). Damit die Montage des Halbleiterbauelements nicht behindert wird, ragt der Pfropfen nur wenig über die Vorderseite 22 des Interposers 20 hinaus. Aus diesem Grund müssen auch die Drahtbrücken 40 relativ dicht an der Oberfläche der Kontaktinseln 36 geführt werden.Wire bridges 40 (bonding wires) are pulled through the opening 26 from one bonding island 18 of the semiconductor chip 10 to one central contact island 36 to the right or left of the opening 26. Gold or aluminum wire is used as the material for the wire bridges 40. The wire bridges 40 run alternately from the row of bond pads 18 to a left or right contact pad 36, so that the risk of undesired contact and connection between two wire bridges 40 is avoided. The opening 26 is arranged such that it is located exactly above the bond pads 18 and keeps an area around the row of bond pads 18 that is sufficient for the bonding process. The opening 26 is filled with a potting compound 42 known per se, which also encases the wire bridges 40 and protects them against damage. The potting compound 42 forms a plug which is mushroom-shaped in cross section and has a slightly convex cap (FIG. 2). So that the assembly of the semiconductor component is not hindered, the plug protrudes only slightly beyond the front side 22 of the interposer 20. For this reason, the wire bridges 40 must also be guided relatively close to the surface of the contact islands 36.
Eine Lötstopmaske 44 bedeckt die Vorderseite 22 des Interposers 20, wobei die Kontaktflächen 32 und ein innerer Bereich 46 freigehalten werden. Der freigehaltene Bereich 46 umfaßt den Durchbruch 26 und die daran anschließenden Kontaktinseln 36. Die Lötstopmaske 44 ist deutlich dicker, als dies für die reine Funktion des Schutzes vor flüssigem Lot erforderlich wäre. Dadurch bilden die Ränder der Lötstopmaske 44 am freigehaltenen Bereich 46 eine Begrenzung für die Vergußmasse 42. Der durch die Vergußmasse 42 gebildete Pfropfen erhält somit eine definierte Form. Überdies ist eine vollständige Abdeckung der Drahtbrücken 40 sichergestellt, wenn die Vergußmasse 42 bis zum oberen Rand der Lötstopmaske 42 in den Durchbruch 26 und den freigehaltenen Bereich 46 eingefüllt wird. In Aus- führungsalternativen ist statt oder zusätzlich zu der Lötstopmaske 44 eine andere Barriere als Begrenzung für die Vergußmasse 42 vorgesehen, beispielsweise ein Wulst oder ein Strang aus einem anderen Material.A solder mask 44 covers the front 22 of the interposer 20, the contact surfaces 32 and an inner region 46 being kept free. The area 46 which is kept free comprises the opening 26 and the adjoining contact islands 36. The solder mask 44 is significantly thicker than would be necessary for the pure function of protection against liquid solder. As a result, the edges of the solder mask 44 on the area 46 which is kept free form a boundary for the sealing compound 42. The plug formed by the sealing compound 42 thus has a defined shape. In addition, complete coverage of the wire bridges 40 is ensured when the potting compound 42 is filled into the opening 26 and the area 46 kept free up to the upper edge of the solder mask 42. In alternative embodiments, instead of or in addition to the solder mask 44, another barrier is provided as a limitation for the sealing compound 42, for example a bead or a strand made of another material.
Im hier beschriebenen Ausführungsbeispiel ist die Dicke der Lötstopmaske 44 am Bereich um die Kontaktflächen 32 ungefähr gleich der Dicke der Kontaktflächen 32. Mit anderen Worten weist der Übergang an der Grenze zwischen den Kontaktflächen 32 und der Lötstopmaske 44 nur einen geringen Höhenunterschied auf (z.B. weniger als 0,2 mm oder weniger als 0,1 mm). Durch diese Maßnahme wird verhindert, daß bei einer seitlichen Belastung der Außenanschlüsse 30 ein heraus- ragender Rand der Lötstopmaske 44 wie ein Hebelansatzpunkt wirkt, wobei der gebildete Hebel eine verstärkte Kraft auf die Verbindung zwischen den Kontaktflächen 32 und den Außenanschlüssen 30 ausüben würde. Eine solche seitliche Belastung kann beispielsweise durch eine unterschiedliche Wärmeausdehnung des Interposers 20 und einer Leiterplatte, auf die das gesamte Halbleiterbauteil aufgelötet ist, hervorgerufen werden. Die Leitbahnen 34 und die Kontaktinseln 36 sind dagegen im hier beschriebenen Ausführungsbeispiel deutlich dünner als die Kontaktflächen 32 bzw. die Lötstopmaske 44. Dadurch wird erstens verhindert, daß sich die Lötstopmaske 44 über den Leitbahnen 34 emporwölbt. Zweitens verbleibt dadurch zwischen den Oberseiten der Kontaktinseln 36 und dem oberen Rand des freigehaltenen Bereichs 46 genügend Raum für die Drahtbrücken 40 und die diese Drahtbrücken 40 bedeckende Vergußmasse 42. In Ausführungsalternativen sind die Kontaktflächen 32, die Leitbahnen 34 und die Kontaktinseln 36 dagegen ungefähr gleich dick.In the exemplary embodiment described here, the thickness of the solder mask 44 at the area around the contact surfaces 32 is approximately equal to the thickness of the contact surfaces 32. In other words, the transition at the boundary between the contact surfaces 32 and the solder mask 44 has only a slight difference in height (for example less than 0.2 mm or less than 0.1 mm). This measure prevents a protruding edge of the solder mask 44 from acting as a lever attachment point when the external connections 30 are subjected to a lateral load, the lever being formed exerting an increased force on the connection between the contact surfaces 32 and the external connections 30. Such a lateral load can be caused, for example, by a different thermal expansion of the interposer 20 and a printed circuit board on which the entire semiconductor component is soldered. In contrast, in the exemplary embodiment described here, the interconnects 34 and the contact islands 36 are significantly thinner than the contact surfaces 32 or the solder mask 44. This firstly prevents the solder mask 44 from arching up above the interconnects 34. Secondly, this leaves enough space between the tops of the contact islands 36 and the upper edge of the area 46 which is kept free for the wire bridges 40 and the casting compound 42 covering these wire bridges 40. In alternative embodiments, the contact surfaces 32, the interconnects 34 and the contact islands 36 are approximately the same thickness .
Der Interposer 20 weist eine etwas größere Fläche als das Halbleiterchip 10 auf und ragt auf jeder Seite etwa 0,5 mm über den Seitenrand des Halbleiterchips 10 hinaus. In dem Winkel, der jeweils zwischen der Seitenwand des Halbleiterchips 10 und dem überstehenden Abschnitt des Interposers 20 gebildet ist, befindet sich Vergußmasse, die ein Glob Top 50 bildet. Im hier beschriebenen Ausführungsbeispiel werden von dem Glob Top 50 lediglich die Seiten des Halbleiterchips 10 umschlossen, während in Ausführungsalternativen das Glob Top 50 das Halbleiterchip 10 auch auf dessen Rückseite 14 umgibt oder zumindest zum Teil abdeckt. Durch die Kombination des (geringen) Überstands des Interposers 20 mit dem Glob Top 50 wird ein guter mechanischer Schutz bei geringer Baugröße (insbesondere geringer Bauhöhe) erreicht.The interposer 20 has a somewhat larger area than the semiconductor chip 10 and projects on each side about 0.5 mm beyond the side edge of the semiconductor chip 10. At the angle that is formed in each case between the side wall of the semiconductor chip 10 and the projecting section of the interposer 20, there is potting compound that forms a glob top 50. In the exemplary embodiment described here, only the sides of the semiconductor chip 10 are enclosed by the glob top 50, while in alternative embodiments the glob top 50 also surrounds the semiconductor chip 10 or at least partially covers the rear side 14 thereof. By combining the (small) protrusion of the interposer 20 with the Glob Top 50, good mechanical protection is achieved with a small overall size (in particular a low overall height).
Im hier beschriebenen Ausführungsbeispiel ist das Glob Top 50 unmittelbar am Halbleiterchip 10 ungefähr so dick wie das Halbleiterchip 10. Zur Seite hin fällt die Dicke des Glob Tops 50 etwas, aber nicht wesentlich ab. Diese Form bietet einen besonders guten seitlichen Schutz des Halbleiterchips 10. Sie wird dadurch erreicht, daß nach dem unten noch genauer beschriebenen Herstellungsverfahren das Glob Top 50 für mehrere Halbleiterbausteine schon vor der Vereinzelung dieser Bausteine aufgetragen wird.In the exemplary embodiment described here, the glob top 50 directly on the semiconductor chip 10 is approximately as thick as the semiconductor chip 10. To the side, the thickness of the glob top 50 drops somewhat, but not significantly. This form offers a particularly good lateral protection of the semiconductor chip 10. It is achieved in that the Glob Top 50 for several semiconductor components is applied before the separation of these components using the manufacturing method described in more detail below.
Das in Fig. 3 gezeigte Ausführungsbeispiel entspricht dem bisher beschriebenen. Es sind lediglich einige Komponenten anders dimensioniert. So sind halbkugelförmige Außenanschlüsse 30 vorgesehen, und der seitliche Überstand des Interposers 20 über das Halbleiterchip 10 ist größer. Der wichtigste Unterschied ist, daß die Dicke des Glob Tops 50 zum Rand des Interposers 20 hin bis auf praktisch Null abnimmt.The embodiment shown in Fig. 3 corresponds to that previously described. Only a few components are dimensioned differently. Thus, hemispherical external connections 30 are provided, and the lateral protrusion of the interposer 20 over the semiconductor chip 10 is greater. The main difference is that the thickness of the glob top 50 decreases towards the edge of the interposer 20 to practically zero.
Im folgenden wird ein Ausführungsbeispiel eines Herstellungsverfahrens beschrieben, mit dem sich mehrere erfindungsgemäße Häusungen und Halbleiterbauelemente gleichzeitig und kostengünstig herstellen lassen. Dieses Verfahren geht von einer in Fig. 4 gezeigten Interposerplatte 60 aus, auf der mehrere (in Fig. 4 fünfundzwanzig) Interposer 20 mit geringem Abstand zueinander ausgebildet werden.An exemplary embodiment of a production method is described below, with which several housings and semiconductor components according to the invention can be produced simultaneously and inexpensively. This method is based on an interposer plate 60 shown in FIG. 4, on which a plurality of (twenty-five in FIG. 4) interposers 20 are formed at a short distance from one another.
Die Interposerplatte 60 besteht aus einem leiterplattenähnlichen Material, das auch für typische Trägerplatinen eingesetzt wird, z.B. einem der als FR4-Epoxy oder FR5-Epoxy oder BT bekannten Materialien. Für jeden der späteren Interposer 20 wird ein Durchbruch 26 in die Interposerplatte 60 eingearbeitet, beispielsweise durch Fräsen oder Stanzen. Außerdem wird auf der Vorderseite der Interposerplatte 60 für jeden späteren Interposer 20 die Lötstopmaske 44 aufgetragen, wobei die Kontaktflächen 32 und der Bereich 46 freigehalten werden. Um eine besonders dicke Lötstopmaske 44 zu erhalten, wird in Ausführungsvarianten entweder ein spezieller Lötstoplack verwendet, oder es werden mehrere (vorzugsweise zwei) Lackschichten aufgetragen.The interposer plate 60 is made of a circuit board-like material that is also used for typical carrier boards, e.g. one of the materials known as FR4-Epoxy or FR5-Epoxy or BT. For each of the later interposers 20, an opening 26 is machined into the interposer plate 60, for example by milling or punching. In addition, the solder mask 44 is applied to the front of the interposer plate 60 for each subsequent interposer 20, the contact surfaces 32 and the region 46 being kept free. In order to obtain a particularly thick solder mask 44, either a special solder resist is used in design variants, or several (preferably two) layers of lacquer are applied.
Nun wird hinter jeden Durchbruch 26 ein Halbleiterchip 10 aufgeklebt, so daß sich der Durchbruch 26 genau über den Bondinseln 18 befindet. Als Klebstoff wird ein an sich bekanntes Epoxy-Harz verwendet. In einem folgenden Schritt wird die elektrische Verbindung in Form der Drahtbrücken 40 durch ein an sich bekanntes Bond-Verfahren hergestellt, wobei die Drahtbrücken 40 je eines Halbleiterbauteils durch den entsprechenden Durchbruch 26 hindurch von den Bondinseln 18 zu den Kontaktinseln 36 gezogen werden. Nach dem Bonden wird die Vergußmasse 42 in jeden Durchbruch 26 der Interposerplatte 60 und in den daran anschließenden, freigehaltenen Bereich 46 der Lötstopmaske 44 gefüllt. Die Drahtbrücken 40 werden dadurch vollständig von der Vergußmasse 42 eingehüllt und so fixiert und geschützt. Vor oder nach dem Vergießen der Durchbrüche 26 werden die Glob Tops 50 aufgebracht. Dazu kann die gleiche Vergußmasse wie für die Durchbrüche 26 oder ein anderes Material verwendet werden. Im hier beschriebenen Ausführungsbeispiel umschließen die Glob Tops 50 lediglich die Kanten der Halbleiterchips 10. Dies reicht zur Hermetisierung (Schutz vor Feuchtigkeit) und zum mechanischen Schutz aus. Bei dem hier beschriebenen Verfahren wird die Glob-Top-Masse oder eine andere Vergußmasse in die Zwischenräume zwischen den Halbleiterchips 10 an der Rückseite der noch zusammenhängenden Interposerplatte 60 gefüllt. Die Zwischenräume werden zumindest zum großen Teil ausgefüllt, so daß die Glob- Top-Masse eine nur leicht konkave oder sogar konvexe Oberfläche aufweist. Dieser Zustand ist in der Schnittdarstellung von Fig. 5 gezeigt.A semiconductor chip 10 is now glued on behind each opening 26, so that the opening 26 is located exactly above the bonding pads 18. An epoxy resin known per se is used as the adhesive. In a subsequent step, the electrical connection in the form of the wire bridges 40 is established by a bonding method known per se, the wire bridges 40 of each semiconductor component being pulled through the corresponding opening 26 from the bonding pads 18 to the contact pads 36. After bonding, the casting compound 42 is filled into each opening 26 of the interposer plate 60 and into the adjoining, kept free area 46 of the solder mask 44. The wire bridges 40 are thereby completely enveloped by the potting compound 42 and thus fixed and protected. The glob tops 50 are applied before or after the openings 26 are cast. For this purpose, the same casting compound as for the openings 26 or another material can be used. In the exemplary embodiment described here, the glob tops 50 only enclose the edges of the semiconductor chips 10. This is sufficient for hermeticization (protection against moisture) and for mechanical protection. In the method described here, the glob-top compound or another casting compound is filled into the spaces between the semiconductor chips 10 on the rear side of the interposer plate 60, which is still connected. The gaps are at least largely filled, so that the glob-top mass has only a slightly concave or even convex surface. This state is shown in the sectional view of FIG. 5.
Nach dem Aushärten der Glob-Top-Masse werden die Häusungen getrennt, indem die Interposerplatte 60 an Trennbereichen 62 durchschnitten wird (z.B. durch Sägen oder mittels eines Lasers). Die Trennbereiche 62, die in Fig. 4 und Fig. 5 durch gestrichelte Linien angedeutet sind, verlaufen mit geringem Abstand von den Seiten der Halbleiterchips 10 durch die vergossenen Zwischenräume zwischen den Halbleiterchips 10. Der genannte Abstand bestimmt den Überhang des Interposers 20 bei dem fertiggestellten Bauteil und beträgt beispielsweise 0,5 mm. Bei der Trennung werden die Interposerplatte 60 und die darauf befindliche Glob- Top-Masse durchschnitten. Die so gebildeten Halbleiterbauelemente werden nun individualisiert. Während in Ausführungsalternativen die Außenanschlüsse 30 erst jetzt auf die Kontaktflächen 32 aufgebracht werden (z.B. durch Siebdruck oder ein Lotschwallverfahren), findet dieser Schritt im hier beschriebenen Ausführungs- beispiel noch vor der Trennung der Interposerplatte 60, aber nach dem Aufbringen der Lötstopmaske 44 statt.After the glob-top mass has hardened, the housings are separated by cutting the interposer plate 60 at separation areas 62 (for example by sawing or using a laser). The separation regions 62, which are indicated in FIG. 4 and FIG. 5 by dashed lines, run at a short distance from the sides of the semiconductor chips 10 through the encapsulated gaps between the semiconductor chips 10. The distance mentioned determines the overhang of the interposer 20 in the finished one Component and is, for example, 0.5 mm. During the separation, the interposer plate 60 and the glob top mass located thereon are cut through. The semiconductor components formed in this way are now individualized. While, in alternative embodiments, the external connections 30 are only now being applied to the contact surfaces 32 (for example by screen printing or a solder wave process), in the exemplary embodiment described here this step takes place before the interposer plate 60 is separated, but after the solder mask 44 has been applied.
Bei der sehr schematischen, perspektivischen Darstellung von Fig. 6 ist in einem leicht abgewandelten Ausführungsbeispiel nochmals das Halbleiterchip 10 und der Interposer 20 gezeigt. Letzterer ist noch Bestandteil der Interposerplatte 60. Die Außenanschlüsse 30 sind schon angebracht.6, the semiconductor chip 10 and the interposer 20 are shown again in a slightly modified exemplary embodiment. The latter is still part of the interposer plate 60. The external connections 30 are already attached.
Die in Fig. 7 dargestellte Ausführungsalternative beruht auf der bisher ausführlich beschriebenen Anordnung. Diese Ausführungsalternative ist als Häusung für Halb- leiterchips 10 geeignet, die auf ihrer Vorder- und Rückseite 12, 14 aktive Strukturen und jeweils zugeordnete Bondinseln 18, 19 aufweisen. Solche Halbleiterchips 10 können durch beidseitiges Herausbilden der aktiven Strukturen auf einem Träger (Die) gebildet werden. In dem in Fig. 6 dargestellten Ausführungsbeispiel besteht der Halbleiterchip 10 jedoch aus zwei Chipelementen 70, 72, die ihrerseits übliche Halbleiterchips mit jeweils einer aktiven Seite (Vorderseite) und einer Rückseite sind. Die Chipeiemente 70, 72 sind an ihren Rückseiten zusammengeklebt.The alternative embodiment shown in FIG. 7 is based on the arrangement previously described in detail. This alternative is designed as a housing for half Suitable conductor chips 10, which have on their front and back 12, 14 active structures and associated bond pads 18, 19. Such semiconductor chips 10 can be formed by forming the active structures on both sides on a carrier (die). In the exemplary embodiment shown in FIG. 6, however, the semiconductor chip 10 consists of two chip elements 70, 72, which in turn are conventional semiconductor chips, each with an active side (front side) and a rear side. The chip elements 70, 72 are glued together on their rear sides.
Gemäß der Ausführungsalternative von Fig. 7 weist der Interposer 20 weitereAccording to the alternative embodiment of FIG. 7, the interposer has 20 more
Leitbahnen 74 auf, die den Interposer 20 durchdringen und die Kontaktflächen 32 auf der Vorderseite 12 des Interposers 20 auf geeignete Weise mit Kontaktinseln 76 auf der Rückseite des Interposers 20 verbinden. Die Kontaktinseln 76 sind am Rand des Interposers 20 in dem überstehenden, nicht vom Halbleiterchip 10 bedeckten Bereich angeordnet. Von den Kontaktinseln 76 sind Drahtbrücken 78 zu Kontaktinseln 36 auf der Rückseite 14 des Halbleiterchips 10 (Vorderseite des Chipelements 72) gezogen. Die Drahtbrücken 78 können sich am Rand oder in einem zentralen Bereich der Rückseite 14 befinden. Ein Glob Top 50 oder eine andere geeignete Schutzumhüllung umschließt das Halbleiterchip 10 und die Drahtbrücken 78.Conductors 74 which penetrate the interposer 20 and connect the contact surfaces 32 on the front 12 of the interposer 20 in a suitable manner with contact islands 76 on the rear of the interposer 20. The contact islands 76 are arranged on the edge of the interposer 20 in the protruding area which is not covered by the semiconductor chip 10. Wire bridges 78 are drawn from the contact islands 76 to contact islands 36 on the rear side 14 of the semiconductor chip 10 (front side of the chip element 72). The wire bridges 78 can be located on the edge or in a central region of the rear side 14. A glob top 50 or another suitable protective covering encloses the semiconductor chip 10 and the wire bridges 78.
Die in der obigen Beschreibung von Ausführungsbeispielen enthaltenen Einzelheiten sollen nicht als Einschränkungen des Schutzbereichs der Erfindung aufgefaßt werden, sondern vielmehr als Beispiele von bevorzugten Ausführungs- formen. Viele andere Abwandlungen sind möglich und für den Fachmann offensichtlich. Der Bereich der Erfindung soll deshalb nicht durch die dargestellten Ausführungsbeispiele bestimmt werden, sondern durch die anhängenden Ansprüche und ihre Äquivalente. The details contained in the above description of exemplary embodiments are not to be interpreted as limitations on the scope of protection of the invention, but rather as examples of preferred embodiments. Many other modifications are possible and obvious to the person skilled in the art. The scope of the invention should therefore not be determined by the exemplary embodiments shown, but rather by the appended claims and their equivalents.

Claims

Patentansprüche claims
1. Häusung für ein Halbleiterchip (10), bei der - das Halbleiterchip (10) mit seiner Vorderseite (12) über eine Klebeverbindung mit einem Interposer (20) verbunden ist, der Interposer (20) einen zentralen Durchbruch (26) über einem zentralen Bondinselbereich (16) des Halbleiterchips (10) aufweist, der Interposer (20) Leitbahnen (34) aufweist, die einerseits über Kontakt- inseln (36) und Drahtbrücken (40) mit Bondinseln (18) des Halbleiterchips (10) und andererseits mit Anschlüssen (30) für die Außenkontaktierung verbunden sind, und die Drahtbrücken (40) zwischen den Bondinseln (18) auf dem Halbleiterchip (10) und den Kontaktinseln (36) auf dem Interposer (20) gezogen sind und durch den zentralen Durchbruch (26) verlaufen.1. Housing for a semiconductor chip (10), in which - the semiconductor chip (10) is connected with its front side (12) via an adhesive connection to an interposer (20), the interposer (20) has a central opening (26) above a central one Has bond island region (16) of the semiconductor chip (10), the interposer (20) has interconnects (34) which on the one hand via contact islands (36) and wire bridges (40) with bond islands (18) of the semiconductor chip (10) and on the other hand with connections (30) for the external contact, and the wire bridges (40) between the bond pads (18) on the semiconductor chip (10) and the contact pads (36) on the interposer (20) are drawn and run through the central opening (26) .
2. Häusung nach Anspruch 1 , dadurch gekennzeichnet, daß die Kontaktinseln (36) und/oder die Anschlüsse (30) für die Außenkontaktierung auf mindestens zwei Seiten des zentralen Durchbruchs (26) des Interposers (20) angeordnet sind.2. Housing according to claim 1, characterized in that the contact islands (36) and / or the connections (30) for the external contact are arranged on at least two sides of the central opening (26) of the interposer (20).
3. Häusung nach Anspruch 1 oder Anspruch 2, dadurch gekennzeichnet, daß die Kontaktinseln (36) auf zwei Seiten des zentralen Durchbruchs (26) angeordnet sind, und daß die Bondinseln (18) des Halbleiterchips (10) zentral in wenigstens einer Reihe angeordnet sind, und daß die Drahtbrücken (40) zwischen den Bond- inseln (18) und wechselseitig zu je einer Kontaktinsel (36) auf einer bzw. der anderen Seite des zentralen Durchbruchs (26) gezogen sind.3. Housing according to claim 1 or claim 2, characterized in that the contact islands (36) are arranged on two sides of the central opening (26), and that the bonding islands (18) of the semiconductor chip (10) are arranged centrally in at least one row , and that the wire bridges (40) between the bond pads (18) and alternately to a contact pad (36) on one or the other side of the central opening (26) are drawn.
4. Häusung nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, daß das Halbleiterchip (10) auf mindestens einer Seite oder mindestens zwei Seiten des zentralen Durchbruchs (26) flächig mit dem Interposer (20) verklebt ist.4. Housing according to one of claims 1 to 3, characterized in that the semiconductor chip (10) on at least one side or at least two sides of the central opening (26) is glued flat to the interposer (20).
5. Häusung nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, daß das auf dem Interposer (20) befestigte Halbleiterchip (10) zumindest teilweise mit einem Glob Top (50) oder einer Vergußmasse umgeben ist. 5. Housing according to one of claims 1 to 4, characterized in that the semiconductor chip (10) attached to the interposer (20) is at least partially surrounded by a glob top (50) or a sealing compound.
6. Häusung nach Anspruch 5, dadurch gekennzeichnet, daß das Glob Top (50) bzw. die Vergußmasse die Kanten des Halbleiterchips (10) umschließt.6. Housing according to claim 5, characterized in that the glob top (50) or the sealing compound surrounds the edges of the semiconductor chip (10).
7. Häusung nach Anspruch 5 oder Anspruch 6, dadurch gekennzeichnet, daß als seitliche Schutzeinrichtungen für das Halbleiterchip (10) ausschließlich der Interposer (20) und das Glob Top (50) bzw. die Vergußmasse vorgesehen sind.7. Housing according to claim 5 or claim 6, characterized in that only the interposer (20) and the glob top (50) or the sealing compound are provided as lateral protective devices for the semiconductor chip (10).
8. Häusung nach einem der Ansprüche 5 bis 7, dadurch gekennzeichnet, daß die Dicke des Glob Tops (50) bzw. der Vergußmasse am Seitenrand des Interposers (20) mindestens 75 % oder mindestens 50 % der Dicke des Halbleiterchips (10) beträgt.8. Housing according to one of claims 5 to 7, characterized in that the thickness of the glob top (50) or the sealing compound on the side edge of the interposer (20) is at least 75% or at least 50% of the thickness of the semiconductor chip (10).
9. Häusung nach einem der Ansprüche 1 bis 8, dadurch gekennzeichnet, daß der Interposer (20) flächenmäßig größer ist als das Halbleiterchip (10) und/oder hinsichtlich der Seitenabmessungen geringfügig größer ist als das Halbleiterchip (10) und/oder seitlich höchstens 10 mm oder höchstens 5 mm oder höchstens 2 mm oder höchstens 1 mm über die Seitenränder des Halbleiterchips (10) hervorragt.9. Housing according to one of claims 1 to 8, characterized in that the interposer (20) is larger in area than the semiconductor chip (10) and / or in terms of the side dimensions is slightly larger than the semiconductor chip (10) and / or laterally at most 10 mm or at most 5 mm or at most 2 mm or at most 1 mm protrudes beyond the side edges of the semiconductor chip (10).
10. Häusung nach einem der Ansprüche 1 bis 9, dadurch gekennzeichnet, daß die dem Halbleiterchip (10) zugewandte Seite des Interposers (20) im wesentlichen eben ist.10. Housing according to one of claims 1 to 9, characterized in that the side of the interposer (20) facing the semiconductor chip (10) is substantially flat.
11. Häusung nach einem der Ansprüche 1 bis 10, dadurch gekennzeichnet, daß der zentrale Durchbruch (26) mit einer Vergußmasse (42) verfüllt ist, welche gleichzeitig die Drahtbrücken (40) einhüllt.11. Housing according to one of claims 1 to 10, characterized in that the central opening (26) is filled with a casting compound (42) which simultaneously envelops the wire bridges (40).
12. Häusung nach Anspruch 11 , dadurch gekennzeichnet, daß die Vorderseite (22) des Interposers (20) eine Lötstopmaske (44) oder eine sonstige Barriere mit einem zentralen, freigehaltenen Bereich (46) aufweist, der den Durchbruch (26) des Interposers (20) umgibt und eine seitliche Begrenzung für die Vergußmasse (42) bildet. 12. Housing according to claim 11, characterized in that the front side (22) of the interposer (20) has a solder mask (44) or another barrier with a central, kept free area (46) which has the opening (26) of the interposer ( 20) surrounds and forms a lateral boundary for the sealing compound (42).
13. Häusung nach einem der Ansprüche 1 bis 12, dadurch gekennzeichnet, daß die Leitbahnen (34) des Interposers (20) über Kontaktflächen (32) mit den Anschlüssen (30) für die Außenkontaktierung verbunden sind, und daß die Dicke der Kontaktflächen (32) geringer als die Dicke der Kontaktinseln (36) und/oder der Leitbahnen (34) ist.13. Housing according to one of claims 1 to 12, characterized in that the interconnects (34) of the interposer (20) are connected via contact surfaces (32) to the connections (30) for the external contact, and that the thickness of the contact surfaces (32 ) is less than the thickness of the contact islands (36) and / or the interconnects (34).
14. Häusung nach einem der Ansprüche 1 bis 13, dadurch gekennzeichnet, daß das Halbleiterchip (10) über die Klebeverbindung unmittelbar mit dem Interposer (20) verbunden ist, und/oder daß der Interposer (20) mindestens den bondinsel- freien Bereich des Halbleiterchips (10) überdeckt.14. Housing according to one of claims 1 to 13, characterized in that the semiconductor chip (10) via the adhesive connection is directly connected to the interposer (20), and / or that the interposer (20) at least the bond island-free area of the semiconductor chip (10) covered.
15. Häusung nach einem der Ansprüche 1 bis 14, dadurch gekennzeichnet, daß der Interposer (20) aus einem Material mit leiterplattenähnlichen thermo-mechani- schen Eigenschaften besteht, insbesondere aus dem Material der Leiterplatte, auf der die Häusung montiert werden soll.15. Housing according to one of claims 1 to 14, characterized in that the interposer (20) consists of a material with circuit board-like thermo-mechanical properties, in particular from the material of the circuit board on which the housing is to be mounted.
16. Häusung nach einem der Ansprüche 1 bis 15, dadurch gekennzeichnet, daß die auf dem Interposer (20) befindlichen Außenanschlüsse (30) als Lotkugeln und/oder als Polymerhügel und/oder in Form von Lotdepots ausgebildet sind.16. Housing according to one of claims 1 to 15, characterized in that the external connections (30) located on the interposer (20) are designed as solder balls and / or as polymer bumps and / or in the form of solder deposits.
17. Häusung nach einem der Ansprüche 1 bis 16, dadurch gekennzeichnet, daß die Rückseite (14) des Halbleiterchips (10) unmittelbar mit einem Kühlkörper verbunden ist.17. Housing according to one of claims 1 to 16, characterized in that the back (14) of the semiconductor chip (10) is connected directly to a heat sink.
18. Häusung nach einem der Ansprüche 1 bis 17, dadurch gekennzeichnet, daß bei der Herstellung mehrere Interposer (20) auf einer gemeinsamen Interposerplatte (60) ausgebildet sind und daß die Interposerplatte (60) nach dem Aufkleben der Halbleiterchips (10) in einzelne Halbleiterbauelemente teilbar ist.18. Housing according to one of claims 1 to 17, characterized in that in the manufacture of a plurality of interposers (20) are formed on a common interposer plate (60) and that the interposer plate (60) after gluing the semiconductor chips (10) into individual semiconductor components is divisible.
19. Häusung nach Anspruch 18 und einem der Ansprüche 5 bis 8, dadurch gekennzeichnet, daß die Interposerplatte (60) erst nach dem Aufbringen des Glob Top (50) bzw. der Vergußmasse in einzelne Halbleiterbauelemente geteilt worden ist. 19. Housing according to claim 18 and one of claims 5 to 8, characterized in that the interposer plate (60) has only been divided into individual semiconductor components after the application of the glob top (50) or the sealing compound.
20. Häusung nach einem der Ansprüche 1 bis 19, dadurch gekennzeichnet, daß das Halbleiterchip (10) auch auf seiner Rückseite (14) aktive Strukturen aufweist, und daß Drahtbrücken (40) von auf der Rückseite (14) des Halbleiterchips (10) angeordneten Bondinseln (19) zum Interposer (20) geführt sind.20. Housing according to one of claims 1 to 19, characterized in that the semiconductor chip (10) also has active structures on its rear side (14), and that wire bridges (40) are arranged on the rear side (14) of the semiconductor chip (10) Bond islands (19) to the interposer (20) are guided.
21. Häusung nach Anspruch 20, dadurch gekennzeichnet, daß das Halbleiterchip (10) aus zwei an ihren Rückseiten verbundenen Chipelementen (70, 72) besteht, wobei die Vorderseite des ersten Chipelements (70) die Vorderseite (12) des Halbleiterchips (10) bildet und die Vorderseite des zweiten Chipelements (72) die Rückseite des Halbleiterchips (10) bildet.21. Housing according to claim 20, characterized in that the semiconductor chip (10) consists of two chip elements (70, 72) connected on their rear sides, the front side of the first chip element (70) forming the front side (12) of the semiconductor chip (10) and the front of the second chip element (72) forms the back of the semiconductor chip (10).
22. Halbleiterbauelement mit einem Halbleiterchip (10) und einer Häusung nach einem der Ansprüche 1 bis 21.22. A semiconductor device with a semiconductor chip (10) and a package according to one of claims 1 to 21.
23. Speichermodul mit mehreren Halbleiterbauelementen, die jeweils eine Häusung nach einem der Ansprüche 1 bis 21 aufweisen.23. Memory module with a plurality of semiconductor components, each having a housing according to one of claims 1 to 21.
24. Speichermodul nach Anspruch 23, dadurch gekennzeichnet, daß das Speichermodul eine Leiterplatte aus demselben Material wie die Interposer (20) der Halbleiterbaueiemente aufweist.24. Memory module according to claim 23, characterized in that the memory module has a circuit board made of the same material as the interposer (20) of the semiconductor components.
25. Verfahren zur Herstellung eines Halbleiterbauelements, insbesondere mit einer Häusung nach einem der Ansprüche 1 bis 21 , mit den Schritten:25. A method for producing a semiconductor component, in particular with a housing according to one of claims 1 to 21, comprising the steps:
Bereitstellen einer Interposerplatte (60) mit einer Vielzahl von Durchbrüchen (26),Providing an interposer plate (60) with a plurality of openings (26),
Aufkleben einer Vielzahl von Halbleiterchips (10) mit ihrer Vorderseite (12) auf die Interposerplatte (60), so daß je ein zentraler Bondinselbereich (16) jedes Halbleiterchips (10) unter je einem Durchbruch (26) der Interposerplatte (60) angeordnet ist, - Herstellen von Drahtbrücken (40) zwischen den Bondinseln (18) der zentralen Bondinselbereiche (16) der Halbleiterchips (10) und zugeordneten Kontaktinseln (36) auf der Interposerplatte (60), wobei die Drahtbrücken (40) durch die Durchbrüche (26) der Interposerplatte (60) gezogen werden, Vergießen der Durchbrüche (26) der Interposerplatte (60) sowie der Zwischenräume zwischen den Halbleiterchips (10), undGluing a large number of semiconductor chips (10) with their front side (12) onto the interposer plate (60), so that a central bond island region (16) of each semiconductor chip (10) is arranged under each opening (26) in the interposer plate (60), - Production of wire bridges (40) between the bond pads (18) of the central bond pad areas (16) of the semiconductor chips (10) and associated contact islands (36) on the interposer plate (60), the wire bridges (40) through the openings (26) of the Interposer plate (60) are pulled, Potting the openings (26) of the interposer plate (60) and the spaces between the semiconductor chips (10), and
Trennen der Interposerplatte (60) an den vergossenen Zwischenräumen zwischen den Halbleiterchips (10). Separating the interposer plate (60) at the potted spaces between the semiconductor chips (10).
PCT/EP2000/000678 1999-02-16 2000-01-28 Packaging for a semiconductor chip WO2000048444A2 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
EP0810655A2 (en) * 1996-05-29 1997-12-03 Texas Instruments Incorporated A package for a semiconductor device
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
GB2320616A (en) * 1996-12-18 1998-06-24 Hyundai Electronics Ind Semiconductor chip package
US5858815A (en) * 1996-06-21 1999-01-12 Anam Semiconductor Inc. Semiconductor package and method for fabricating the same
EP0915505A1 (en) * 1997-11-06 1999-05-12 Sharp Kabushiki Kaisha Semiconductor device package, manufacturing method thereof and circuit board therefor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0428260A (en) * 1990-05-23 1992-01-30 Matsushita Electric Ind Co Ltd Method of mounting semiconductor chip
JP3146849B2 (en) * 1994-05-27 2001-03-19 松下電器産業株式会社 Electronic component and method of manufacturing electronic component
JPH09260441A (en) * 1996-03-26 1997-10-03 Mitsubishi Electric Corp Semiconductor device
JPH1154537A (en) * 1997-07-31 1999-02-26 Mitsui High Tec Inc Semiconductor device and its manufacture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5703405A (en) * 1993-03-15 1997-12-30 Motorola, Inc. Integrated circuit chip formed from processing two opposing surfaces of a wafer
US5674785A (en) * 1995-11-27 1997-10-07 Micron Technology, Inc. Method of producing a single piece package for semiconductor die
EP0810655A2 (en) * 1996-05-29 1997-12-03 Texas Instruments Incorporated A package for a semiconductor device
US5858815A (en) * 1996-06-21 1999-01-12 Anam Semiconductor Inc. Semiconductor package and method for fabricating the same
GB2320616A (en) * 1996-12-18 1998-06-24 Hyundai Electronics Ind Semiconductor chip package
EP0915505A1 (en) * 1997-11-06 1999-05-12 Sharp Kabushiki Kaisha Semiconductor device package, manufacturing method thereof and circuit board therefor

Non-Patent Citations (6)

* Cited by examiner, † Cited by third party
Title
AMAGAI M: "Chip scale package (CSP) solder joint reliability and modeling" , 2ND 1998 IEMT/IMC SYMPOSIUM (IEEE CAT. NO.98EX225), 2ND 1998 IEMT/IMC SYMPOSIUM, TOKYO, JAPAN, 15-17 APRIL 1998 , 1998, TOKYO, JAPAN, ORGANIZING COMMITTEE 1998 IEMT/IMC SYMPOSIUM, JAPAN, PAGE(S) 216 - 223 XP002136547 ISBN: 0-7803-5090-1 Seite 216 -Seite 217; Abbildungen 2,21 *
CHANCHANI R ET AL: "A NEW MINI BALL GRID ARRAY (MBGA) MULTICHIP MODULE TECHNOLOGY" INTERNATIONAL JOURNAL OF MICROCIRCUITS AND ELECTRONIC PACKAGING,US,INTERNATIONAL MICROELECTRONICS & PACKAGING SOCIETY, Bd. 18, Nr. 3, 1. Juli 1995 (1995-07-01), Seiten 185-192, XP000538985 ISSN: 1063-1674 *
PATENT ABSTRACTS OF JAPAN vol. 016, no. 196 (E-1200), 12. Mai 1992 (1992-05-12) -& JP 04 028260 A (MATSUSHITA ELECTRIC IND CO LTD), 30. Januar 1992 (1992-01-30) *
PATENT ABSTRACTS OF JAPAN vol. 1996, no. 04, 30. April 1996 (1996-04-30) -& JP 07 321244 A (MATSUSHITA ELECTRIC IND CO LTD), 8. Dezember 1995 (1995-12-08) *
PATENT ABSTRACTS OF JAPAN vol. 1998, no. 02, 30. Januar 1998 (1998-01-30) -& JP 09 260441 A (MITSUBISHI ELECTRIC CORP), 3. Oktober 1997 (1997-10-03) *
PATENT ABSTRACTS OF JAPAN vol. 1999, no. 05, 31. Mai 1999 (1999-05-31) -& JP 11 054537 A (MITSUI HIGH TEC INC), 26. Februar 1999 (1999-02-26) *

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