WO2000036652A2 - Method of manufacturing a gate electrode - Google Patents

Method of manufacturing a gate electrode Download PDF

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Publication number
WO2000036652A2
WO2000036652A2 PCT/US1999/027382 US9927382W WO0036652A2 WO 2000036652 A2 WO2000036652 A2 WO 2000036652A2 US 9927382 W US9927382 W US 9927382W WO 0036652 A2 WO0036652 A2 WO 0036652A2
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Prior art keywords
insulator
substrate
titanium
interfacial layer
semiconductor device
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PCT/US1999/027382
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French (fr)
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WO2000036652A3 (en
Inventor
Aniruddha B. Joshi
Lih-Jou Chung
Dim-Lee Kwong
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Conexant Systems, Inc.
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Publication of WO2000036652A2 publication Critical patent/WO2000036652A2/en
Publication of WO2000036652A3 publication Critical patent/WO2000036652A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02186—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing titanium, e.g. TiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material

Definitions

  • the present invention generally relates to semiconductor devices, and more particularly, to semiconductors having insulated gates.
  • Insulated gate semiconductors such as MOSFETs, dissipate less power than other types of components.
  • the insulated gate itself reduces the standby current of these components significantly.
  • MOS semiconductors include an insulator of silicon dioxide between the gate and the substrate.
  • the insulator electrically isolates the gate from the substrate to inhibit current.
  • Lower power applications demand aggressive power supply reduction. This, in turn, demands reduction in silicon insulator thickness to ensure adequate performance.
  • Thinner silicon dioxide insulators in semiconductors present operational and manufacturing problems.
  • thin silicon dioxide insulators (such as less than 25 Angstroms thick) tend to exhibit relatively high direct tunneling of electrons through the insulator, generating an undesirable standby current and reducing the overall efficiency of the semiconductor.
  • growing a uniform, high quality silicon dioxide insulator of such limited thickness is difficult and often results in high rejection rates for components.
  • dopants from the gate material, such as boron diffuse through thin silicon dioxide, which tend to adversely affect transistor behavior.
  • nitride and tantalum pentoxide have been used as insulating materials. Such materials, however, do not bond particularly well with the silicon, and electrical properties of the resulting structure are not adequate. Further, though nitride and tantalum pentoxide have higher dielectric constants than silicon dioxide, materials with even higher dielectric constants would allow the use of thicker, more manageable insulators.
  • a semiconductor device includes an insulator between an electrode and a substrate.
  • the semiconductor device may include an insulated gate component, such as a MOSFET.
  • the insulator is comprised of a material having a relatively high dielectric constant compared to silicon dioxide, such as titanium dioxide.
  • the titanium dioxide is suitably formed by initially depositing titanium (Ti) or titanium nitride (TiN). Exposure of this initial deposit to a suitable oxidizing ambient, such as a nitric oxide (NO), oxygen (O 2 ), or nitrous oxide (N 2 O), causes the formation of titanium dioxide.
  • a suitable oxidizing ambient such as a nitric oxide (NO), oxygen (O 2 ), or nitrous oxide (N 2 O)
  • Figure 1 illustrates the general structure of a MOSFET
  • FIG. 2 is a flow diagram depicting a method of manufacturing the MOSFET.
  • IGFET insulated gate field effect transistors
  • a semiconductor component comprises a semiconductor system, such as an IGFET, including an electrode separated from another electronic element by an insulator.
  • the semiconductor system comprises a metal-oxide- silicon field effect transistor (MOSFET) 100.
  • the MOSFET 100 suitably comprises a substrate 110, including a source 112, a drain 114, and a channel region 116; a gate 118; and an insulator 120.
  • the substrate 110 suitably comprises a conventional semiconductor substrate, comprising silicon, gallium arsenide, or any other appropriate semiconductor material.
  • the substrate 110 is doped, for example using conventional doping techniques or any other suitable technique, to form the channel region 116, the source 112, and the drain 114.
  • the MOSFET 100 is configured as an n channel depletion-mode MOSFET, having an n+ source 112, an n+ drain 114, and an n channel region 116 formed in a p substrate.
  • a semiconductor according to various aspects of the present invention may be configured, however, in any suitable manner, with any appropriate doping profile, and with any suitable variations in the size and doping density of the source 112, drain 114, and channel region 116 according to the desired characteristics of the semiconductor system and the applicable manufacturing process.
  • the transistor may a p channel MOSFET, and/or an enhancement-mode MOSFET.
  • the gate 118 and the insulator 120 are formed adjacent the channel region 116.
  • the insulator 120 is preferably sandwiched between the substrate 110 and the gate 118 to electrically insulate the substrate 110 from the gate 118, thus inhibiting current between the gate 118 and the substrate 110.
  • the gate 118 receives a selected charge from a control circuit (not shown) to generate a field across the channel region 116, thus affecting the electrical properties of the channel region 116. Consequently, the gate 118 may comprise any electrode and be comprised of any suitable material for receiving an electrical charge.
  • the gate 118 comprises a conductive material which effectively bonds to the underlying insulator 120.
  • the gate 118 suitably comprises a conventional gate 118 formed of a sheet of conventional gate materials, such as polysilicon, aluminum or titanium nitride.
  • the insulator 120 is disposed between the gate 118 and the underlying substrate 110 to inhibit transfer of charge to and from the channel region 116, thus substantially maintaining the selected charge on the gate 118 until the control circuit adjusts the charge.
  • the insulator 120 preferably underlies the entire bottom surface of the gate 118.
  • the insulator 120 suitably exhibits a relatively high dielectric constant compared to silicon dioxide (dielectric constant of about 3.9) or nitride (dielectric constant of about 7), for example a dielectric constant of about 30-100.
  • the insulator 120 includes titanium dioxide, and suitably is comprised substantially entirely of titanium dioxide. Titanium dioxide has a dielectric constant of about 30-100, which varies according to film stoichiometry. As described in further detail below, the insulator 120 layer is suitably formed by an initial layer of titanium or titanium nitride, which is then oxidized to form titanium dioxide. The thickness of the insulator 120 is selected according to any appropriate criteria, such as to maximize capacitance between the gate 118 and the underlying substrate 110, for example according to the following equation:
  • the MOSFET 100 may further include an interfacial layer 124 disposed between the substrate 110 and the insulator 120. The interfacial layer 124 tends to improve the physical and/or electrical bond between the substrate 110 and the insulator 120.
  • the interfacial layer 124 comprises a very thin layer, for example up to about 5 Angstroms, suitably comprising nitrogen rich silicon dioxide.
  • the interfacial layer 124 tends to provide a smoother material transition from the substrate 116 to the insulator 120. The smooth transition tends to ensure adequate behavior of the MOSFET 100.
  • the source 112, drain 114, and gate 118 are connected to other circuitry (not shown), suitably via conventional connections 122A, 122B, such as aluminum, copper, or suicide connections formed according to conventional techniques.
  • the other circuitry may selectively apply electrical potentials and charges to the gate 118, source 112, and drain 114 to affect the operation of the MOSFET 100.
  • the substrate 110 is initially prepared to form the channel 116 (step 210).
  • the substrate may be prepared according to any appropriate technique, such as ion implantation.
  • the substrate 110 may be cleaned to remove surface debris and chemicals from the surface of the substrate 110 (step 212), such as in accordance with conventional cleaning methods.
  • the substrate 110 is then suitably annealed (step 214).
  • the annealing process in the present embodiment forms the interfacial layer 124 between the substrate 110 and the insulator 120.
  • the annealing process suitably comprises exposing the substrate 110 to a selected substance, such as a nitric oxide (NO) or ammonia ambient, to form a very thin interfacial layer 124 of about 5 Angstroms, for example comprised of nitrogen rich silicon dioxide.
  • a selected substance such as a nitric oxide (NO) or ammonia ambient
  • the pre-insulating material is deposited on the interfacial layer, or if the annealing step is omitted, the substrate 110 (step 216).
  • the pre-insulating material initially comprises titanium or titanium nitride.
  • the pre-insulating material may be deposited using any suitable technique, such as chemical vapor deposition, plasma deposition, reactive sputtering, thermal decomposition of titanium compounds, or any other appropriate deposition technique.
  • the pre-insulating material may be transformed into the insulator 120 (step 218). Transformation of the insulator 120 comprises suitably treating the pre-insulating material to form the insulator 120.
  • the titanium or titanium nitride pre-insulating material is exposed to an oxidizing agent to form a titanium dioxide insulator 120.
  • An appropriate method of forming titanium dioxide comprises exposing the titanium or titanium nitride to an oxidizing ambient, such as NO or O2 or N2O, at a temperature in the range of about 600-1000 degrees C, and preferably in the range of about 700-900 degrees C. As the oxidizing ambient reacts with the titanium or titanium nitride, titanium dioxide forms.
  • This reaction is substantially self-limiting, because it ends when the starting titanium or titanium nitride is substantially consumed by the oxidation process.
  • the particular temperature and duration at which the pre-insulating material is exposed to the oxidizing ambient may vary considerably without significantly affecting the transformation process.
  • the substrate 110 and insulator 120 may be subjected to a final bake (step 220).
  • the final baking process improves the performance stability of the MOSFET 100.
  • the final baking process tends to reduce the drift of the MOSFET's 100 electrical properties, in case the insulator 120 is continuous, i.e., not isolated for individual MOSFETs.
  • the bake endures for a duration in the range of about 20-40 minutes, more preferably of about 30 minutes, at a temperature in the range of 350-500 degrees Celsius, and more preferably in the range of 400-450 degrees Celsius.
  • the gate 118 is formed on top of the insulator 120 (step 222).
  • the gate 118 holds a selected amount of charge, which is controlled by a control circuit, which creates an electric field and affects the electrical properties of the channel region 116.
  • the gate 118 may comprise any suitable conductive material, such as polysilicon, aluminum or TiN.
  • the gate 118 may be formed in any suitable manner, such as conventional gate deposition techniques.
  • the MOSFET 100 of the present embodiment includes the gate 118, it should be noted that various aspects of the present invention may be applied to any electrode intended to be electrically insulated from a substrate by an insulator.
  • Source 112, drain 114, and electrical connections 122 may then be formed (step 224). If necessary, the gate 118 may be connected to the respective elements of a control circuit. To complete the package, an external insulating layer, such as oxide or nitride, may then be applied around the entire MOSFET 100 except for the electrical connections to electrically insulate the MOSFET 100 from subsequent processing which may involve formation of connections among MOSFETs (step 226).
  • an external insulating layer such as oxide or nitride
  • a semiconductor component according to various aspects of the present invention provides various desirable characteristics over conventional components. Due to the high dielectric value of the titanium dioxide, thicker layers of titanium dioxide can generate the similar electrical properties of much thinner silicon dioxide insulators. The manufacturing aspects of such thicker layers are simpler. In addition, thicker layers of titanium dioxide are less subject to direct tunneling than silicon dioxide layers providing the same electrical properties, thus tending to reduce the standby current in the component. Further, the self-regulating aspect of the titanium dioxide formation from titanium or titanium nitride provides for simpler manufacturing, and the addition of the interfacial layer provides improved interface control and operational properties.

Abstract

A semiconductor device includes an insulator between an electrode and a substrate. For example, the semiconductor device may include an insulated gate component, such as a MOSFET. The insulator is comprised of a material having a relatively high dielectric constant compared to silicon dioxide, such as titanium dioxide. The titanium dioxide is suitably formed by initially depositing titanium nitride. The titanium nitride may be exposed to an oxidizing ambient, such as nitric oxide ambient. The titanium nitride reacts with nitric oxide to form titanium dioxide.

Description

METHODS AND APPARATUS FOR MANUFACTURING SEMICONDUCTORS
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, to semiconductors having insulated gates.
2. Description of the Related Art
The expanding market for small and portable components, such as computers and cellular telephones, has demanded new and more efficient designs in power supplies and power conservation. Though battery manufacturers have dramatically improved the lifetime and power delivery of small batteries, electronics manufacturers have also attempted to reduce the power consumed by their products. Accordingly, many manufacturers design systems around low power electronic components, such as 1.8, 2.5, or 3.3 volt transistors instead of the conventional 5 volt transistors.
To accommodate lower power consumption, many designers use insulated gate semiconductor components. Insulated gate semiconductors, such as MOSFETs, dissipate less power than other types of components. The insulated gate itself reduces the standby current of these components significantly.
Lower power insulated gate components, however, are subject to limitations. Conventional MOS semiconductors include an insulator of silicon dioxide between the gate and the substrate. The insulator electrically isolates the gate from the substrate to inhibit current. Lower power applications demand aggressive power supply reduction. This, in turn, demands reduction in silicon insulator thickness to ensure adequate performance.
Thinner silicon dioxide insulators in semiconductors present operational and manufacturing problems. For example, thin silicon dioxide insulators (such as less than 25 Angstroms thick) tend to exhibit relatively high direct tunneling of electrons through the insulator, generating an undesirable standby current and reducing the overall efficiency of the semiconductor. In addition, growing a uniform, high quality silicon dioxide insulator of such limited thickness is difficult and often results in high rejection rates for components. A further concern is that dopants from the gate material, such as boron, diffuse through thin silicon dioxide, which tend to adversely affect transistor behavior.
To address these and other problems associated with thin insulators in MOS semiconductors, the use of alternative insulating materials has been explored. For example, nitride and tantalum pentoxide (Ta2O5) have been used as insulating materials. Such materials, however, do not bond particularly well with the silicon, and electrical properties of the resulting structure are not adequate. Further, though nitride and tantalum pentoxide have higher dielectric constants than silicon dioxide, materials with even higher dielectric constants would allow the use of thicker, more manageable insulators.
SUMMARY OF THE INVENTION A semiconductor device includes an insulator between an electrode and a substrate. For example, the semiconductor device may include an insulated gate component, such as a MOSFET. The insulator is comprised of a material having a relatively high dielectric constant compared to silicon dioxide, such as titanium dioxide. The titanium dioxide is suitably formed by initially depositing titanium (Ti) or titanium nitride (TiN). Exposure of this initial deposit to a suitable oxidizing ambient, such as a nitric oxide (NO), oxygen (O2), or nitrous oxide (N2O), causes the formation of titanium dioxide.
BRIEF DESCRIPTION OF THE DRAWINGS
The subject matter of the invention is particularly pointed out and distinctly claimed in the concluding portion of the specification. The invention, however, both as to organization and method of operation, may best be understood by reference to the following description taken in conjunction with the claims and the accompanying drawing, in which like parts may be referred to by like numerals:
Figure 1 illustrates the general structure of a MOSFET; and
Figure 2 is a flow diagram depicting a method of manufacturing the MOSFET. DETAILED DESCRIPTION OF THE PREFERRED EXEMPLARY EMBODIMENTS The subject matter of the present invention is particularly suited for use in connection with semiconductor devices, such as insulated gate field effect transistors (IGFETs). As a result, the preferred exemplary embodiment of the present invention is described in that context. It should be recognized, however, that such description is not intended as a limitation on the use or applicability of the present invention, but is instead provided merely to enable a full and complete description of a preferred embodiment. On the contrary, various aspects of the present invention may be applied to a wide array of semiconductor systems and manufacturing processes. Referring now to Figure 1 , a semiconductor component according to various aspects of the present invention comprises a semiconductor system, such as an IGFET, including an electrode separated from another electronic element by an insulator. In the present exemplary embodiment, the semiconductor system comprises a metal-oxide- silicon field effect transistor (MOSFET) 100. The MOSFET 100 suitably comprises a substrate 110, including a source 112, a drain 114, and a channel region 116; a gate 118; and an insulator 120. The substrate 110 suitably comprises a conventional semiconductor substrate, comprising silicon, gallium arsenide, or any other appropriate semiconductor material. The substrate 110 is doped, for example using conventional doping techniques or any other suitable technique, to form the channel region 116, the source 112, and the drain 114. In the present embodiment, the MOSFET 100 is configured as an n channel depletion-mode MOSFET, having an n+ source 112, an n+ drain 114, and an n channel region 116 formed in a p substrate. A semiconductor according to various aspects of the present invention may be configured, however, in any suitable manner, with any appropriate doping profile, and with any suitable variations in the size and doping density of the source 112, drain 114, and channel region 116 according to the desired characteristics of the semiconductor system and the applicable manufacturing process. For example, the transistor may a p channel MOSFET, and/or an enhancement-mode MOSFET.
In the present embodiment, the gate 118 and the insulator 120 are formed adjacent the channel region 116. The insulator 120 is preferably sandwiched between the substrate 110 and the gate 118 to electrically insulate the substrate 110 from the gate 118, thus inhibiting current between the gate 118 and the substrate 110. The gate 118 receives a selected charge from a control circuit (not shown) to generate a field across the channel region 116, thus affecting the electrical properties of the channel region 116. Consequently, the gate 118 may comprise any electrode and be comprised of any suitable material for receiving an electrical charge. Preferably, the gate 118 comprises a conductive material which effectively bonds to the underlying insulator 120. In the present embodiment, the gate 118 suitably comprises a conventional gate 118 formed of a sheet of conventional gate materials, such as polysilicon, aluminum or titanium nitride. The insulator 120 is disposed between the gate 118 and the underlying substrate 110 to inhibit transfer of charge to and from the channel region 116, thus substantially maintaining the selected charge on the gate 118 until the control circuit adjusts the charge. To more fully insulate the gate 118 from the substrate 110, the insulator 120 preferably underlies the entire bottom surface of the gate 118. Further, the insulator 120 suitably exhibits a relatively high dielectric constant compared to silicon dioxide (dielectric constant of about 3.9) or nitride (dielectric constant of about 7), for example a dielectric constant of about 30-100. In the present embodiment, the insulator 120 includes titanium dioxide, and suitably is comprised substantially entirely of titanium dioxide. Titanium dioxide has a dielectric constant of about 30-100, which varies according to film stoichiometry. As described in further detail below, the insulator 120 layer is suitably formed by an initial layer of titanium or titanium nitride, which is then oxidized to form titanium dioxide. The thickness of the insulator 120 is selected according to any appropriate criteria, such as to maximize capacitance between the gate 118 and the underlying substrate 110, for example according to the following equation:
C = Ae t where C is the capacitance, A is the area of the gate 118, e is the dielectric constant of the insulator 120, and t is the thickness of the insulator 120. Because the dielectric constant of the insulator 120 material is preferably higher than that of silicon dioxide or nitride, the thickness of the insulator 120 in the present embodiment is typically significantly greater than the thickness of silicon dioxide or nitride insulators providing comparable capacitances. In some embodiments, the MOSFET 100 may further include an interfacial layer 124 disposed between the substrate 110 and the insulator 120. The interfacial layer 124 tends to improve the physical and/or electrical bond between the substrate 110 and the insulator 120. In the present embodiment, the interfacial layer 124 comprises a very thin layer, for example up to about 5 Angstroms, suitably comprising nitrogen rich silicon dioxide. The interfacial layer 124 tends to provide a smoother material transition from the substrate 116 to the insulator 120. The smooth transition tends to ensure adequate behavior of the MOSFET 100.
The source 112, drain 114, and gate 118 are connected to other circuitry (not shown), suitably via conventional connections 122A, 122B, such as aluminum, copper, or suicide connections formed according to conventional techniques. The other circuitry may selectively apply electrical potentials and charges to the gate 118, source 112, and drain 114 to affect the operation of the MOSFET 100.
A semiconductor device according to various aspects of the present invention is manufactured according to any appropriate techniques and methods. Referring now to Figure 2, in the present embodiment, the substrate 110 is initially prepared to form the channel 116 (step 210). The substrate may be prepared according to any appropriate technique, such as ion implantation. Following formation of the channel 116, the substrate 110 may be cleaned to remove surface debris and chemicals from the surface of the substrate 110 (step 212), such as in accordance with conventional cleaning methods. The substrate 110 is then suitably annealed (step 214). The annealing process in the present embodiment forms the interfacial layer 124 between the substrate 110 and the insulator 120. The annealing process suitably comprises exposing the substrate 110 to a selected substance, such as a nitric oxide (NO) or ammonia ambient, to form a very thin interfacial layer 124 of about 5 Angstroms, for example comprised of nitrogen rich silicon dioxide.
Following the annealing, the pre-insulating material is deposited on the interfacial layer, or if the annealing step is omitted, the substrate 110 (step 216). In the present embodiment, the pre-insulating material initially comprises titanium or titanium nitride. The pre-insulating material may be deposited using any suitable technique, such as chemical vapor deposition, plasma deposition, reactive sputtering, thermal decomposition of titanium compounds, or any other appropriate deposition technique.
The pre-insulating material may be transformed into the insulator 120 (step 218). Transformation of the insulator 120 comprises suitably treating the pre-insulating material to form the insulator 120. For example, in the present embodiment, the titanium or titanium nitride pre-insulating material is exposed to an oxidizing agent to form a titanium dioxide insulator 120. An appropriate method of forming titanium dioxide comprises exposing the titanium or titanium nitride to an oxidizing ambient, such as NO or O2 or N2O, at a temperature in the range of about 600-1000 degrees C, and preferably in the range of about 700-900 degrees C. As the oxidizing ambient reacts with the titanium or titanium nitride, titanium dioxide forms. This reaction is substantially self-limiting, because it ends when the starting titanium or titanium nitride is substantially consumed by the oxidation process. The particular temperature and duration at which the pre-insulating material is exposed to the oxidizing ambient may vary considerably without significantly affecting the transformation process.
After transformation of the pre-insulating material into the insulator 120, the substrate 110 and insulator 120 may be subjected to a final bake (step 220). The final baking process improves the performance stability of the MOSFET 100. For example, the final baking process tends to reduce the drift of the MOSFET's 100 electrical properties, in case the insulator 120 is continuous, i.e., not isolated for individual MOSFETs. Preferably, the bake endures for a duration in the range of about 20-40 minutes, more preferably of about 30 minutes, at a temperature in the range of 350-500 degrees Celsius, and more preferably in the range of 400-450 degrees Celsius.
The gate 118 is formed on top of the insulator 120 (step 222). The gate 118 holds a selected amount of charge, which is controlled by a control circuit, which creates an electric field and affects the electrical properties of the channel region 116. Accordingly, the gate 118 may comprise any suitable conductive material, such as polysilicon, aluminum or TiN. In addition, the gate 118 may be formed in any suitable manner, such as conventional gate deposition techniques. Although the MOSFET 100 of the present embodiment includes the gate 118, it should be noted that various aspects of the present invention may be applied to any electrode intended to be electrically insulated from a substrate by an insulator.
Source 112, drain 114, and electrical connections 122 may then be formed (step 224). If necessary, the gate 118 may be connected to the respective elements of a control circuit. To complete the package, an external insulating layer, such as oxide or nitride, may then be applied around the entire MOSFET 100 except for the electrical connections to electrically insulate the MOSFET 100 from subsequent processing which may involve formation of connections among MOSFETs (step 226).
Thus, a semiconductor component according to various aspects of the present invention provides various desirable characteristics over conventional components. Due to the high dielectric value of the titanium dioxide, thicker layers of titanium dioxide can generate the similar electrical properties of much thinner silicon dioxide insulators. The manufacturing aspects of such thicker layers are simpler. In addition, thicker layers of titanium dioxide are less subject to direct tunneling than silicon dioxide layers providing the same electrical properties, thus tending to reduce the standby current in the component. Further, the self-regulating aspect of the titanium dioxide formation from titanium or titanium nitride provides for simpler manufacturing, and the addition of the interfacial layer provides improved interface control and operational properties.
Although the present invention has been described in conjunction with particular embodiments illustrated in the appended drawing figures, various modification may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: a substrate; an electrode; an insulator sandwiched between the electrode and the substrate, wherein the insulator includes titanium dioxide, and wherein the titanium dioxide does not form a continuous layer with a titanium suicide.
2. A semiconductor device according to claim 1 , wherein the titanium dioxide of the insulator is formed by oxidizing at least one of titanium and titanium nitride.
3. A semiconductor device according to claim 1 , further comprising an interfacial layer sandwiched between the insulator and the substrate.
4. A semiconductor device according to claim 3, wherein the interfacial layer comprises nitrogen rich oxide.
5. A semiconductor device according to claim 3, wherein the interfacial layer is formed by annealing.
6. A semiconductor device according to claim 5, wherein said annealing includes exposing the interfacial layer to at least one of NO and ammonia.
7. A semiconductor device according to claim 1 , wherein said semiconductor device is baked.
8. An insulated gate transistor, comprising: a substrate having a drain, a source, and a channel region between said drain and said source; a first electrical connection attached to said drain; a second electrical connection attached to said source; a gate adjacent said channel region; and an insulator sandwiched between said gate and said channel region, wherein said insulator is comprised of titanium dioxide, and wherein said first and second electrical connections are not formed of titanium silicide that forms a continuous layer with said insulator.
9. An insulated gate transistor according to claim 8, wherein the titanium dioxide of the insulator is formed by oxidizing at least one of titanium and titanium nitride.
10. An insulated gate transistor according to claim 8, further comprising an interfacial layer sandwiched between said insulator and said substrate.
11. An insulated gate transistor according to claim 10, wherein the interfacial layer comprises nitrogen rich oxide.
12. An insulated gate transistor according to claim 10, wherein the interfacial layer is formed by annealing.
13. An insulated gate transistor according to claim 12, wherein said annealing includes exposing the interfacial layer to at least one of NO and ammonia.
14. An insulated gate transistor according to claim 8, wherein said insulated gate transistor is baked.
15. A method of manufacturing a semiconductor device, comprising: providing a substrate; depositing a pre-insulating material on the substrate; transforming the pre-insulating material into an insulator; and depositing an electrode on the insulator.
16. A method according to claim 15, wherein the pre-insulating material comprises at least one of titanium and titanium nitride.
17. A method according to claim 16, wherein the step of transforming the pre- insulating material includes exposing the pre-insulating material to an oxidizing agent.
18. A method according to claim 17, wherein the oxidizing agent comprises at least one of nitric oxide, oxygen, and nitrous oxide.
19. A method according to claim 15, further comprising the step of forming an interfacial layer between the substrate and at least one of the pre-insulating material and the insulator.
20. A method according to claim 19, wherein the step of forming the interfacial layer includes annealing the interfacial layer.
21. A method according to claim 20, wherein the annealing step includes exposing the interfacial layer to at least one of NO and ammonia.
22. A method according to claim 15, further comprising the step of baking the semiconductor device.
PCT/US1999/027382 1998-12-15 1999-11-18 Method of manufacturing a gate electrode WO2000036652A2 (en)

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