WO2000031782A1

WO2000031782A1 - Silane-based oxide anti-reflective coating for patterning of metal features in semiconductor manufacturing

Info

Publication number: WO2000031782A1
Application number: PCT/US1999/014599
Authority: WO
Inventors: Sey-Ping Sun; Minh Van Ngo
Original assignee: Advanced Micro Devices, Inc.
Priority date: 1998-11-25
Filing date: 1999-06-28
Publication date: 2000-06-02
Also published as: EP1133788A1; KR20010086053A; JP2002530885A

Abstract

A silane-based oxide (40) having a thickness of about 300 nm or less is formed for use in an anti-reflective coating for patterning metal interconnects having small dimensions (e.g., 0.18 micron or less) and large aspect ratios. The oxide (40) is formed in such a way that it does not react with a popular deep ultraviolet photoresist (38). The reaction, known as 'footing' (18), can result in a loss of the intended feature dimensions. In one embodiment of the method, the silane-based oxide (40) is deposited using a non-nitrogen carrier gas for the silane. In an alternate embodiment, a nitrogen carrier gas is used and the oxide (40) is subsequently exposed to an N2O plasma (2). The resulting oxide (40) can be made using a low-cost, high-throughput, and low-defect process as compared to other oxide formation methods.

Description

TITLE: SILANE-BASED OXIDE AΝTI-REFLECTIVE COATING FOR PATTERNING OF

METAL FEATURES IN SEMICONDUCTOR MANUFACTURING

BACKGROUND OF THE INVENTION

1. Technical Field

This invention relates to integrated circuit fabrication, and more particularly to a method for patterning high-aspect-ratio metal features, such as interconnects having dimensions of 0.18 micron or less.

2. Background Art

Integrated circuits include a large number of transistors fabricated into a monolithic semiconductor substrate. Isolation structures such as field oxides or shallow trench dielectrics are used to electrically isolate the individual transistors from one another. The transistors are then selectively coupled to other transistors or to contact pads to achieve a desired circuit through the use of patterned layers of conductors. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide ("oxide"). Conductors are thereby lithographically patterned across the semiconductor topography, wherein the topography includes a dielectric placed over the semiconductor substrate. The conductors are made from an electrically conductive material, suitable materials including metals, doped polysilicon, metal suicides, or combinations thereof. The choice of conductive material is generally influenced in part by the type of interconnect formed by a conductor. Conductors used for relatively short connections, such as connections between neighboring transistors, are often termed "local interconnects". Local interconnects may be formed from materials such as doped polysilicon or metal suicides. Conductors extending for longer distances in and across an integrated circuit are often called "global interconnects". Global interconnects are generally in layers above those containing the local interconnect, and the length of global interconnect conductors makes it important that they be formed from low-resistivity materials such as aluminum or, more recently, copper.

When a layer of a metal such as aluminum is patterned to form conductors, a layer of photoresist is typically formed above the metal. The photoresist is subsequently exposed through a mask and developed using techniques well-known in the art. Exposure of photoresist deposited over a metal is complicated, however, by the high reflectivity of the metal layer. The exposing light may be reflected back up through the photoresist by the metal layer, creating standing waves within the photoresist during exposure. This can produce a vertical undulation of the sidewall of developed resist features, which can in turn result in an inaccurate transfer of the mask pattern to the metal during the etch process. To address this problem, an anti-reflective coating (ARC) is typically deposited on the metal layer prior to the photolithography/etch sequence. An ARC typically works by absorbing most of the radiation that penetrates the resist during exposure, thereby preventing reflection of radiation back up into the resist. Titanium nitride (TiN) is a commonly-used ARC material.

The suitability of a particular ARC material may depend on the particular photoresist being used. The photoresist used depends on the exposure wavelength, which in turn depends on the dimensions of the mask features. For features having dimensions of less than 1.0 micron or, more particularly, less than 0.18 micron, a deep ultraviolet (DUV) photoresist is typically needed. The chemistry of a DUV photoresist may be significantly different than that of the near- and mid-UV photoresists used for patterning larger features. One DUV photoresist which has been found to be desirable for patterning ultra small features is a product known as UV5 available from Shipley Company. This photoresist, however, has been found to react with TiN ARC layers such that a portion of the photoresist adjacent to the TiN layer becomes bonded to the TiN and is not removed by the developer. This results in an extra "foot" of photoresist presented along the bottom of the developed and patterned photoresist feature, as shown in the partial cross-sectional view of Fig. 1.

Semiconductor substrate 10 of Fig. 1 is covered with interconnect metal layer 12 and TiN ARC layer 14. A layer of UV5 photoresist is then spun on, exposed, and developed to form photoresist feature 16. "Footing" of the photoresist at the interface with the TiN results in photoresist extensions 18 (separated from feature 16 by dashed lines). The footing results in an actual feature width d_a which is larger than intended feature width This increased feature width is transferred to the metal layer during the subsequent etching step, so that the intended interconnect width is not realized.

It is therefore necessary to develop an ARC which does not involve contact between TiN and UV5 resist, so that the footing problem described above is avoided. An attractive approach is to use a dual-layer ARC containing a thin oxide layer over a layer of TiN. In this way, the radiation-absorbing properties of TiN are retained, yet the UV5 photoresist is not in contact with the TiN. An ARC deposited over a metal for patterning is typically retained after the metal is patterned. The metal/ARC interconnect pattern is covered with a dielectric layer that may function either as a final passivation layer or as an interlevel dielectric for an additional interconnect layer. When interconnect widths and spacings between interconnect conductors are made small, care must be taken to avoid excessive thickness of the metal ARC interconnect conductors. If the aspect ratio (ratio of height to width) of the channels formed between the conductors by the etch process is too large, the subsequently-deposited dielectric may not fill the channels completely, leaving voids. Voids in a dielectric film can cause reliability problems by, for example, trapping gases which may subsequently cause unwanted reactions. Metal layer thicknesses may range from about 0.6 micron to about 1 micron, while TiN ARC layers are typically between about 80 nm and 120 nm thick. To limit the thickness of a metal/TiN/oxide interconnect, the oxide layer is preferably limited to a thickness of about 30 nm or less.

One possible candidate for the thin oxide layer described above is an oxide layer grown using decomposition of tetraethyl orthosilicate (TEOS). TEOS-deposited oxides are known to be very conformal, making TEOS oxides popular for applications such as filling isolation trenches and forming interlevel dielectrics over transistor topographies. There are problems associated with TEOS for thin oxide formation, however. TEOS oxides are difficult to grow thin (less than 100 nm), because thickness control is more difficult to achieve than for other oxide-forming reactions. Factors which make thickness control difficult include a dependence of the deposition rate on TEOS partial pressure, chamber clean frequency, and an exponential dependence of the deposition rate on temperature at higher temperatures. TEOS deposition processes may also result in significant deposition on chamber fixtures and walls. Deposition chambers therefore may have to be cleaned often, resulting in increased downtime and lower throughput. Furthermore, changes in thermal and reactive properties of the chamber walls and fixtures in the period during which they become recoated after a cleaning can make deposition conditions difficult to stabilize after each cleaning. Overall, the TEOS-based oxide ARC may result in lower throughput, lower defects, and higher cost as compared to oxides formed using other deposition processes.

It would therefore be desirable to develop a method for forming a lower-cost, higher-throughput thin oxide as part of an ARC for patterning interconnects having small feature sizes and high aspect ratios. The desired oxide should not cause footing of UV5 DUV photoresist, or other photoresists which may react with TiN ARCs. Accurate control of the oxide deposition process (i.e., rate and thickness) would also be of benefit.

DISCLOSURE OF INVENTION

The problems outlined above are in large part addressed by forming a silane-based thin oxide. When formed in the manner recited herein, this oxide may be used in an ARC process for patterning of metal interconnects having small width and large aspect ratio, and does not cause footing of UV5 photoresist. The method may also be useful for patterning of other small metal features, as may be found in, for example, micro- electro-mechanical systems (MEMS).

An insulating layer is deposited over a substrate upon and within which transistors are formed. An interconnect metal is deposited upon the insulating layer, and an ARC, preferably TiN, is deposited upon the interconnect metal. A thin (about 50 nm or less) oxide layer is then formed using a silane-based CVD process. The oxide is preferably deposited using plasma-enhanced CVD (PECVD), which allows deposition at temperatures between about 200 °C and about 500 °C. Low-temperature deposition of the oxide layer allows the underlying metal layer to be formed from low-resistance, low-melting-point metals such as aluminum. Silane-based CVD processes for oxide are well-characterized and controllable, so that thin layers may be grown without undue difficulty. Silane-based CVD of oxide for the ARC recited herein is also believed to be lower- cost and higher-throughput than forming a TEOS oxide. It should be noted that the plasma enhanced deposition recited above and elsewhere herein is distinct from a plasma treatment using an N₂0 plasma which is recited below. The phrase "plasma treatment" as used herein refers to a post-deposition exposure to an N₂0 plasma which is performed in an embodiment of the method recited herein.

In one embodiment of the method recited herein, the silane-based oxide is grown using a non-nitrogen carrier gas. Because silane is highly pyrophoric and burns upon exposure to air, it is typically supplied in a dilute form in an inert carrier gas such as nitrogen or argon. Nitrogen is a very popular carrier gas because of its low cost compared to other inert gases. Unfortunately, oxides grown using silane in a nitrogen carrier gas have been found to result in footing of UV5 photoresist, similar to the footing that occurs when TiN is in contact with the photoresist. Nitrogen-hydrogen (N-H) bonds have been detected in such silane-based oxides, and nitrogen from these N-H bonds is believed to react with the UV5 photoresist and cause footing. Use of a non-nitrogen carrier gas, such as argon or helium, for the silane source is believed to substantially eliminate nitrogen in deposited oxide layers, and thereby eliminate the source of the footing. In an alternate embodiment of the method recited herein, the silane-based oxide is deposited using a nitrogen carrier gas for the silane source. Subsequent to this oxide deposition, a short (less than about 2 minutes) N₂0 plasma treatment is performed. A plasma pressure ranging from about 240 Pa to 425 Pa is used. This N₂0 plasma treatment is believed to substantially eliminate the reaction of any nitrogen on the oxide surface with overlying UV5 photoresist, possibly by oxygen passivation of the nitrogen. The plasma treatment may also break up any N-H bonds on the surface of the silane-based oxide layer. Use of the N₂0 plasma treatment allows use of a less expensive nitrogen carrier gas for the silane used in the oxide deposition.

After formation of a thin silane-based oxide layer according to either of the above embodiments, the oxide layer may be coated with a layer of DUV photoresist, preferably UV5 photoresist. The photoresist may then be exposed and developed to produce an interconnect pattern in the photoresist. The photoresist features formed in this manner are believed to not exhibit the footing described above. It is postulated that the footing is caused by reaction of the UV5 photoresist with nitrogen at the surface of an underlying film. The method recited herein for forming a thin silane-based oxide is believed to substantially eliminate reaction of nitrogen from the oxide with the photoresist. In the embodiment in which the oxide is grown using a non-nitrogen silane carrier gas, the nitrogen itself is believed to be eliminated. In the embodiment in which the grown oxide is treated with an N₂0 plasma, the reactivity of any nitrogen on the oxide surface is believed to be reduced. The interconnect pattern in the photoresist may subsequently be transferred to the metal by etching the oxide, ARC, and metal layers using a dry etch process. In this manner, interconnects having ultra small feature sizes and high aspect ratios may be formed. The deposition and, in one embodiment, plasma treatment of the silane-based oxide recited herein are typically performed in a CVD chamber associated with a "cluster tool" used in the semiconductor industry. Cluster tools include chambers grouped together so that multiple deposition, etching, or other processes can be performed sequentially without exposing substrates to room air between the processes. The CVD chambers often have multiple (for example, six) substrate mounting positions. A substrate is moved sequentially into different positions during a deposition such that a portion of the deposition takes place with the substrate in each of the mounting positions in the chamber. For example, a substrate may be loaded into the first substrate position of the chamber, after which one-sixth of the deposition is performed. The substrate is then moved to the second substrate position, while a second substrate is brought into the chamber and loaded into the first position. Another one-sixth of a deposition is performed, and the process continues with movement of the two substrates into adjacent positions and entry of a third substrate into the chamber. This type of system is designed to improve the uniformity of a deposited layer across the substrate by averaging out random process variations which are chamber-location dependent, in addition to increasing throughput by allowing overlapping deposition sequences for multiple substrates.

For the embodiment of the method recited herein in which a plasma treatment is performed, this sequence is preferably modified so that the oxide layer deposition is divided between all but one of the substrate mounting positions, and the plasma treatment is performed with the substrate on the last mounting position. For example, using the chamber having six mounting positions described above, the oxide layer may be deposited using substrate mounting positions 1 through 5, while the plasma treatment may be performed with the substrate on mounting position 6. In this way, the plasma treatment may be performed without exposing the substrate to room air following the oxide deposition. This is desirable because room air exposure may cause particulate contamination and/or unwanted oxidation.

A CVD deposition system such as that described above typically further includes a "showerhead" positioned above each substrate mounting position. The showerhead typically includes an array of holes through which reactant gases are supplied to the region above the substrate during a deposition. The showerhead construction also includes a metal surface to which a radio frequency (RF) voltage is applied to generate a glow discharge for plasma-enhanced processes. In the case of a plasma-enhanced deposition, the - system configuration is typically such that a high-frequency (HF) RF voltage, typically having a frequency of about 13.56 MHz, is applied to the showerhead. This RF connection configuration is used for both the PECVD oxide deposition and N₂0 plasma treatment recited herein, if performed in this type of deposition system. If a low-frequency (LF) RF voltage, typically having a frequency of less than 1 MHz, is used, it is typically applied to a metal substrate mounting surface of the chamber. The deposition and plasma treatment processes recited herein preferably use only HF power. When this type of CVD system is used for the plasma treatment recited herein, the HF power for the plasma treatment may range from about 500 watts to about 1100 watts, and the N₂0 flow rate used for the plasma treatment may be between about 500 standard cubic centimeters per minute (seem) and about 2000 seem.

BRIEF DESCRIPTION OF DRAWINGS

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

Fig. 1 is a partial cross-sectional view of a semiconductor topography including a semiconductor substrate upon which metal and TiN layers are formed and a photoresist feature is patterned;

Fig. 2 is a partial cross-sectional view of a semiconductor topography upon which a transistor is formed, contacts are made to the transistor through an interlevel dielectric, and a metal layer and an ARC layer are deposited;

Fig. 3 is a partial cross-sectional view of the semiconductor topography wherein a thin oxide layer is formed over the ARC layer, subsequent to the ARC layer deposition of Fig. 2;

Fig. 4 is a partial cross-sectional view of the semiconductor topography wherein a plasma treatment is performed, subsequent to the oxide deposition of Fig. 3;

Fig. 5 is a partial cross-sectional view of the semiconductor topography wherein a DUV photoresist layer is deposited over the oxide layer, subsequent to the oxide deposition of Fig. 3 or the plasma treatment of Fig. 4;

Fig. 6 is a partial cross-sectional view of the semiconductor topography wherein photoresist features are patterned, subsequent to the photoresist deposition of Fig. 5;

Fig. 7 is a top plan view showing the substrate mounting position layout of an exemplary deposition system;

Fig. 8 is a plan view showing the gas delivery and RF connection layout at a substrate mounting position of an exemplary deposition system; and Fig. 9 is a flow diagram of the process sequence for an embodiment of the method recited herein.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

MODES FOR CARRYING OUT THE INVENTION

Turning to the drawings, Fig. 2 illustrates a partial cross-section of a transistor, including a gate conductor 24 and a gate dielectric 22 arranged above semiconductor substrate 20. Dielectric spacers 26 may be formed adjacent to gate conductor 24. Source and drain regions 28 may be formed using a lightly-doped impurity distribution self-aligned to gate conductor 24 and a heavily-doped impurity distribution self-aligned to lateral surfaces of spacers 26. Following the formation of source and drain regions 28, a salicide process may be performed in a manner well-known in the art to form suicides 30 on upper surfaces of source and drain regions 28 and gate conductor 24. Formation of spacers 26 may be advantageous for reasons including the ability to form lightly-doped regions under the spacers which may lower the maximum electric field developed at the drain end of the channel. This lowered electric field may reduce the severity of hot-carrier effects such as avalanche breakdown at the drain/substrate junction and injection of carriers into the gate dielectric. Spacers 26 may also be advantageous by providing isolation between the source/drain and gate regions so that a salicide process may be performed.

An interlevel dielectric 32 may subsequently be deposited over substrate 20, and may then be planarized. The planarization may be performed using, for example, chemical-mechanical polishing or an etchback technique. Openings are formed in the dielectric for contact to the source and drain regions 28 and gate conductor 24. The openings are filled with conducting material 34. For example, a tungsten plug process in which an adhesion layer is deposited to line the opening and tungsten is then deposited to fill the opening may be used. To form interconnects by which the source, drain, and gate are connected to other regions of the circuit, a metal layer 36 is deposited. An ARC layer 38, such as TiN, is deposited over metal layer 36. As discussed above, an ARC is typically needed when patterning metals in order to avoid formation of standing waves in the overlying photoresist.

Semiconductor substrate 20 is preferably monocrystalline silicon, and is doped either n-type or p-type. More specifically, substrate 20 may be an epitaxial silicon layer grown on a monocrystalline silicon substrate, or an n-type or p-type well region formed in a monocrystalline silicon substrate. Although not shown, dielectric isolation regions may be formed in substrate 20 which separate adjacent transistors. One method by which such isolation regions may be formed is the formation of trenches which are subsequently filled with a deposited dielectric, while another method which may be used is local oxidation of the substrate, using silicon nitride to mask the active regions in which transistors are to be formed. Gate dielectric 22 is preferably grown by heating substrate 20 to a temperature of greater than about 700 °C in an oxidizing ambient to grow silicon dioxide. Other gate dielectrics may be used, however, including silicon nitride, nitrided silicon dioxide, silicon oxynitride, and deposited silicon dioxide. Gate conductor 24 is preferably a polysilicon gate conductor patterned from a polysilicon layer which is deposited using chemical vapor deposition (CVD) of silicon from, for example, a silane source. Such a CVD process may alternatively result in an amorphous silicon layer, particularly if low substrate temperatures are used. An amorphous silicon layer may also be patterned to form gate conductor 24, and other materials which can withstand subsequent processing (such as that needed to form source and drain regions) may also be used.

The impurity distributions forming source and drain regions 28 are preferably introduced using ion implantation, and are of opposite type to that of substrate 20. For an n-channel transistor, for example, substrate 20 is p-type and source and drain regions 28 are n-type. Typical n-type dopants include arsenic and phosphorus, while boron is a typical p-type dopant. If source and drain regions 28 are introduced by ion implantation, a subsequent anneal is performed in order to activate the impurities and repair damage to substrate 20. Spacers 26 are typically silicon dioxide, formed by CVD of a conformal silicon dioxide layer and anisotropic etching of the layer to form spacers. Spacers 26 may also be formed from other dielectrics such as silicon nitride or silicon oxynitride. Silicides 30 are typically titanium silicide or cobalt silicide, but may also be formed using other metals, including, for example, tantalum, nickel, tungsten, molybdenum, and platinum. Interlevel dielectric 32 is typically an oxide layer formed using CVD, but could be formed from a different dielectric. Dielectric 32 may be formed using silane-based CVD or alternatively by decomposition of TEOS. Deposition is preferably performed using PECVD at a temperature between about 200 °C and 500 °C, but other methods, such as low pressure CVD (LPCVD) and atmospheric-pressure CVD (APCVD), may also be used. Dielectric 32 may also include an etch-stop layer having different composition than the remainder of the dielectric. Conductive material 34 may consist of tungsten plugs, as noted above, or may be a different metal or another conductor such as doped polysilicon. Conductive material 34 may also include adhesion layers and/or diffusion barrier layers. Metal layer 36 is typically aluminum or an aluminum alloy, but may also be formed from copper or other materials used for interconnects. As for conductive material 34, metal layer 36 may also include adhesion layers and/or diffusion barrier layers. In the case shown in Fig. 2 for which metal layer 36 is in a first interconnect level above substrate 20, the thickness of layer 36 typically ranges from about 0.6 micron to about 1.8 micron. The method recited herein may also be performed for higher-level interconnects. For upper interconnect levels, metal layer thicknesses are typically between about 0.8 micron to 2.0 microns. ARC layer 38 is preferably TiN, which is a well-characterized material in semiconductor processing. TiN is commonly used for adhesion and diffusion barrier layers as well as for ARC layers. When formed from TiN, ARC layer 38 may have a thickness of between about 60 nm to about 140 nm.

The structure underlying metal 36 may be different from that of Fig. 2 in several ways without changing the utility of the method recited herein. The transistor shown in Fig. 2 may be formed in a different manner. For example, spacers 26 and silicides 30 may be omitted. The method recited herein may also be applied to a bipolar circuit, so that a bipolar transistor underlies metal 36 rather than the metal-oxide- semiconductor (MOS) field effect transistor shown in Fig. 2. Alternatively, the method may be applied to patterning of a metal layer for a different purpose than forming an interconnect, in which case transistors may not be formed on substrate 20. An example of such a case may be the formation of metal structures on semiconductor substrates for fabrication of MEMS devices. Even for use in MOS circuits, the structure underlying metal 36 may be different in that additional layers of interconnect may be included therein. Either local interconnect or global interconnect layers may be formed below metal layer 36.

Oxide 40 is subsequently deposited over ARC layer 38, as shown in Fig. 3. Oxide 40 is deposited using a silane-based process. Silane is reacted with an oxygen-containing gas in a CVD reactor. The oxygen- containing gas is preferably 0₂, but other gases, such as N₂0, may also be used. The oxide is preferably deposited using PECVD at a substrate temperature of about 400 °C. PECVD deposition may also be performed at temperatures ranging from about 200 °C to about 500 °C. Such low deposition temperatures are necessary when metal 36 is a low-melting point metal such as aluminum or copper. If a higher-temperature metal, such as tungsten, is used for metal 36 and any other underlying metal layers, higher temperature deposition methods such as LPCVD may be used. Oxide 40 is preferably no more than about 30 nm thick.

In one embodiment of the method recited herein, oxide 40 is deposited using a non-nitrogen silane carrier gas, such as argon or helium. This is believed to substantially eliminate nitrogen in deposited oxide layers, which is believed to be the source of the UV5 photoresist footing observed when a nitrogen carrier gas is used. Following deposition of this oxide layer, a layer of DUV photoresist can be applied and patterned, as shown in Fig. 5 and discussed further below.

In an alternate embodiment of the method, in which oxide 40 is deposited using a nitrogen carrier gas, plasma treatment 2 is subsequently applied to oxide layer 40, as shown in Fig. 4. Plasma treatment 2 is performed by exposing substrate 20 to an N₂0 plasma for a duration of about 2 minutes or less. The substrate temperature during plasma treatment 2 is preferably about 400 °C, but may range from about 380 °C to about 430 °C. Oxide 40 may be deposited and plasma treatment 2 may be performed in a deposition chamber having multiple substrate mounting positions, such as a Novellus Concept II deposition chamber. In this case, the plasma pressure used for plasma treatment 2 is between about 240 Pa and about 425 Pa, and the N₂0 flow rate is between 500 standard cubic centimeters per minute (seem) and 2000 seem. This embodiment further employs HF RF power of between about 500 watts and about 1100 watts. Although LF power is not needed for plasma process 2 in this embodiment of the method recited herein, it is believed that LF power may be included without changing the utility of the method. Furthermore, although plasma treatment 2 is not believed to be necessary in embodiments for which a non-nitrogen carrier gas is used for deposition of oxide 40, it is believed that the plasma treatment may be applied in this case without harming the performance of oxide 40. Turning now to Fig. 5, DUV photoresist layer 42 is subsequently deposited over oxide 40. DUV photoresists respond to exposure radiation having wavelengths smaller than about 300 nm. Photoresist layer 42 is preferably formed from Shipley UV5 photoresist. Photoresist layer 42 is subsequently exposed through a mask and developed, such that photoresist features 44, shown in Fig. 6, are formed. Photoresist features 44 are believed to be free of footing, such as that exhibited by photoresist feature 16 in Fig. 1. The lack of footing is believed to result from substantial elimination of any reaction of the photoresist with nitrogen in or on oxide 40. In the embodiment described above in which oxide 40 is deposited using a non-nitrogen carrier gas, a lack of nitrogen in oxide 40 is believed to prevent any reaction of nitrogen with the photoresist. In the embodiment described above for which deposition of oxide 40 using a nitrogen carrier gas is followed by plasma treatment 2, any nitrogen present on the surface of the oxide is believed to be prevented from reacting with the photoresist. The pattern dimensions of the exposure mask are therefore reproduced by features 44, and can be subsequently transferred to metal 36 through an etch process.

Turning now to Fig. 7, a cross-sectional top view of an exemplary deposition chamber 46 is shown. Deposition chambers for the semiconductor industry such as that illustrated in Fig. 7 are manufactured by, for example, Novellus. Substrate mounting surface 48 includes multiple substrate, or wafer, mounting positions (in this case, six). The dashed-line arrows show the path taken by a substrate entering the chamber for a deposition. A first portion of a deposited layer is formed with the substrate on first mounting position 50. The substrate is^" then moved to second mounting position 52 for deposition of a second portion of the layer. The deposition process typically continues on each mounting position until the sixth portion is deposited with the substrate on sixth mounting position 56, and the substrate is then moved out of the deposition chamber. In embodiments of the method recited herein in which a post-deposition plasma treatment is used, this sequence is altered somewhat. Deposition of oxide 40, as shown in Fig. 3, is divided between all but one of the substrate mounting positions in the chamber. For the chamber of Fig. 7, therefore, the oxide deposition would begin at first position 50 and end at fifth position 54. The remaining substrate mounting position (the sixth position, in the chamber of Fig. 7) is then used for N₂0 plasma treatment 2, shown in Fig. 4. After completion of plasma treatment 2, the substrate is removed from chamber 46 for photoresist application.

Although the sequence in moving through chamber 46 has been described for one substrate, it should be noted that during typical operation of the deposition system illustrated in Fig. 7, a new substrate is moved onto first mounting position 50 and a completed substrate is removed from the chamber after each portion of a deposition. In other words, six substrates may be undergoing deposition simultaneously, each substrate within one portion of the chamber receiving a portion of the total deposition amount. Or in the case of embodiments including a plasma treatment, five substrates may be undergoing deposition simultaneously, while one substrate undergoes plasma treatment. Parts of a typical chamber which are not shown in Fig. 7 include a substrate- handling mechanism, substrate heaters, plumbing for delivery of reactant gases, electrodes for plasma generation, and one or more vacuum pumps. Although six substrate mounting positions are shown in the chamber of Fig. 7, a different number of positions could be used.

Turning now to Fig. 8, a cross-sectional view is shown which illustrates the gas delivery and RF connection layout at a substrate mounting position of a deposition chamber such as chamber 46 in Fig. 7. Substrate 58 is mounted in a substrate mounting position of mounting surface 48, a portion of which is shown in Fig. 8. Showerhead 60 is positioned above substrate 58, such that reactant gases 62 may be delivered to the vicinity of substrate 58. Gas lines 64 deliver reactant gases to showerhead 60 for dispersal, typically through an array of holes. An HF RF voltage is typically connected to a metal portion of showerhead 60, using an HF generator 66 which is external to the chamber wall. The HF voltage is typically connected through an electrical matching network. In the event that an LF voltage is used, it is typically connected to metal substrate mounting surface 48. In embodiments of the method recited herein which use a chamber such as the Novellus Concept 2, LF power is not necessary for the silane-based oxide deposition or the N₂0 plasma treatment.

A procedure for performing the method recited herein using equipment such as that shown in Figs. 7 and 8 is given by the flow diagram of Fig. 9. The procedure of the flow diagram is described here, using reference labels for parts of the equipment shown in Figs. 7 and 8. To perform the process recited herein for thin oxide ARC formation on substrate 58, the substrate is loaded onto first substrate mounting position 50 of deposition chamber 46. The number of mounting positions used for the oxide deposition depends on whether or not a nitrogen carrier gas is used for the silane. If a nitrogen carrier gas is used, a plasma treatment is performed in the chamber after oxide deposition. In this case the oxide is therefore deposited in five portions, by moving the substrate through the first five substrate mounting positions of chamber 46 as illustrated in Fig. 7. This oxide corresponds to oxide 40 shown in Fig. 3. As described in the flow diagram of Fig. 9, the substrate is heated to deposition temperature and allowed to stabilize in temperature before reactant gases 62 are introduced. Reactant gases 62 include silane and an oxygen-containing chemical, preferably 0₂. For PECVD deposition of the oxide layer, an HF voltage is typically applied to the corresponding showerhead, such as showerhead 60, for each mounting position. This process is repeated for each portion of the deposition.

After deposition of the final portion of the oxide in fifth mounting position 54, substrate 58 is moved to sixth mounting position 56 for an N₂0 plasma treatment. This plasma treatment corresponds to plasma treatment 2 illustrated by Fig. 4. As shown in the flow diagram of Fig. 9, the substrate is brought to a plasma treatment temperature. In a chamber such as the Novellus Concept 2, the plasma treatment temperature and the oxide deposition temperature are the same. This is because there is one heater in the chamber which brings all of the substrates to the same temperature. Because other substrates are typically undergoing deposition while substrate 58 undergoes plasma treatment, the deposition and treatment are performed at the same temperature. In the event that other equipment which may have independent substrate temperature control for the deposition and plasma treatment is used, these processes could be performed at different substrate temperatures. An HF voltage is applied to the showerhead corresponding to sixth substrate mounting position 56, and N,0 is supplied through one or more of gas lines 64. In this manner, a glow discharge is created, so that reactant gases 62 include ions and radicals formed from the N₂0 as well as N₂0 molecules. After exposure to the N₂0 plasma for a time in a range from about 10 seconds to about 2 minutes, substrate 58 is removed from deposition chamber 46 for photoresist application. In embodiments for which a non-nitrogen carrier gas is used, the plasma treatment described above is believed not to be necessary. In this case, deposition of oxide 40 is divided between all of the mounting positions in the deposition chamber, as shown in the flow diagram of Fig. 9. The deposition proceeds as described above, except that the last portion of oxide 40 is deposited on sixth mounting position 56 of chamber 46. Substrate 58 is then removed from chamber 46 for photoresist application. Photoresist application and subsequent processing may be performed in additional chambers connected to chamber 46 as part of a cluster tool arrangement. Alternatively, the substrate may have to be moved to a separate chamber for further processing. As pointed out in the discussion of Fig. 7 above, it should be noted that a new substrate is typically introduced into each chamber as soon as the first mounting position becomes unoccupied, so that multiple substrates are moving through the process at any given time. As in the case of Fig. 7, some aspects of an actual chamber, including substrate heaters and vacuum pumps, are not shown in Fig. 8.

3. Industrial Applicability

This invention is suitable for a number of industrial applications including, but not limited to, the fields of semiconductor circuit manufacture and micro-electro-mechanical systems manufacture. It will be appreciated to those skilled in the art having the benefit of this disclosure that this invention is believed to provide a method for forming a thin oxide to be used as part of an ARC for patterning of metal interconnects having small feature sizes and large aspect ratios. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. For example, equipment other than the deposition chamber described herein could be used in carrying out the process recited herein. Other types of deposition chamber which might be used include horizontal tube LPCVD reactors. It is intended that the following claims be interpreted to embrace all such modifications and changes and, accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

WHAT IS CLAIMED IS:

1. A method for patterning features on a semiconductor substrate (20), comprising:

forming an oxide (40) above a semiconductor topography;

exposing said oxide (40) to a plasma (2) formed using nitrous oxide; and

forming a photoresist layer (42) upon said oxide layer (40).

2. The method as recited in claim 1, wherein said forming the oxide (40) further comprises:

forming a transistor upon and within said semiconductor topography;

forming an insulating layer (32) over said transistor;

forming a metal layer (36) upon said insulating layer (32); and

forming an anti-reflective coating (38) upon said metal layer (36).

3. The method as recited in claim 2, wherein said anti-reflective coating (38) comprises titanium nitride.

4. The method as recited in claim 1, wherein said forming the oxide (40) comprises plasma-enhanced chemical vapor depositing by reacting silane with an oxygen-containing chemical at a deposition temperature in a range from about 200 °C to about 500 °C.

5. The method as recited in claim 1, wherein said exposing comprises forming a plasma (2) having a pressure in a range from about 240 Pa to about 425 Pa, using a high-frequency power in a range from about 500 watts to about 1100 watts with a frequency of about 13.56 MHz, and a nitrous oxide flow rate in a range from about 500 standard cubic centimeters per minute (seem) to about 2000 seem, and wherein said exposing is performed for a duration of less than about 2 minutes at a substrate temperature in a range from about 380 °C to about 430 °C.

6. The method as recited in claim 1, wherein said forming the photoresist layer (42) comprises depositing a photoresist designed for exposure by radiation having a wavelength less than or equal to about 300 nm.

7. A method for patterning features on a semiconductor substrate (20), comprising: loading said semiconductor substrate into a first substrate mounting position (50) of a deposition chamber (46) having multiple substrate mounting positions;

heating said semiconductor substrate (20) to a deposition temperature in a range from about 200 °C to about 500 °C until said deposition temperature is maintained;

introducing reactant gases (62) into said deposition chamber (46) such that a portion of an oxide (40) is deposited;

sequentially moving said semiconductor substrate (20) to all except one of remaining mounting positions in said deposition chamber (46) for deposition of another portion of said oxide (40) at each substrate mounting position, such that complete oxide is deposited;

subsequently moving said semiconductor substrate (20) to said one remaining mounting position (56) in said deposition chamber (46);

heating said semiconductor substrate (20) to a plasma treatment temperature in a range from about 380 °C to about 430 ^βC;

exposing said semiconductor substrate (20) for a duration of less than about 2 minutes to a plasma (2) formed using nitrous oxide;

removing said semiconductor substrate (20) from said deposition chamber (46); and

forming a photoresist layer (42) upon said oxide (40).

8. The method as recited in claim 7, wherein said introducing reactant gases (62) comprises introducing silane and an oxygen-containing chemical and further comprises applying radio frequency power to a conducting surface (60) of said deposition chamber (46) such that a glow discharge is formed.

9. The method as recited in claim 7, wherein said exposing comprises forming a plasma (2) having a pressure in a range from about 240 Pa to about 425 Pa, using a high-frequency power in a range from about 500 watts to about 1100 watts, and a nitrous oxide flow rate in a range from about 500 seem to about 2000 seem.

10. A method for patterning features on a semiconductor substrate (20), characterized in that:

forming a titanium nitride anti-reflective coating (38) upon a metal layer (36) deposited upon said semiconductor substrate (20); depositing an oxide layer (40) over said anti-reflective coating (38), wherein said oxide (40) is deposited by chemical vapor deposition using silane and oxygen, and wherein gases introduced to a deposition chamber (46) for deposition of said oxide (40) are substantially absent nitrogen; and

forming a photoresist layer (42) over said oxide layer (40), wherein said photoresist layer (42) is designed for exposure with radiation having a wavelength of less than about 300 nm.