WO2000030308A3 - Equalizer for multi-pair gigabit ethernet - Google Patents

Equalizer for multi-pair gigabit ethernet Download PDF

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Publication number
WO2000030308A3
WO2000030308A3 PCT/US1999/027055 US9927055W WO0030308A3 WO 2000030308 A3 WO2000030308 A3 WO 2000030308A3 US 9927055 W US9927055 W US 9927055W WO 0030308 A3 WO0030308 A3 WO 0030308A3
Authority
WO
WIPO (PCT)
Prior art keywords
feedforward equalizer
equalizer
receiver
gain
filtered signal
Prior art date
Application number
PCT/US1999/027055
Other languages
French (fr)
Other versions
WO2000030308A2 (en
Inventor
Oscar E Agazzi
David Kruse
Arthur Abnous
Mehdi Hatamian
Original Assignee
Broadcom Corp
Oscar E Agazzi
David Kruse
Arthur Abnous
Mehdi Hatamian
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US09/370,354 external-priority patent/US6249544B1/en
Priority claimed from US09/370,370 external-priority patent/US6253345B1/en
Priority claimed from US09/370,353 external-priority patent/US6226332B1/en
Priority claimed from US09/370,491 external-priority patent/US6252904B1/en
Application filed by Broadcom Corp, Oscar E Agazzi, David Kruse, Arthur Abnous, Mehdi Hatamian filed Critical Broadcom Corp
Priority to AU17259/00A priority Critical patent/AU1725900A/en
Priority to AT99960364T priority patent/ATE476814T1/en
Priority to DE69942652T priority patent/DE69942652D1/en
Priority to EP99960364A priority patent/EP1145511B1/en
Publication of WO2000030308A2 publication Critical patent/WO2000030308A2/en
Publication of WO2000030308A3 publication Critical patent/WO2000030308A3/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
    • H04L7/0062—Detection of the synchronisation error by features other than the received signal transition detection of error based on data decision error, e.g. Mueller type detection
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3004—Current or voltage test
    • G01R31/3008—Quiescent current [IDDQ] test or leakage current test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G01R31/3016—Delay or race condition test, e.g. race hazard test
    • G—PHYSICS
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    • G01R31/317—Testing of digital circuits
    • G01R31/31712—Input or output aspects
    • G01R31/31715—Testing of input or output circuits; test of circuitry between the I/C pins and the functional core, e.g. testing of input or output driver, receiver, buffer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
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    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318502—Test of Combinational circuits
    • G—PHYSICS
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    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
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    • G01R31/317—Testing of digital circuits
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    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
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    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318594—Timing aspects
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    • H04B3/23—Reducing echo effects or singing; Opening or closing transmitting path; Conditioning for transmission in one direction or the other using a replica of transmitted signal in the time domain, e.g. echo cancellers
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    • H04L25/067—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing soft decisions, i.e. decisions together with an estimate of reliability
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Abstract

A feedforward equalizer for equalizing a sequence of signal samples received by a receiver from a remote transmitter. The feedforward equalizer has a gain and is included in the receiver which includes a timing recovery module for setting a sampling phase and a decoder. The feedforward equalizer comprises a non-adaptive filter and a gain stage. The non-adaptive filter receives the signal samples and produces a filtered signal. The gain stage adjusts the gain of the feedforward equalizer by adjusting the amplitude of the filtered signal. The amplitude of the filtered signal is adjusted so that it fits in the operational range of the decoder. The feedforward equalizer does not affect the sampling phase setting of the timing recovery module of the receiver.
PCT/US1999/027055 1998-11-13 1999-11-12 Equalizer for multi-pair gigabit ethernet WO2000030308A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU17259/00A AU1725900A (en) 1998-11-13 1999-11-12 Demodulator for a multi-pair gigabit transceiver
AT99960364T ATE476814T1 (en) 1998-11-13 1999-11-12 EQUALIZER FOR MULTIPAIR GIGABIT ETHERNET
DE69942652T DE69942652D1 (en) 1998-11-13 1999-11-12 DECARTER FOR MULTIPLE GIGABIT ETHERNET
EP99960364A EP1145511B1 (en) 1998-11-13 1999-11-12 Equalizer for multi-pair gigabit ethernet

Applications Claiming Priority (14)

Application Number Priority Date Filing Date Title
US10831998P 1998-11-13 1998-11-13
US60/108,319 1998-11-13
US11694699P 1999-01-20 1999-01-20
US60/116,946 1999-01-20
US13061699P 1999-04-22 1999-04-22
US60/130,616 1999-04-22
US09/370,354 US6249544B1 (en) 1998-11-13 1999-08-09 System and method for high-speed decoding and ISI compensation in a multi-pair transceiver system
US09/370,535 1999-08-09
US09/370,370 US6253345B1 (en) 1998-11-13 1999-08-09 System and method for trellis decoding in a multi-pair transceiver system
US09/370,370 1999-08-09
US09/370,353 US6226332B1 (en) 1998-11-13 1999-08-09 Multi-pair transceiver decoder system with low computation slicer
US09/370,491 US6252904B1 (en) 1998-11-13 1999-08-09 High-speed decoder for a multi-pair gigabit transceiver
US09/370,491 1999-08-09
US09/370,354 1999-08-09

Publications (2)

Publication Number Publication Date
WO2000030308A2 WO2000030308A2 (en) 2000-05-25
WO2000030308A3 true WO2000030308A3 (en) 2000-12-21

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PCT/US1999/027055 WO2000030308A2 (en) 1998-11-13 1999-11-12 Equalizer for multi-pair gigabit ethernet

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AU (1) AU1725900A (en)
WO (1) WO2000030308A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002030075A1 (en) * 2000-10-05 2002-04-11 Matsushita Electric Industrial Co., Ltd. Digital data transmitter, transmission line encoding method, and decoding method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4713829A (en) * 1985-06-19 1987-12-15 Codex Corporation Coded modulation system with a simplified decoder capable of reducing the effects of channel distortion
US5734680A (en) * 1995-08-09 1998-03-31 Hewlett-Packard Co. Analog implementation of a partial response maximum likelihood (PRML) read channel
US5734685A (en) * 1996-01-03 1998-03-31 Credence Systems Corporation Clock signal deskewing system

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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