WO2000019524A3 - Ic interconnect structures and methods for making same - Google Patents

Ic interconnect structures and methods for making same Download PDF

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Publication number
WO2000019524A3
WO2000019524A3 PCT/US1999/022567 US9922567W WO0019524A3 WO 2000019524 A3 WO2000019524 A3 WO 2000019524A3 US 9922567 W US9922567 W US 9922567W WO 0019524 A3 WO0019524 A3 WO 0019524A3
Authority
WO
WIPO (PCT)
Prior art keywords
etch
layer
stop
methods
sub
Prior art date
Application number
PCT/US1999/022567
Other languages
French (fr)
Other versions
WO2000019524A2 (en
WO2000019524A9 (en
Inventor
Bin Zhao
Maureen R Brongo
Original Assignee
Conexant Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conexant Systems Inc filed Critical Conexant Systems Inc
Publication of WO2000019524A2 publication Critical patent/WO2000019524A2/en
Publication of WO2000019524A3 publication Critical patent/WO2000019524A3/en
Publication of WO2000019524A9 publication Critical patent/WO2000019524A9/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

Methods and structures are disclosed for advanced interconnects in sub-micron and sub-half-micron integrated circuit devices fabricated using a single damascene process. A dielectric etch-stop layer (e.g., silicon nitride) is deposited subsequent to rather than prior to CMP processing of the previous metallization layer (e.g., the conductive plug). This scheme effectively eliminates the effect of CMP-induced erosion on the etch-stop layer and therefore allows an extremely thin etch stop to be used. Moreover, a high etch-selectivity can be obtained for the trench etch, and all etch-stop material is removed from beneath the interconnect metal, thereby reducing parasitic effects. A patterned dielectric layer is used as a metal cap in place of the standard blanket silicon nitride layer, thus preventing the formation of blisters and bubbles associated with trapped moisture and gasses, and reducing interconnect capacitance.
PCT/US1999/022567 1998-09-30 1999-09-30 Ic interconnect structures and methods for making same WO2000019524A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/163,967 US6245663B1 (en) 1998-09-30 1998-09-30 IC interconnect structures and methods for making same
US09/163,967 1998-09-30

Publications (3)

Publication Number Publication Date
WO2000019524A2 WO2000019524A2 (en) 2000-04-06
WO2000019524A3 true WO2000019524A3 (en) 2000-09-14
WO2000019524A9 WO2000019524A9 (en) 2001-12-13

Family

ID=22592406

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/022567 WO2000019524A2 (en) 1998-09-30 1999-09-30 Ic interconnect structures and methods for making same

Country Status (3)

Country Link
US (1) US6245663B1 (en)
TW (1) TW430966B (en)
WO (1) WO2000019524A2 (en)

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US6734110B1 (en) * 1999-10-14 2004-05-11 Taiwan Semiconductor Manufacturing Company Damascene method employing composite etch stop layer
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US6893969B2 (en) * 2001-02-12 2005-05-17 Lam Research Corporation Use of ammonia for etching organic low-k dielectrics
US6841483B2 (en) * 2001-02-12 2005-01-11 Lam Research Corporation Unique process chemistry for etching organic low-k materials
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JP3780189B2 (en) * 2001-09-25 2006-05-31 富士通株式会社 Semiconductor device manufacturing method and semiconductor device
US6472314B1 (en) * 2001-10-02 2002-10-29 Lsi Logic Corporation Diamond barrier layer
US7932603B2 (en) 2001-12-13 2011-04-26 Megica Corporation Chip structure and process for forming the same
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US7151273B2 (en) 2002-02-20 2006-12-19 Micron Technology, Inc. Silver-selenide/chalcogenide glass stack for resistance variable memory
JP2004119478A (en) * 2002-09-24 2004-04-15 Renesas Technology Corp Semiconductor memory device, nonvolatile memory device, and magnetic memory device
KR100504666B1 (en) * 2002-11-12 2005-08-03 한국전자통신연구원 Method of forming a photosensitive film pattern
US7214609B2 (en) * 2002-12-05 2007-05-08 Texas Instruments Incorporated Methods for forming single damascene via or trench cavities and for forming dual damascene via cavities
US7147767B2 (en) * 2002-12-16 2006-12-12 3M Innovative Properties Company Plating solutions for electrochemical or chemical deposition of copper interconnects and methods therefor
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Also Published As

Publication number Publication date
US6245663B1 (en) 2001-06-12
WO2000019524A2 (en) 2000-04-06
TW430966B (en) 2001-04-21
WO2000019524A9 (en) 2001-12-13

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