WO2000019490A3 - Dummy fill cell for reducing layer-to-layer interaction - Google Patents

Dummy fill cell for reducing layer-to-layer interaction Download PDF

Info

Publication number
WO2000019490A3
WO2000019490A3 PCT/US1999/016794 US9916794W WO0019490A3 WO 2000019490 A3 WO2000019490 A3 WO 2000019490A3 US 9916794 W US9916794 W US 9916794W WO 0019490 A3 WO0019490 A3 WO 0019490A3
Authority
WO
WIPO (PCT)
Prior art keywords
layer
dummy fill
cell
pattern
dummy
Prior art date
Application number
PCT/US1999/016794
Other languages
French (fr)
Other versions
WO2000019490A2 (en
Inventor
Robert Zwingman
Aniruddha Joshi
Original Assignee
Conexant Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Conexant Systems Inc filed Critical Conexant Systems Inc
Publication of WO2000019490A2 publication Critical patent/WO2000019490A2/en
Publication of WO2000019490A3 publication Critical patent/WO2000019490A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76819—Smoothing of the dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A dummy fill pattern for a multi-layer semiconductor device is based upon an intelligently designed dummy fill cell. The dummy fill pattern is formed from an array of the dummy fill cells. The dummy fill cell is configured to reduce the amount of undesirable layer-to-layer interaction, e.g., capacitance, between different material layers within the semiconductor device. The dummy fill cell includes regions associated with each of the material layers that include dummy fill. For example, a region of the dummy fill cell may be associated with a metal-1 layer and a separate region of the cell may be associated with a metal-2 layer. The configuration of the different regions is such that the likelihood of layer-to-layer interactions is reduced. In addition, the dummy fill pattern itself may be intelligently designed to contemplate possible layer-to-layer effects. The dummy fill pattern for a first material layer may be suitably designed such that the dummy fill of the first material layer does not reside above the circuit pattern for the underlying layer. Similarly, the dummy fill of the first material layer may be configured such that it does not lie below the circuit pattern for the abovelying layer.
PCT/US1999/016794 1998-09-29 1999-07-23 Dummy fill cell for reducing layer-to-layer interaction WO2000019490A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16257998A 1998-09-29 1998-09-29
US09/162,579 1998-09-29

Publications (2)

Publication Number Publication Date
WO2000019490A2 WO2000019490A2 (en) 2000-04-06
WO2000019490A3 true WO2000019490A3 (en) 2002-01-10

Family

ID=22586247

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/016794 WO2000019490A2 (en) 1998-09-29 1999-07-23 Dummy fill cell for reducing layer-to-layer interaction

Country Status (1)

Country Link
WO (1) WO2000019490A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10058078C1 (en) * 2000-11-23 2002-04-11 Infineon Technologies Ag Integrated circuit with analyzer protection has gaps left by first group of conducting tracks in wiring plane and filled by second group of conducting tracks provided for protection of IC
US6777813B2 (en) * 2001-10-24 2004-08-17 Micron Technology, Inc. Fill pattern generation for spin-on-glass and related self-planarization deposition
US7681166B2 (en) 2007-09-28 2010-03-16 Synopsys, Inc. Method and apparatus for performing dummy-fill by using a set of dummy-fill cells
US11334703B2 (en) 2017-06-29 2022-05-17 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit layouts with fill feature shapes

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278105A (en) * 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers
US5459093A (en) * 1993-03-18 1995-10-17 Sony Corporation Method for forming dummy pattern in a semiconductor device
US5763955A (en) * 1996-07-01 1998-06-09 Vlsi Technology, Inc. Patterned filled layers for integrated circuit manufacturing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5278105A (en) * 1992-08-19 1994-01-11 Intel Corporation Semiconductor device with dummy features in active layers
US5459093A (en) * 1993-03-18 1995-10-17 Sony Corporation Method for forming dummy pattern in a semiconductor device
US5763955A (en) * 1996-07-01 1998-06-09 Vlsi Technology, Inc. Patterned filled layers for integrated circuit manufacturing

Also Published As

Publication number Publication date
WO2000019490A2 (en) 2000-04-06

Similar Documents

Publication Publication Date Title
WO2000002253A3 (en) Silicon thin-film, integrated solar cell, module, and methods of manufacturing the same
TW200616140A (en) SER immune cell structure
TW363256B (en) Semiconductor integrated circuit, design and manufacturing method thereof
WO2005059930A3 (en) Printed circuit embedded capacitors
EP1308961A3 (en) Memory cell structure
TWI257122B (en) Semiconductor device and method for forming conductive path
JP2001176959A5 (en)
US6815619B2 (en) Circuit board
EP1239520A3 (en) Fabrication of memory devices
WO2006053163A3 (en) Protection of active layers of memory cells during processing of other elements
EP0813248A3 (en) Dielectrically isolated IC merged with surge protection circuit and method for manufacturing the same
WO2000019490A3 (en) Dummy fill cell for reducing layer-to-layer interaction
WO2002071482A8 (en) Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit
WO2002054494A3 (en) Integrated semiconductor memory arrangement and a method for producing the same
GB2364440A (en) Surface mount ic stacking method and device
US6380567B1 (en) Semiconductor device and fabrication method thereof
EP0155698A3 (en) A method for manufacturing a semiconductor integrated circuit device provided with an improved isolation structure
US6645809B2 (en) Process for producing a capacitor configuration
JPS5258491A (en) Semiconductor device
JPS5662353A (en) Semiconductor device and its manufacturing method
EP0469935A3 (en) Method for manufacturing a semiconductor memory device
JPS5720993A (en) Semiconductor storage device
JPH0322470A (en) Semiconductor integrated circuit
EP0163795A3 (en) A method and means for reducing signal propagation losses in very large scale integrated circuits
JP2551077B2 (en) Semiconductor integrated circuit device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
AK Designated states

Kind code of ref document: A3

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

122 Ep: pct application non-entry in european phase