WO2000014681A3 - Circuit chip comprising a specific connection area configuration - Google Patents

Circuit chip comprising a specific connection area configuration Download PDF

Info

Publication number
WO2000014681A3
WO2000014681A3 PCT/EP1999/006471 EP9906471W WO0014681A3 WO 2000014681 A3 WO2000014681 A3 WO 2000014681A3 EP 9906471 W EP9906471 W EP 9906471W WO 0014681 A3 WO0014681 A3 WO 0014681A3
Authority
WO
WIPO (PCT)
Prior art keywords
circuit chip
connection area
specific connection
area configuration
integrated circuit
Prior art date
Application number
PCT/EP1999/006471
Other languages
German (de)
French (fr)
Other versions
WO2000014681A2 (en
Inventor
Andreas Plettner
Karl Haberger
Original Assignee
Fraunhofer Ges Forschung
Andreas Plettner
Karl Haberger
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Ges Forschung, Andreas Plettner, Karl Haberger filed Critical Fraunhofer Ges Forschung
Publication of WO2000014681A2 publication Critical patent/WO2000014681A2/en
Publication of WO2000014681A3 publication Critical patent/WO2000014681A3/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention relates to a circuit chip comprised of a semiconducting substrate (2) having a front side and a rear side, whereby an integrated circuit (4) with a plurality of components is defined in the front side of the semiconducting substrate (2). The integrated circuit (4) comprises two connections which are provided for inserting or extracting signals and which can be interchanged without impairing the function of the integrated circuit (4). The circuit chip comprises merely two connection areas (10, 12) of which one (10) is arranged on the front side of the semiconducting substrate (2) and the other (12) is arranged on the rear side of the same, whereby each of the connection areas is connected to one of the interchangeable connections.
PCT/EP1999/006471 1998-09-03 1999-09-02 Circuit chip comprising a specific connection area configuration WO2000014681A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19840248.1 1998-09-03
DE1998140248 DE19840248A1 (en) 1998-09-03 1998-09-03 Circuit chip with specific pad arrangement

Publications (2)

Publication Number Publication Date
WO2000014681A2 WO2000014681A2 (en) 2000-03-16
WO2000014681A3 true WO2000014681A3 (en) 2000-06-02

Family

ID=7879729

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/EP1999/006471 WO2000014681A2 (en) 1998-09-03 1999-09-02 Circuit chip comprising a specific connection area configuration

Country Status (2)

Country Link
DE (1) DE19840248A1 (en)
WO (1) WO2000014681A2 (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6715675B1 (en) 2000-11-16 2004-04-06 Eldat Communication Ltd. Electronic shelf label systems and methods
DE10120408B4 (en) * 2001-04-25 2006-02-02 Infineon Technologies Ag Electronic component with a semiconductor chip, electronic assembly of stacked semiconductor chips and method for their production
US6770186B2 (en) 2001-11-13 2004-08-03 Eldat Communication Ltd. Rechargeable hydrogen-fueled motor vehicle
US7074509B2 (en) 2001-11-13 2006-07-11 Eldat Communication Ltd. Hydrogen generators for fuel cells
DE10161043B4 (en) * 2001-12-12 2005-12-15 Infineon Technologies Ag chip system
DE10356367B4 (en) 2003-11-28 2009-06-10 Georg Bernitz Method for producing a component and component
DE10358282A1 (en) * 2003-12-12 2005-07-28 Georg Bernitz Component and method for its production
DE102006048583B3 (en) * 2006-10-13 2008-01-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Component has two connections and four side surfaces with contact areas, where two side surfaces are opposite to each other, and contact areas of opposite side surfaces are connected with different connections
US8796137B2 (en) * 2010-06-24 2014-08-05 Stats Chippac, Ltd. Semiconductor device and method of forming RDL along sloped side surface of semiconductor die for z-direction interconnect

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621190A (en) * 1983-06-09 1986-11-04 Kabushiki Kaisha Toshiba Card with an IC module
NL9200885A (en) * 1992-05-20 1993-12-16 Nedap Nv Single-use disposable chip card
DE19628504A1 (en) * 1995-07-18 1997-01-23 Oki Electric Ind Co Ltd Labeling device with an integrated circuit capacitively coupled to an antenna and method for its production
US5739554A (en) * 1995-05-08 1998-04-14 Cree Research, Inc. Double heterojunction light emitting diode with gallium nitride active layer

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4249299A (en) * 1979-03-05 1981-02-10 Hughes Aircraft Company Edge-around leads for backside connections to silicon circuit die
US4549247A (en) * 1980-11-21 1985-10-22 Gao Gesellschaft Fur Automation Und Organisation Mbh Carrier element for IC-modules
US5223851A (en) * 1991-06-05 1993-06-29 Trovan Limited Apparatus for facilitating interconnection of antenna lead wires to an integrated circuit and encapsulating the assembly to form an improved miniature transponder device
US5374818A (en) * 1992-03-09 1994-12-20 Control Module Inc. Identification means with integral memory device
DE19654902C2 (en) * 1996-03-15 2000-02-03 David Finn Smart card

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4621190A (en) * 1983-06-09 1986-11-04 Kabushiki Kaisha Toshiba Card with an IC module
NL9200885A (en) * 1992-05-20 1993-12-16 Nedap Nv Single-use disposable chip card
US5739554A (en) * 1995-05-08 1998-04-14 Cree Research, Inc. Double heterojunction light emitting diode with gallium nitride active layer
DE19628504A1 (en) * 1995-07-18 1997-01-23 Oki Electric Ind Co Ltd Labeling device with an integrated circuit capacitively coupled to an antenna and method for its production

Also Published As

Publication number Publication date
DE19840248A1 (en) 2000-03-16
WO2000014681A2 (en) 2000-03-16

Similar Documents

Publication Publication Date Title
USD442222S1 (en) Card with an ornamental rectangle and IC chip
AU1330897A (en) Electroplated interconnection structures on integrated circuit chips
WO2002011501A1 (en) Wiring board
AU5607100A (en) Microfabricated transducers formed over other circuit components on an integrated circuit chip and methods for making the same
AU7889598A (en) Card mounted with circuit chip and circuit chip module
EP0892434A3 (en) RF IC package
AU7889698A (en) Circuit chip mounted card and circuit chip module
AU7889498A (en) Card mounted with circuit chip and circuit chip module
AU4648497A (en) Array of solder pads on an integrated circuit
AU6878398A (en) Chip with internal signal routing in external element
AU6053996A (en) Bear chip mounting printed circuit board
NO990099D0 (en) Integrated circuit board, as well as related application module
AU5378798A (en) Rf circuit module
EP0849793A3 (en) Improvements in or relating to integrated circuit device packages
WO1995016322A3 (en) Noise reduction
WO1999021175A3 (en) Integrated circuit layout methods and layout structures
WO2000014681A3 (en) Circuit chip comprising a specific connection area configuration
EP0942532A3 (en) Delay circuit
AUPO493597A0 (en) Logic circuit emulator
USD424628S (en) Symbol indicator for a gaming device
AU693964B2 (en) Delay detection circuit and low-noise oscillation circuit using the same
USD414752S (en) Electronic module enclosure
USD417241S (en) Advertising board
USD403597S (en) Combined watch and bracelet
USD408013S (en) Connection module for a PCB (printed circuit board)

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): US

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): US

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase