WO2000014681A2

WO2000014681A2 - Circuit chip comprising a specific connection area configuration

Info

Publication number: WO2000014681A2
Application number: PCT/EP1999/006471
Authority: WO
Inventors: Andreas Plettner; Karl Haberger
Original assignee: Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V.
Priority date: 1998-09-03
Filing date: 1999-09-02
Publication date: 2000-03-16
Also published as: WO2000014681A3; DE19840248A1

Abstract

The invention relates to a circuit chip comprised of a semiconducting substrate (2) having a front side and a rear side, whereby an integrated circuit (4) with a plurality of components is defined in the front side of the semiconducting substrate (2). The integrated circuit (4) comprises two connections which are provided for inserting or extracting signals and which can be interchanged without impairing the function of the integrated circuit (4). The circuit chip comprises merely two connection areas (10, 12) of which one (10) is arranged on the front side of the semiconducting substrate (2) and the other (12) is arranged on the rear side of the same, whereby each of the connection areas is connected to one of the interchangeable connections.

Description

Circuit chip with specific pad arrangement

description

The present invention relates generally to circuit chips and the arrangement of at least two pads on the same and in particular to ultra-thin circuit chips which are suitable for the construction of flat chip cards or electronic labels.

The development of contact-based and contactless chip cards has given rise to a completely new and rapidly growing market for electronic micro-systems. Integrated circuits are no longer only installed in large devices or handheld systems, but rather "naked" in chip cards. At the end of this development is the so-called disposable electronics, the first representative of which was the telephone card.

Disposable electronics require inexpensive chips or micro modules in ecologically acceptable carriers. In addition, increasingly flatter modules are required, particularly in the case of electronic labels, in which a contactless module, which consists of an integrated circuit, ie a circuit chip, and an antenna coil, is embedded between two papers. Such an electronic label requires a particularly flat design of the contactless module with a thickness application that is as small as possible, so as not to impair paper technology processes, such as printing, laminating, etc. In addition to paper, other thin, flexible substrates such as polymer films can also be used to produce electronic labels. The area of application for electronic labels ranges from goods labeling to tickets to security papers and beyond to the domain of today's chip cards. A number of special requirements must be made of the contacting technology for such thin chips. These refer to a low price, a low use of materials, easy contactability and above all a low overall height. The latter is essential if all advantages of thin chip technology are to be used.

In contrast to individual and, above all, power components, integrated circuits are generally connected to the peripheral circuitry by means of contacts which are planar in one plane, namely the useful surface of the semiconductor. In the simplest case, this peripheral circuitry is formed by the contact pins of a housing. In the case of special assembly techniques, for example chip-on-board technology, this peripheral circuitry is formed, for example, by conductor tracks on a substrate, which essentially corresponds to a conventional copper-clad printed circuit board. With regard to current contacting techniques, see for example the article "Packing trends: high-tech in the smallest format" H. Reichl u. a., Components, IC packaging, electronics 12/1998, referenced. In particular, flip-chip bonding techniques are described there, in which the assembly of the chip and the contacting take place simultaneously. The possibility of thin-film wiring is also described there. The use of such a flip chip method for contactless chip cards is also described in DE-A-19639902.

DE-C-4430812 describes a method for producing an ion-sensitive field-effect transistor with a rear-side contact. A method is described there to implement freely selectable vertical contacts between the component level and the rear side metallization. The component level is then contacted exclusively from the rear, so that the metallization is only on the side remote from the sample liquid, which increases the short-circuit protection. All known contacting methods are disadvantageous in the production of ultra-flat chip card modules or electronic labels, since on the one hand exact adjustment methods are required and on the other hand the contacts generated prevent a further reduction in the thickness of such modules.

The planar contact arrangement of conventional integrated circuits is based on their planar manufacture. This is based on the one-sided access to the surface and its structuring by means of lithographic processes. Conventional integrated circuits generally have from a few 10 in the case of memories to several 100 connections in the case of complex logic components, which are usually arranged on the edge of the integrated circuits as so-called connection pads. Typical pad dimensions are in the range of 70 μm in order to keep the requirements for the adjustment accuracy during testing and contacting within tolerable limits.

Circuit chips suitable for disposable electronics largely have different requirements. For example, integrated circuits for transponder modules, as the only peripheral circuitry, have a large-area inductance, ie an antenna coil and / or a capacitance, ie a dipole. The thickness of these external connection elements is typically a few micrometers. By means of the external connection elements, the integrated circuit draws its operating energy from an external high-frequency field and exchanges data with this high-frequency field. In the simplest case, this data exchange takes place by means of a data memory-programmed attenuation of the antenna circuit. Together with an integrated capacitor and a resistor, the antenna circuit forms a resonance circuit through a transistor that opens and closes and thus dampens the resonant circuit. Consequently, such an integrated circuit requires only two external connections for use in a transponder module. Here hardly pose Problems with heating, since the energy converted in the integrated circuit comes from the radiation field of the read / write device, is relatively small in accordance with the solid angle and is also only present for a short time.

The back of conventional circuit chips has long been provided with metallic coatings in order to achieve defined potential relationships and ohmic contact on the one hand and to be able to use various soldering processes on the other. A large number of metals come into question for this metallization, which are selected and combined according to their properties. These properties are, for example, the formation of a low-melting eutectic, the alloy behavior, the wetting behavior, the corrosion behavior, the behavior as a diffusion barrier and the mechanical strength. Typical known layer structures consist of combinations of Ti, TiN, W, Ni, Al, Au, Cr.

In addition, the usual function of a rear-side contact in conventionally packaged chips is to establish a mechanically and, above all, thermally well-conductive connection to the casing.

The object of the present invention is to create a circuit chip with a specific pad arrangement, which enables the simple and inexpensive production of ultra-flat chip cards or electronic labels.

This object is achieved by a circuit chip according to claim 1.

The present invention provides a circuit chip consisting of a semiconducting substrate with a front and a back, an integrated circuit with a in the front of the semiconducting substrate A plurality of components is defined. The integrated circuit has two connections which serve for signal coupling or signal coupling and can be interchanged without impairing the function of the integrated circuit. The circuit chip has only two pads, one on the front of the semiconducting substrate and one on the back thereof, each of the pads being connected to one of the interchangeable terminals.

According to the present invention, the integrated circuit has two connections for signal coupling or signal coupling and interchangeable without impairing the function of the integrated circuit, one of which is connected to the connection pad arranged on the front side, while the other of these is connected to the connection pad arranged on the rear side connected is. The two pads are therefore considered to be electrically equivalent. When the circuit chip according to the invention is used for a transponder module, it therefore has only two connection areas, one of which is arranged on the front side and essentially covers it, while the other is arranged on the rear side and essentially covers it.

As indicated above, the metallic contacts are preferably made over a large area, taking up a maximum of the entire chip area. This results in a very simple and therefore imprecise adjustment and contacting with low contact resistance. A low contact resistance is required to conduct the relatively high currents in the resonant circuit in the case of resonance. These determine the coil quality, which should be as high as possible in the sense of a narrow-band resonance.

The arrangement of the connection surfaces according to the invention enables, for example, a connection that is as flat as possible when using the circuit chip in a transponder module Connection surfaces with the peripheral components, whereby, as stated above, two connections are usually sufficient for a transponder module in order to ensure both the energy supply and the bidirectional data flow. This means that an extremely flat transponder module with a total thickness in the range of 10 μm can be implemented. This enables installation in or between thin substrates. In particular, the construction of the circuit chip according to the invention enables a very low-mass micro module, which plays a role in the material costs and in particular in the disposal in the case of disposable electronics. Given the small thickness of the circuit chip, typically in the range of 10 μm, a contact can be made on the back of the circuit chip by a number of methods. In addition, the provision of a connection area on the front side and a connection area on the rear side of the circuit chip maximizes the area occupied by the connection areas, so that the bonding process can be carried out both in a simplified and in an accelerated manner.

In preferred exemplary embodiments of the present invention, the two contacts are designed to be electrically equivalent, so that the installation orientation with regard to the alignment of the upper side or the lower side is arbitrary. Furthermore, large-area metallizations on the front or the back can take on further tasks, for example as light protection, as shielding, as equipotential bonding, as corrosion protection, as an attachment surface for magnetic or electrostatic handling, etc.

Moreover, the connection surfaces located on different main surfaces eliminate the risk of short circuits due to conductive adhesive and the like flowing into one another.

Thus, the circuit chip according to the invention is particularly suitable for installation in an insulation substrate, such that both main surfaces of the chip are essentially flush with it the main surfaces of the insulation substrate. A full-area metallization can preferably be provided on the underside of the insulation substrate, as a result of which contact is made with the connection area provided on the underside of the circuit chip. The contacting of the connection surface arranged on the upper side of the circuit chip can take place by means of a structured metallization, which is applied to this surface of the insulation substrate and the circuit chip.

Preferred exemplary embodiments of the present invention are explained in more detail below with reference to the accompanying drawings. Show it:

1 schematically shows a cross-sectional view of a circuit chip according to the invention;

2 shows a schematic cross-sectional view of a transponder module which contains a circuit chip according to the invention; and

Fig. 3 is a schematic representation illustrating how a metallization can be performed on the back of the circuit chip.

In Fig. 1, a simple embodiment of a circuit chip according to the invention is shown schematically. An integrated circuit 4 with a plurality of components is formed in the useful side of a semiconducting substrate 2. The semiconducting substrate 2 has a thickness of 10 μm, for example. Thin passivation layers 6 and 8 are applied to the top and bottom of the semiconducting substrate 2, respectively. A metal layer 10 and 12 with a thickness of typically 0.5 μm is provided on each of these passivation layers 6 and 8. The metal layer 10 is connected to the integrated circuit in the semiconducting substrate 2 via a conductive connection 14. Likewise, the metal layer 12 is on an arbitrary bige suitable way connected to the integrated circuit 4, as shown schematically by a connection 16 shown in dashed lines. The metal layers 10 and 12 are preferably connected to two connections of the integrated circuit serving for signal coupling or signal coupling, which are interchangeable without impairing the integrated circuit, so that the circuit chip can be contacted externally in any orientation by means of the connection surfaces 10 and 12. The passivation layers 6 and 8 serve to isolate the semiconductor substrate 2 from the connection areas which are formed by the metal layers 10 and 12. It should be noted that the passivation layer 8 is not necessarily present, as will be explained in more detail below.

The metal layers 10 and 12 can consist of any metal according to the specifications of the semiconductor technology and can be produced by means of the methods used there. Exemplary metals are Al, W, Cr, Ti, TiN, Cu or Au, as well as alloys and combinations thereof.

The conductive connection shown schematically at 16 in FIG. 1 can be implemented in different ways. For example, it can be implemented through a plated-through hole up to a suitably doped region of the integrated circuit. Alternatively, this conductive connection can be implemented via conductive structures provided on at least one side surface of the semiconducting substrate 2, two multilayer metallizations then being able to be provided on the useful side of the semiconductor substrate, which are used to connect the conductive structures provided on the side surface of the semiconductor substrate to a corresponding connection area serve the integrated circuit.

A plated-through hole for the conductive connection of the metal layer 12 can also be used up to a metallization level of a plurality of metallization levels on the useful side of the semiconducting substrate 2 are performed. For this purpose, one or more contact holes are first etched, the depth of which corresponds to the later chip thickness. If a galvanic separation is to take place between the semiconducting substrate 2 and the rear side metallization 12, plasma oxide is subsequently deposited isotropically in the contact hole for lateral isolation. This oxide is subsequently anisotropically etched at the bottom of the hole, whereupon the hole is filled with a metal, preferably tungsten. Following this, the semiconducting substrate is preferably still thinned in the wafer assembly until the semiconducting substrate has the desired thickness and the contact pin is exposed. The back is then metallized with one of the metals mentioned above. This method is particularly suitable for extremely thin chips, while thick chips are less suitable for this method due to the limited aspect ratio that can be achieved by etching.

Another possibility is to completely dispense with an additional galvanic isolation between the rear side metallization 12 and the semiconducting substrate 2. In this case, the passivation layer 8 on the back of the semiconducting substrate 2 is unnecessary. Thus, the rear side metallization 12 is connected directly to the substrate, care being taken to ensure that a sufficiently good ohmic contact is established between the metallization layer 12 and the semiconducting substrate. In order to achieve such a good ohmic contact, processing must take place on thin and mechanically no longer manageable wafers, this processing possibly involving temperature steps up to 450 ° C, which are not easily tolerated by thin wafers and in particular the components contained therein . Ion implantation combined with a short-term annealing process (RTP (RTP = rapid thermal processing), eg by laser) can be used as a method for achieving good ohmic contacts on the back of thinned wafers. Such more or less transient processes can also be carried out on a For example, thin chip wafers attached to a handling wafer by means of organic adhesives can be used advantageously. After this processing, the backside metallization is then applied.

If, as described above, the rear side metallization 12 is connected directly to the semiconducting substrate 2, suitable insulation of the semiconductor substrate 2 from the integrated circuit 4 must of course be provided. Such isolation can expediently be implemented by blocking diode paths to the CMOS wells of the integrated circuit that are usually used.

Alternatively, a conductive connection of the rear side metallization 12 to the integrated circuit 4 could be realized by the provision of suitably doped conductive areas.

2 shows a transponder module that contains a circuit chip according to the invention. The circuit chip 20 is introduced into a recess in an insulation substrate 22 such that both main surfaces of the circuit chip 20 are essentially flush with the main surfaces of the insulation substrate 22. A metallization layer 24 is preferably provided over the entire area on the rear side of the insulation substrate 22. A structured metallization 26, which defines an antenna device in the form of a coil, is provided on the front side of the insulation substrate 22 and on parts of the circuit chip 20. A connection end 28 of the coil is conductively connected to the front contact (not shown in FIG. 2) of the circuit chip 20. A second connection end 30 of the structured metallization 26 is connected via a via 32 through the insulation substrate 22 to the metallization layer 24 provided on the rear side of the insulation substrate 22. The metallization layer 24 contacts the rear side connection area (not shown in FIG. 2) of the circuit chip 20, so that this rear side connection is connected via the metallization layer 24 and the via 32 to the second connection end 30 of the structured metallization layer. It is thus obvious that the circuit chip according to the present invention enables extremely simple contacting and moreover enables the creation of a flat transponder module with a thickness between 10 and 50 μm, possibly below up to 5 μm. The contacting between the connection end 28 of the structured metallization 26 and the contacting between the metallization layer 24 and the circuit chip 20 can be carried out by any known contacting method.

FIG. 3 shows a schematic illustration of how a conductive structure can already be carried out on the edges of a circuit chip during the production of the circuit chips in order to produce a conductive connection to the rear side. 3 shows two semiconductor chips 40 which are applied to an auxiliary carrier 42. The integrated circuits in the chips 40 shown in FIG. 3 are formed in the upper regions thereof. The chips are separated by means of an anisotropic KOH etching, which causes the 54-degree edges shown. An insulation 44 and subsequently a metallization 46 can now advantageously optionally be applied to these beveled edges in order to produce the aforementioned conductive connection to the rear of the circuit chip.

A transponder module, as shown, for example, in FIG. 2, can have the following parameters, for example: frequency 13 MHz, L = 4 nH, C = 30 pF, resonant circuit quality> 20. The coil area can be approximately 2 to 100 square centimeters. As already stated, the thickness of the module should be in a range of 10 μm. This small thickness enables sufficiently low resistance values even with the substrate doping of 10 ¹⁴ cm ^-3 , which is common in CMOS technology, which leads to a specific resistance of 1 to 10 Ohmcm leads. This series resistance of the substrate enters into the resonant circuit resistance when it makes direct contact with the rear side connection area and must be as low as possible in order to ensure sufficient coil quality.

The circuit chip according to the present invention has a semiconducting substrate, which preferably consists of monocrystalline or polycrystalline silicon. However, the semiconducting substrate can also be replaced by other semiconductors or compound semiconductors, e.g. Gallium arsenide. Furthermore, the semiconducting substrate can be realized by semiconducting polymers.

Claims

claims

Circuit chip made of a semiconducting substrate (2) with a front and a back,

an integrated circuit (4) having a plurality of components is defined in the front of the semiconducting substrate (2),

The integrated circuit (4) has two connections which are used for signal coupling or signal coupling and can be exchanged without impairing the function of the integrated circuit (4),

the circuit chip having only two pads (10, 12), one (10) on the front of the semiconducting substrate (2) and one (12) on the back thereof, each of the pads connected to one of the interchangeable terminals is.

Circuit chip according to Claim 1, in which the connection areas (10, 12) are each arranged over a large area, essentially covering the front and the back.

Circuit chip according to Claim 1 or 2, in which the at least one connection area (12) on the rear side is connected to a connection of the integrated circuit via a through-connection through the circuit chip.

Circuit chip according to Claim 1 or 2, in which the connection surface (12) on the back is connected to a connection of the integrated circuit (4) via conductive structures provided on at least one side surface of the semiconducting substrate (2).

5. Circuit chip according to claim 1 or 2, wherein the pad (12) on the back is directly connected to the substrate.

6. Circuit chip according to one of claims 1 to 5, in which the connection surfaces consist of a metal layer which is formed from Al, W, Cr, Ti, TiN, Cu, Ni, Au or alloys thereof.

7. Circuit chip according to one of claims 1 to 6, wherein the semiconducting substrate (2) is an ultra-thin semiconductor substrate with a thickness of less than 50 microns.