WO2000013323A1 - Method for a general turbo code trellis termination - Google Patents

Method for a general turbo code trellis termination Download PDF

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Publication number
WO2000013323A1
WO2000013323A1 PCT/US1999/019148 US9919148W WO0013323A1 WO 2000013323 A1 WO2000013323 A1 WO 2000013323A1 US 9919148 W US9919148 W US 9919148W WO 0013323 A1 WO0013323 A1 WO 0013323A1
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Prior art keywords
tail
bits
output
constituent encoders
encoder
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Application number
PCT/US1999/019148
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French (fr)
Inventor
Mustafa Eroz
A. Roger Hammons, Jr.
Original Assignee
Hughes Electronics Corporation
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Publication date
Application filed by Hughes Electronics Corporation filed Critical Hughes Electronics Corporation
Priority to AU56854/99A priority Critical patent/AU5685499A/en
Priority to KR1020007004492A priority patent/KR100333469B1/en
Priority to JP2000568190A priority patent/JP3612022B2/en
Priority to EP99943834A priority patent/EP1050110B1/en
Publication of WO2000013323A1 publication Critical patent/WO2000013323A1/en

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2993—Implementing the return to a predetermined state, i.e. trellis termination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2996—Tail biting
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
    • H03M13/41—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors
    • H03M13/4123—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes using the Viterbi algorithm or Viterbi processors implementing the return to a predetermined state

Definitions

  • the present invention relates to methods for terminating both of the constituent encoders of a turbo code and developing puncturing patterns applicable at a trellis rermination stage that ensures the same number of transmitted bits for each trellis stage during the information bit transmission and trellis termination stages .
  • tail bits are inserted after information bits, to zero out all shift registers of an encoder.
  • tail birs are equal to zero.
  • me value of tail birs depend on the contents of trie shift register current values .
  • a turbo encoder consists of a parallel concatenation of rwo (2) or more recursive (feedback) convoiutional encoders. Because each constituent encoder processes the information bits m a different or ⁇ er ⁇ ue to a turbo mterleaver, it is not possible to terminate all constituent encoders by the same tail bits.
  • a trellis termination method general enough to be used for a set of turbo codes with different code rates as m the third generation CDMA systems is desirable. Included m the desirable general etno ⁇ is a method of puncturing tail bit sequences .
  • the present invention advantageously addresses the needs above as well as other needs by providing a method and apparatus for a general Turbo Code trellis termination which may be employed when a turbo encoder operates within a wide range of turbo code rares when transmitting information bits.
  • the invention can be characterized as a method of terminating two or more constituent encoders of a turbo encoder.
  • the method comprises the steps of: generating tail input bits ar each of two or more constituent encoders, including the step of deriving the rail input bits from each of the rwo or more constituent encoders separately from the contenrs of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; and puncturing one or ' more tail output bits such that 1/R tail output bits are transmitted for each of a plurality of trellis stages, wherein R is a turbo code rate employed by the turbo encoder during the information bit transmission.
  • the step of puncturing the one or more tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits only if they are sent from an output branch of one of the two or more constituent encoders that is used during information bit transmission.
  • FIG.l is a block diagram of a turbo encoder with interleaved bits entering a second encoder, for use in accordance with one embodiment of the present invention.
  • an exemplary turbo code encoder is shown wherein one embodiment of a Turbo Code trellis termination design terminates one encoder 10 (a first encoder) while disabling another encoder 10' (a second encoder) and at a different time terminates the other encoder 10' (second encoder) while disabling the encoder 10 (first encoder) .
  • the encoders (first and second encoders) 10, 10' of the turbo code encoder of FIG.l are constituent encoders configured in a parallel concatenation. It is well known in the art that a constituent encoder employ a configuration of modular adders 17, 20, 26, 28, 30, 24, and 25, and shift registers 18, 21, 22, coupled through nodes (such as node 32) to produce output bits, including rail output bits, X(t), Yo(t), Y-_(t), for example, depending upon the encoding scheme.
  • Interleaver 16 is employed between an input for X(t) and the second encoder 10', and wherein additionally, a puncturer 36 is employed, switchably coupled ro respective encoder outputs for each of the encoders (first and second encoders) 10, 10'.
  • tail input bits will mean the bits X, and X' in FIG. 1
  • rail output bits will mean the bits X, X', Yo, YcC , Yi or Yi ' .
  • Each of the constituenr encoders may utilize a fewer or greater number of shift registers than in FIG . 1 .
  • afrer message nits X(t) are enco ⁇ ed
  • a switch 12 is moved to a feedbac position to allow the generation of three (3) consecutive tail input bits, m th s example, generate ⁇ from the contents of each of three shift registers 18, 21, and 22 'also referred to herein as a first shift regisrer 18, a second shift register 21, and a third shift register 22) .
  • a number of tail input bits X(t), X' (t) for terminating a constituent encoder is equal to a number of shift registers m that encoder.
  • new tail input bits X(t), X' (t) are generated for zeroing out each respective shift register of the three shift registers, 18, 21 and 22.
  • the encoders In one embodiment of the invention the encoders
  • first encoder 10 is first terminated while the second encoder 10' is disabled, followed by the second encoder 10' being terminated while the first encoder 10 is disabled.
  • the encoders 10, 10' can be terminated m consecutive clock cycles, wherein six (6) consecutive clock cycle tail input bits X(t), X' (t) , consecutively terminate both the encoders 10, 10'.
  • a second tail input bit sequence 34' for terminating the secon ⁇ encoder 10' is fed back into the second encoder 10' through a switch 12' and circuit 14*.
  • Tail input bits X(t), X' (t ⁇ are nor interleaved by the turbo interleaver 16.
  • a tail input bit sequence 34 for terminating the first encoder 10 is fed back into the first encoder 10 through another switch 12 and another circuit 14.
  • the zeroing of the shift registers 18, 21, 22, prior to implementing a puncturing scheme per an embodiment of the invention, is triggered by a beginning and an ending tail input bit sequence X(t), X' (t), each sequence having a number n of tail input bits X(t), X' (t) equal to the number n of shift registers 18, 21, 22 or 18', 21, 22 coupled to each one of the encoders 10, 10'.
  • tail output bits X, Yo, Yi, X 1 , Yo, Y- ' are also punctured by the puncturer 36.
  • Table 1 indicates associated tail output bit puncturing patterns having indicator sequences (e.g., "Ill 000") identifying which bits to puncture and which bits to transmit.
  • the indicator sequence comprising “l”'s or “0”'s is selected m accordance with an encoder rate. In this notation, “1” indicates the tail output bit should be transmitted and “0” indicates that the tail output should be punctured.
  • Certain entries m Table 1 are labeled “repeat”, which means that transmitte ⁇ bits are transmitted twice.
  • tail input bit sequences 34, 34' which comprise tail input bits X, and X 1 , are generated after the encoders 10, 10' encode the information bits with the switches 12, 12' (FIG.l), while the switches 12, 12' are m an up position.
  • the first n/R tail output bits Xi, Y ⁇ , Y wherein n is the number of shift registers 18, 21, 22 or 18', 21', 22' per constituent encoder (n 3 m FIG.l), ana wherein R is a t ⁇ rbo co ⁇ e rate being employed, are generated by clocking tne first encoder 10 n times w rn its switch 12 in the down position while the second encoder 10' is not clocked, and puncturing or repeating the resulting rail output bits Xi, Y 0 , Yi, X', Y c ' , Y: ' according to Table 1 below.
  • the lasr n/R tail outpur bits X',Yo',Yi' are generated by clocking the second encoder 10' n timer with its switch 12' in the down position while the first encoder 10 is not clocked, and puncturing or repeating the resulting tail output bits according to Table 1. These final output bits are denoted by X', Y c ' or Yi ' .
  • the tail output bits for each of a first n tail input bit are XYo
  • the tail output bits for each of a last n tail bit periods are X ' Yc '
  • the tail output bits for each of the first n tail input bits are XXYcY
  • the tail ourput bits for each of the lasr n tail bits are X ' X ' Yo '
  • the tail output bits for each of the first n tail input bits are XXYoYi and the tail output bits for each of the last n tail input bits periods are X ' X ' Yo ' Yi ' .
  • Tail inputs bits are not interleaved by the interleaver 16. They are added after the encoding of the information bits.
  • the row designation "repeat” means that for a rate 1/3 or a rate 1/4 turbo code, when transmitted, the bits X and X' are transmitted twice .
  • the puncturing table is read first from top to bottom, and then from left to right.
  • the puncturing table is read first from top to bottom, repeating X(t) and X' (t) , and then from left to right .
  • the puncturing patterns in Table 1 are chosen so that:
  • a number of transmitted rail output bits during trellis termination is 1/R for each trellis branch wherein R is the turbo code rate employed during information bit transmission.
  • R is the turbo code rate employed during information bit transmission.
  • X(t) and X' (t) are selected to be repeated in both the turbo code rate 1/3 and rate 1/4 cases.
  • Table 1 may also be employed irrespective of whether the encoders 10, 10' are terminated concurrently or non-concurrently.
  • tail output bit is selected to be repeated, such as, for example that corresponding to Yo(t) and Yn ' (t) .
  • a code rate lower than 1/4 it may be necessary ro repeat more than one tail output bit per encoder 10, 10', m which case an additional tail bit besides X(t) may be repeated, such as repeating X(t) and Yo(t) or repeating X(t) twice or any combination whatsoever.

Abstract

A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, comprising the step of: generating tail input bits at each of two or more constituent encoders, including deriving the tail input bits from each of the two or more constituent encoders separately from a contents of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; puncturing one or more tail output bits such that 1/R output tail bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission. In yet another variation, the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits, only if they are sent from an output branch of one of the two or more constituent encoders that are used during information bit transmission.

Description

METHOD FOR A GENERAL TURBO CODE TRELLIS TERMINATION
This applications claims benefit of U.S. Provisional Application Serial No. 60/098,111, filed August 27, 1998.
BACKGROUND OF THE INVENTION
The present invention relates to methods for terminating both of the constituent encoders of a turbo code and developing puncturing patterns applicable at a trellis rermination stage that ensures the same number of transmitted bits for each trellis stage during the information bit transmission and trellis termination stages .
The process of forward and reverse link turbo encoding and decoding, specifically for Code Division Multiple Access (CDMA) communications channels, is thoroughly described in copending U.S. Patent Application Serial No. 09/248,338 (Attorney Docket No. PD-980024) of Eroz, et al., for SETS OF RATE-COMPATIBLE UNIVERSAL TURBO CODES NEARLY OPTIMIZED OVER VARIOUS RATES AND INTERLEAVER DELAYS, filed 2/11/99, and copending United States Patent Application Serial No. 09/235,582, (Attorney Docket No. PD-980163) of Eroz, et al., for FORWARD ERROR CORRECTION SCHEME FOR DATA CHANNELS USING UNIVERSAL TURBO CODE, filed 1/22/99, both of which are incorporated herein by reference.
In a convolutional encoding scheme, tail bits are inserted after information bits, to zero out all shift registers of an encoder. For feed forward encoders, tail birs are equal to zero. For feedbacK encoders me value of tail birs depend on the contents of trie shift register current values .
A turbo encoder consists of a parallel concatenation of rwo (2) or more recursive (feedback) convoiutional encoders. Because each constituent encoder processes the information bits m a different orαer αue to a turbo mterleaver, it is not possible to terminate all constituent encoders by the same tail bits.
A trellis termination method general enough to be used for a set of turbo codes with different code rates as m the third generation CDMA systems is desirable. Included m the desirable general etnoα is a method of puncturing tail bit sequences .
SUMMARY OF THE INVENTION
The present invention advantageously addresses the needs above as well as other needs by providing a method and apparatus for a general Turbo Code trellis termination which may be employed when a turbo encoder operates within a wide range of turbo code rares when transmitting information bits.
In its most general form, the invention can be characterized as a method of terminating two or more constituent encoders of a turbo encoder. The method comprises the steps of: generating tail input bits ar each of two or more constituent encoders, including the step of deriving the rail input bits from each of the rwo or more constituent encoders separately from the contenrs of shift registers within each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; and puncturing one or' more tail output bits such that 1/R tail output bits are transmitted for each of a plurality of trellis stages, wherein R is a turbo code rate employed by the turbo encoder during the information bit transmission.
In yet another variation, the step of puncturing the one or more tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits only if they are sent from an output branch of one of the two or more constituent encoders that is used during information bit transmission. BRIEF DESCRIPTION OF THE DRAWINGS
The above and other aspects, features and advantages of the present invention will be more apparent from the following more particular description thereof, presented in conjunction with the following drawings wherein:
FIG.l is a block diagram of a turbo encoder with interleaved bits entering a second encoder, for use in accordance with one embodiment of the present invention.
Corresponding reference characters indicate corresponding components throughout the several views of the drawings .
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
The following description of the presently contemplated best mode of practicing the invention is not to be taken in a limiting sense, but is made merely for the purpose of describing the general principles of the invention. The scope of the invention should be determined with reference ro the claims.
Referring to FIG. 1, an exemplary turbo code encoder is shown wherein one embodiment of a Turbo Code trellis termination design terminates one encoder 10 (a first encoder) while disabling another encoder 10' (a second encoder) and at a different time terminates the other encoder 10' (second encoder) while disabling the encoder 10 (first encoder) .
The encoders (first and second encoders) 10, 10' of the turbo code encoder of FIG.l are constituent encoders configured in a parallel concatenation. It is well known in the art that a constituent encoder employ a configuration of modular adders 17, 20, 26, 28, 30, 24, and 25, and shift registers 18, 21, 22, coupled through nodes (such as node 32) to produce output bits, including rail output bits, X(t), Yo(t), Y-_(t), for example, depending upon the encoding scheme. FIG. 1 is just one example of such a parallel concatenation of constituent encoders, wherein an interleaver device (Interleaver) 16 is employed between an input for X(t) and the second encoder 10', and wherein additionally, a puncturer 36 is employed, switchably coupled ro respective encoder outputs for each of the encoders (first and second encoders) 10, 10'. As described herein, tail input bits will mean the bits X, and X' in FIG. 1, and rail output bits will mean the bits X, X', Yo, YcC , Yi or Yi ' . In other turbo encoders, there may be more than two constituenr encoders. Each of the constituenr encoders may utilize a fewer or greater number of shift registers than in FIG . 1 . In- FIG. 1, afrer message nits X(t) are encoαed, a switch 12 is moved to a feedbac position to allow the generation of three (3) consecutive tail input bits, m th s example, generateα from the contents of each of three shift registers 18, 21, and 22 'also referred to herein as a first shift regisrer 18, a second shift register 21, and a third shift register 22) . In general, a number of tail input bits X(t), X' (t) for terminating a constituent encoder is equal to a number of shift registers m that encoder.
At the end of each clock cycle, new tail input bits X(t), X' (t) are generated for zeroing out each respective shift register of the three shift registers, 18, 21 and 22. In one embodiment of the invention the encoders
10, 10' are terminated simultaneously within three clock cycles, each with its own tail input bit X(t), X' (t) . Alternatively, the first encoder 10 is first terminated while the second encoder 10' is disabled, followed by the second encoder 10' being terminated while the first encoder 10 is disabled.
In the variation with the encoders 10, 10' terminated at different times the encoders 10, 10' can be terminated m consecutive clock cycles, wherein six (6) consecutive clock cycle tail input bits X(t), X' (t) , consecutively terminate both the encoders 10, 10'.
As can be seen from FIG. 1, a second tail input bit sequence 34' for terminating the seconα encoder 10' is fed back into the second encoder 10' through a switch 12' and circuit 14*. Tail input bits X(t), X' (tϊ are nor interleaved by the turbo interleaver 16. Similarly, a tail input bit sequence 34 for terminating the first encoder 10 is fed back into the first encoder 10 through another switch 12 and another circuit 14.
The zeroing of the shift registers 18, 21, 22, prior to implementing a puncturing scheme per an embodiment of the invention, is triggered by a beginning and an ending tail input bit sequence X(t), X' (t), each sequence having a number n of tail input bits X(t), X' (t) equal to the number n of shift registers 18, 21, 22 or 18', 21, 22 coupled to each one of the encoders 10, 10'.
As wirh information and coded bits, tail output bits X, Yo, Yi, X1, Yo, Y- ' are also punctured by the puncturer 36.
Table 1 indicates associated tail output bit puncturing patterns having indicator sequences (e.g., "Ill 000") identifying which bits to puncture and which bits to transmit. The indicator sequence, comprising "l"'s or "0"'s is selected m accordance with an encoder rate. In this notation, "1" indicates the tail output bit should be transmitted and "0" indicates that the tail output should be punctured. Certain entries m Table 1 are labeled "repeat", which means that transmitteα bits are transmitted twice.
The tail input bit sequences 34, 34', which comprise tail input bits X, and X1, are generated after the encoders 10, 10' encode the information bits with the switches 12, 12' (FIG.l), while the switches 12, 12' are m an up position. The first n/R tail output bits Xi, Yσ, Y wherein n is the number of shift registers 18, 21, 22 or 18', 21', 22' per constituent encoder (n=3 m FIG.l), ana wherein R is a tαrbo coαe rate being employed, are generated by clocking tne first encoder 10 n times w rn its switch 12 in the down position while the second encoder 10' is not clocked, and puncturing or repeating the resulting rail output bits Xi, Y0, Yi, X', Yc ' , Y: ' according to Table 1 below. The lasr n/R tail outpur bits X',Yo',Yi' are generated by clocking the second encoder 10' n timer with its switch 12' in the down position while the first encoder 10 is not clocked, and puncturing or repeating the resulting tail output bits according to Table 1. These final output bits are denoted by X', Yc ' or Yi ' .
For rate 1/2 turbo codes, the tail output bits for each of a first n tail input bit (also referred ro herein as "the beginning tail bit sequence X(t)") are XYo, and the tail output bits for each of a last n tail bit periods (also referred to herein as "the ending tail bit sequence X' (t)") are X ' Yc ' . For rate 1/3 turbo codes, the tail output bits for each of the first n tail input bits are XXYcY , and the tail ourput bits for each of the lasr n tail bits are X ' X ' Yo ' . For a rate 1/4 turbo code, the tail output bits for each of the first n tail input bits are XXYoYi and the tail output bits for each of the last n tail input bits periods are X ' X ' Yo ' Yi ' .
Tail inputs bits are not interleaved by the interleaver 16. They are added after the encoding of the information bits.
TABLE 1: Puncturing Patterns for Tail Output Bits
Figure imgf000009_0001
Figure imgf000010_0001
When employing Table 1 to design puncturing patterns for tail output bits, the row designation "repeat" means that for a rate 1/3 or a rate 1/4 turbo code, when transmitted, the bits X and X' are transmitted twice .
For a rate 1/2 turbo code, the puncturing table is read first from top to bottom, and then from left to right. For a rate 1/3 turbo code and a rate 1/4 turbo code, the puncturing table is read first from top to bottom, repeating X(t) and X' (t) , and then from left to right .
The puncturing patterns in Table 1 are chosen so that:
y
(1) A number of transmitted rail output bits during trellis termination is 1/R for each trellis branch wherein R is the turbo code rate employed during information bit transmission. Advantageously, this condition ensures that the same turbo code rate is used for trellis termination as for information bit transmission.
(2) Only output branches of the encoders 10, 10' used during information bit transmission are used for trellis termination. For example, for rate 1/2 and rate 1/3 turbo coders, only X(t), X' (t) , Yo(t) and Y'o(t) are transmitted during information bit transmission; Yι(t) and Y'ι(t) are always punctured. Therefore, only X(t), X'(t), Yo(t) and Y'o(t) are transmitted during the trellis termination stage, as well. Advantageously, therefore, if a manufacturer only wanted to implement a rate 1/2 and encoder, such a manufacturer would only have to implement transmissions of bits from branches X, Yo or X', Yo ' .
(3) In order to meet conditions (1) and (2), it may require repetition of some tail output bits during trellis termination. That is, to both keep the turbo code rate the same, and to only use output branches used in information bit transmission, it may be necessary to repeat one or more of the tail bits for each encoder 10, 10^ in order to keep the turbo code rate the same.
In the preferred embodiment illustrated by Table 1, X(t) and X' (t) are selected to be repeated in both the turbo code rate 1/3 and rate 1/4 cases. Table 1 may also be employed irrespective of whether the encoders 10, 10' are terminated concurrently or non-concurrently.
Alternative embodiments are envisioned, in keeping within the spirit of the invention wherein another tail output bit is selected to be repeated, such as, for example that corresponding to Yo(t) and Yn ' (t) .
Alternatively, where a code rate lower than 1/4 is employed it may be necessary ro repeat more than one tail output bit per encoder 10, 10', m which case an additional tail bit besides X(t) may be repeated, such as repeating X(t) and Yo(t) or repeating X(t) twice or any combination whatsoever.
While the invention herein disclosed has been described by means of specific embodiments and applications thereof, numerous modifications and variations could be made thereto by those skilled m rhe arr without departing from the scope of the invention set forth m the claims .

Claims

What is claimed is: 1. A method of terminating two or more constituent encoders of a turbo encoder employing a turbo code, the method comprising the steps of: generating tail input bits at each of two or more constituent encoders, including the step of: deriving the tail input bits from each of the two or more constituent encoders separately for each constituent encoder from a contents of shift registers wi.thin each of the two or more constituent encoders, after an encoding of information bits by the two or more constituent encoders; and puncturing one or more tail output bits such that 1/R tail output bits are transmitted for each of a plurality of trellis branches, wherein R is a turbo code rate employed by the turbo encoder during an information bit transmission.
2. The method of Claim 1 wherein the step of puncturing the tail output bits further comprises the step of: transmitting, during trellis termination, the tail output bits only if they are sent from an output branch of one of the two or more constituent encoders that is used during information bit transmission.
3. The method of Claim 2 wherein the step of transmitting comprises the steps of: transmitting tail output bits from a first X(t) output branch and from a second Yo(t) output branch, when the turbo encoder is employed as a rate 1/2 turbo encoder, during trellis termination of a firsr of the two or more constituent encoders; and transmitting tail output bits from a third X' (t) output branch and from a fourth Yc ' (t) output branch, when the turbo encoder is employed as a rate 1/2 turbo encoder, during trellis termination of a second of the two or more constituent encoders .
4. The method of Claim 2 wherein, when the turbo encoder is employed as a rate 1/3 turbo encoder, the step of transmitting comprises the steps of: transmitting tail output bits from a first X(t) output branch, and a second Yo(t) output branch, during trellis termination of a first of the two or more constituent encoders; re-transmitting tail output bits from the first X(t) output branch during trellis termination of the first of the two or more constituent encoders; transmitting tail output bits from a third X' (t) output branch and from a fourth Yo ' (t) output branch, during trellis termination of a second of the two or more constituent encoders; and re-transmitting tail output bits from the third X' (t) output branch during trellis termination of the second of the two or more constituent encoders.
5. The method of Claim 2 wherein, when the turbo encoder is employed as a rate 1/4 turbo encoder, the step of transmitting comprises the steps of: transmitting tail output bits from a first X(t; output branch, a second Yo(t) output branch, and a third Y╬╣(t) output branch during trellis termination of a first of the two or more constituent encoders; re-transmitting tail output bits from the first X(t) output branch during trellis termination of the first of the two or more constituent encoders; transmitting tail output bits from a fourth X' (t) output branch, a fifth Yc ' (t) output branch, and a sixth Yi ' (t) output branch during trellis termination of a second of the two or more constituent encoders; and re-transmitting tail output bits from the fourth X' (t) output branch during trellis termination of the second of the two or more constituent encoders .
6. The method of Claim 1 wherein the step of generating the tail input bits is performed simultaneously at each of the two or more constituent encoders, wherein tail input bits from a first constituent encoder are generated at same clock cycles from a second constituent encoder.
7. The method of Claim 1 wherein the step of generating the tail input bits is performed consecutively at each of the two or more constituent encoders, wherein tail input bits from a first constituent encoder are generated at different clock cycles than tail input bits from a second constituent encoder.
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