WO2000008554A1

WO2000008554A1 - Apparatus with program memory and processor

Info

Publication number: WO2000008554A1
Application number: PCT/EP1999/005514
Authority: WO
Inventors: Jan Hoogerbrugge; Hendrikus W. J. Van De Wiel
Original assignee: Koninklijke Philips Electronics N.V.
Priority date: 1998-08-07
Filing date: 1999-07-29
Publication date: 2000-02-17

Abstract

The apparatus comprises a program memory for storing instruction opcodes and a processor for executing the instruction opcodes read from the program memory. The apparatus also includes a decoder for decoding an instruction opcode on the basis of the address at which the instruction code has been stored in the memory.

Description

Apparatus with program memory and processor.

The invention relates to an apparatus comprising a program memory for storing instructions at particular addresses in the program memory and also comprising a processor for executing a particular instruction stored in the program memory.

The invention also relates to a method of executing a program, instructions of which are stored at particular addresses in a program memory, the method comprising the steps of reading a particular instruction from the program memory and executing the particular instruction by a processor.

The invention also relates to a system for generating an executable program, the system comprising translation means for translating a source program into a sequence of instructions and coding means for coding the instructions into respective bit patterns to be stored in a program memory.

In such an apparatus, the instructions constitute part of the embedded software that provides a desired functionality of the apparatus. Examples of such apparatus are a portable telephone and a complex television set. In a portable telephone, the support of the communication protocols and the many user features, like maintaining and dialling from a directory with telephone numbers, are realized by the embedded software, requiring a comparatively large program memory and a powerful processor. In a complex television set signal processing and the many user features, like favorite channel selection and on-screen- display, are realized in embedded software. The embedded software of such apparatus contains a large number of program instructions which consist of an operation part and optionally one or more operands. It is known to encode the operation part of the program instructions into so-called instruction opcodes and to store these instruction opcodes and any operands in a program memory of the apparatus. The required number of different opcodes determines the size of the code to be used, i.e. the number of bits in the bit pattern needed to represent the opcode. A typical example is to use an opcode having a width of 8 bits, thus allowing 256 different opcodes. While running the program, an instruction is read from the program memory and executed by the processor of the apparatus. The instructions are read and executed in the order as they are stored in the program memory, unless execution of an instruction causes a jump to another position in the program. The number of program instructions may be very large so that a comparatively large program memory is required. Such a large program memory contributes significantly to the cost of the apparatus.

It is an object of the invention to provide an apparatus of the kind set forth which enables more efficient storage of the software. This object is achieved according to the invention in an apparatus which is characterized in that it also comprises a decoder for decoding the particular instruction on the basis of the address of the particular instruction. In the decoder the meaning of an instruction is not only derived from the bit pattern stored in the program memory, but also from the position where the bit pattern is stored in the program memory. Decoding the instruction may affect the opcode part of the instruction, the operand part of the instruction or both. If it is the opcode part that is affected, a given number of different opcodes can be represented in a shorter bit pattern per opcode. This means that the program memory for storing the instructions of a given program may be designed so as to be smaller. Alternatively, a larger program with more instructions can be stored using the same program memory capacity. The invention is based on the insight that program instructions may be moved inside the program memory while maintaining the same operation for the program as a whole, and that this property can be employed for encoding part of the meaning of an instruction into its address. An example is to encode a first opcode and a second opcode as one and the same bit pattern and to store this bit pattern in the lower part of the program memory to represent the first opcode and in the upper part of the program memory to represent the second opcode.

An embodiment of the apparatus according to the invention is defined in Claim 2. In this embodiment, the information conveyed by the position of the instruction in the program memory is added as one or more bits to the bit pattern retrieved. This results in an extended instruction to be executed by the processor. In this way, application of the invention is kept transparent to the processor which executes the extended instruction while in the program memory a shorter instruction was stored.

An embodiment of the apparatus according to the invention is defined in Claim 4. Extending the instruction opcode read from the program memory with the least significant bit of the address where the instruction is stored is a very advantageous way to realize a shorter bit pattern per opcode for storage in the program memory. The decoder in this embodiment can be realized as a very simple device, since it only needs to copy the value of the least significant bit of the address of the instruction to the least significant bit of the extended instruction opcode. In this embodiment the task of generating a program for the apparatus and storing its instructions in the program memory is also a comparatively simple. Initially, the instruction opcodes are generated and encoded into full-length bit patterns, each opcode thus being given its uniquely encoded bit pattern. The opcodes are subsequently stored in the program memory; opcodes with an even bit pattern are then allocated to even addresses and opcodes with an odd bit pattern to odd addresses. In both cases the least significant bit is discarded and only the remaining bits are stored in the program memory at the allocated addresses. If necessary for correct allocation, the compiler may move and swap instructions in the program for as long as the semantics of the program is not affected, i.e. for as long as the external effects of the program remain the same. Furthermore, the compiler may insert a pseudo instruction with no actual operation to obtain the required allocation of instructions. The organization of instructions into some desired sequence in the program is a known compiler task and is carried out, for example, to obtain optimization of the program. The above even-odd allocation of respective instructions can be carried out by the compiler and may be regarded as an optimization step.

It is a further object of the invention to provide a method of the kind set forth which enables more efficient storage of the software. This object is achieved according to the invention by a method which is characterized in that prior to the execution of the particular instruction, the particular instruction is decoded on the basis of the address of the particular instruction. Due to this decoding, the meaning of an instruction can be coded into a combination of a bit pattern and the position where this bit pattern is stored in the program memory. This makes it possible to use a shorter bit pattern to represent the same number of different instructions. Therefore, a program comprising a certain number of instructions requires a smaller memory for storing these instructions. It is a further object of the invention to provide a system of the kind set forth which generates an executable program that may be stored in a more efficient way. This object is achieved according to the invention by a system which is characterized in that the encoding means are arranged to encode a particular instruction into a shortened bit pattern and to allocate this shortened bit pattern to an address in the program memory on the basis of the instruction.

Further advantageous embodiments of the invention are disclosed in the dependent claims. The invention and its attendant advantages will be further elucidated with the aid of exemplary embodiments and the accompanying schematic drawings, therein:

Figure 1 schematically shows some elements of the apparatus according to the invention, Figure 2 shows an embodiment of the apparatus according to the invention,

Figure 3 shows an alternative embodiment of the apparatus according to the invention, Figure 4 schematically shows a compiler for generating a program according to the invention, and

Figure 5 shows the most important components of the system for generating an executable program according to the invention.

Corresponding features in the various Figures are denoted by the same references. Figure 1 schematically shows some elements of the apparatus according to the invention. The apparatus includes a program memory 102 with a number of storage spaces, like storage space 104, for storing a bit pattern representing an instruction opcode. Each storage space has a unique address allowing the retrieval of previously stored bit patterns. The apparatus also includes a processor 106 for executing an instruction when the opcode of that instruction has been read from the memory 102. The memory 102 of the apparatus is preferably a Read Only Memory (ROM) or a Programmable Read Only Memory (PROM). The instruction opcodes in the program memory form the embedded software of the apparatus which need not be modified at run-time. The apparatus is provided with the memory with the instruction opcodes upon manufacture. If the software of the apparatus must be updated, it will either receive a new ROM or, in the case of a PROM, new instruction opcodes are downloaded in the program memory. The apparatus also includes a decoder 108 that decodes the instruction opcode read from the program memory before execution by the processor. In the preferred embodiment, a bit pattern is read from a storage space at a given address and is extended with an additional bit at the least significant position. The decoder gives the new least significant bit the same value as the least significant bit of the address wherefrom the bit pattern has been read. So the bit pattern of the instruction opcode stored in the program is 1 bit shorter than the bit pattern executed by the processor. Storing the shorter bit pattern means that less memory capacity is necessary to store a given number of instruction opcodes than when the full-length bit pattern were stored.

A small program fragment illustrating the storage of the instruction opcodes in the program memory is given below. The following table shows the sequence of program instructions to be executed by the program fragment. On each line there is given: the address that the instruction should get, the operation part of the instruction and the operands on which the operation should operate. Furthermore, a short explanatory comment of each instruction is given.

Address Instruction

Operation Operand Comment

000 MOV r0, #0 ; move value 0 to register 0 001 MOV ι4, #l ; move value 1 to register 4 002 LDR r5, 0x80e0 ; load register 5 with value at address 0x80e0 003 STR rO, [r5, #8] ; load register 0 with value at address r5+8 004 BL 0x812c ; sub routine call to function at 0x812c 005 MOV r0, #7 ; move value 7 to register 0 006 BL 0x8150 ; sub routine call to function at 0x8150 007 ADD r4, ι4, #1 ; increment value in register 4 008 CMP r4, #5 ; compare value in register 4 with value 5 009 BLE 0x8 lf8 ; if less or equal, jump to address 0x8 lf8

The operation parts of the instructions are encoded into 8-bit instruction opcodes as follows:

MOV 00000010 and 00000011

LDR 00000111

STR 00001011

BL 00010010

ADD 00010011

CMP 00100010

BLE 00100011

The instruction opcodes of the program fragment are stored in the program memory according to the following table. Address Opcode

000 0000001

001 0000011

002 0000001

003 0000101

004 0001001

005 0000001

006 0001001

007 0001001

008 0010001

009 0010001

The operand or operands of each instruction are encoded and stored immediately after the respective opcodes. This is not shown in the table for reasons of clarity, because in this example the invention is only applied to the opcodes. As described above, the decoder adds to the stored bit pattern a least significant bit which has the same value as the least significant bit of the address. This extended bit pattern is the instruction opcode that is executed by the processor. So the decoder adds a '0' to bit patterns stored at even addresses and a '1' to bit patterns stored at odd addresses. The result for each of the instruction opcodes stored in the program memory is shown in the third column of the table below.

Address Opcode Extended opcode (after decoding)

000 0000001 00000010

001 0000011 00000111

002 0000001 00000010

003 0000101 00001011

004 0001001 00010010

005 0000001 00000011

006 0001001 00010010

007 0001001 00010011 008 0010001 00100010

009 0010001 00100011

As is shown above, an 8-bit instruction opcode is stored in a 7-bit pattern in the program memory, its least significant bit not being put into the 7-bit pattern but being retained in the form of the least significant bit of the address. An example in the above program fragment is the 7-bit pattern '0010001' stored at the address 008 and at the address 009. The pattern at the address 008 is extended to '00100010', representing the CMP-instruction. The pattern at the address 009 is extended to '00100011', representing the BLE-instruction. The same is true for the BL-instruction and the ADD-instruction, which are both stored as the 7-bit pattern

'OOOlOO . This demonstrates that the same number of different 8-bit opcodes can be encoded in fewer different 7-bit patterns. The generating of a program to be stored as described above will be described hereinafter with reference to Figure 4.

Application of the invention by reducing the number of bits per stored opcodes achieves a larger relative reduction in storage space when a comparatively large portion of the instructions have no operands. This is the case, for example in a stack machine.

In the above example, the reduction of the bit pattern of the instruction stored in memory is realized by reducing the bit pattern of the opcode. Alternatively, or additionally, the bit pattern encoding the operand of the instruction may be reduced when storing the instruction in the memory. An example in this respect is the following instruction:

OPCODE I DST_REG | SRC_REG

Therein: OPCODE is the 8-bit pattern encoding a MOV-instruction,

DSTJREG is the 4-bit pattern encoding the destination register of the MOV-instruction, and SRC_REG is the 4-bit pattern encoding the source register of the MOV-instruction. When storing this instruction, the least significant bit of DST_REG is discarded and the instruction is stored at an address whose least significant bit has the same value as the discarded bit of DST_REG. When at run-time the instruction is read from memory, the decoder adds the least significant bit of the address to the 3-bit pattern of DST_REG, thus restoring the original 4-bit pattern. Application of the invention makes that the stored bit pattern encoding the instruction is 1 bit shorter than the original bit pattern. The stored bit pattern has a length of 15 bits whereas that of the original bit pattern is 16 bits. According to the above example, a move instruction to an even register must be stored at an even address and a move instruction to an odd register must be stored at an odd address.

Figure 2 shows an embodiment of the apparatus according to the invention. The apparatus 200 comprises a program memory 102 for storing instruction opcodes and a processor 106 for executing instructions. The apparatus also includes a decoder 108 that extends the bit pattern stored in the program memory. As described above, it adds to the bit pattern a new least significant bit which is given the same value as the least significant bit of the address. The apparatus comprises a bus 202 for the communication of data and addresses between the various parts of the apparatus. Furthermore, the bus is connected to other parts of the apparatus not shown here, which parts are controlled by the processor and/or are intended to enter information into the processor. The connections to those parts are symbolized by interface 204. The decoder 108 in this embodiment of the apparatus the decoder 108 is closely coupled to the program memory 102. The program memory 102 and the decoder 108 together can be viewed as a larger program memory 206. The fact that the program memory 102 stores 7-bit opcodes is hidden by the decoder 108 that extends them to 8-bit opcodes. The invention can thus be applied without it being necessary to modify the processor 106 or other part of the apparatus 200. The apparatus seems to comprise a program memory that stores 8-bit opcodes and application of the invention is kept transparent for the rest of the apparatus.

Figure 3 shows an alternative embodiment of the apparatus according to the invention. The apparatus 300 comprises a program memory 102, a decoder 108, a processor 106, a bus 202 and an interface 204 which function as described with reference to Figure 2. The decoder 108 in the apparatus 300 is closely coupled to processor 106. Processor 106 and decoder 108 can together be viewed as a new processor 302 that is specifically arranged to process the 7-bit instruction opcodes stored in program memory 102 and transferred to the processor via the bus 202.

Figure 4 schematically shows a compiler for generating a program according to the invention. A source program 402 written in a high level language like the C programming language is translated into an intermediate representation 406 by a translation unit 404. The intermediate representation 406 is based on instructions that can be executed by the processor on which the program will be run. An encoding unit 408 encodes the instructions and determines the order in which the instructions are to be executed. Furthermore, it allocates addresses for the instruction opcodes in the program memory. This results in a program 410 that can be loaded into the apparatus and executed by its processor. The representation of a compiler as two distinct units 404 and 408 is for illustrative purposes only. In reality, a compiler has many passes for translating a source program into an executable program. Some of these passes are carried out in parallel in a single unit and some of them are carried out sequentially.

As described above in relation to Figure 1, the compiler must assure that the encoding of the instruction opcodes and their allocation to memory addresses is done in the appropriate way. This can be realized by rearranging the order of instructions in the program. Such rearranging is allowed as long as proper execution of the program is ensured. An example in this respect is the swap of the MOV-instruction at address 001 and the LDR-instruction at address 002. As a result of such a swap the instruction opcode of the LDR-instruction is allocated to an odd address, which is necessary since its least significant bit is a '1'. The swap of the two instructions has no effect on the result of the program as a whole. In many cases, an instruction may be executed independently of its direct predecessor or successor. This offers the compiler a relatively large degree of freedom for allocating instruction opcodes to an address in the program memory and for swapping instructions, if necessary. A further mechanism to assist in allocating an instruction opcode to its proper address is to introduce two codes for one opcode. The first code is intended for even addresses and the second code for odd addresses; for example, see the above MOV-instruction, for which two such codes have been defined. The advantage is that such an instruction can be placed anywhere in the program memory. Introducing an extra code for an instruction can be done only for as long as the total number of codes does not make it necessary to encode them in a longer bit-pattern. If, despite the freedom of the compiler for allocating addresses, a proper allocation cannot be realized, a NOP-instruction may be inserted. This NOP-instruction is a pseudo instruction that does not perform any real operation but is inserted merely to move the subsequent instruction to a next address. Adding this additional instruction requires an extra space in the program memory. Therefore, this operation is carried out only when no other solution is available. Figure 5 shows the most important components of the system for generating an executable program according to the invention. The system 500 is implemented according to a known architecture and can be realized on a general-purpose computer. The system has a processor 502 for carrying out instructions of a compiler program loaded into a working memory 504. The system also has an interface 506 for communication with peripheral devices. There is provided a bus 508 for the exchange of commands and data between the various components of the apparatus. The peripherals of the system include a storage medium 510 containing the executable compiler program, the source program to be translated, and various other data. Furthermore, the translated program and intermediate results are stored on the storage medium 510. The storage medium 510 can be realized as various separate devices, which are potentially of a different kind. Application of the invention is not restricted by the type of device, storage devices that can be used include optical disc, magnetic disc, tape or combinations of these devices. Furthermore, the system may be connected to a remote server by a network, via connection a 512. The peripherals of the apparatus also include a display 514 on which the system displays menus and messages for the user. Furthermore, the peripherals may include a selection device 516 and a pointing device 518 with which the user can move a cursor on the display in order to make a selection from a menu. The devices 516 and 518 can be integrated into one selecting means 520, like a computer mouse with one or more selection buttons. However, other devices like a track ball, graphic tablet, joystick or touch sensitive display are also feasible. In order to carry out the various tasks, the respective software units are loaded into the working memory 504. These units are in particular a translation unit 522 for translating the source program into a sequence of instruction opcodes and an encoding unit 524 for encoding the instruction opcodes into bit patterns. The nature of the instruction opcodes in the program memory is of no relevance to the application of the invention. The instruction opcodes may relate to so-called native instructions that are directly executable by the processor. Alternatively, the instruction opcodes may relate to instructions that are interpreted by an interpreter running on the processor. In the latter case the combination of the processor and the interpreter forms a virtual machine executing the instruction opcodes in the program memory. The invention can then again be applied by storing in the program memory bit patterns shorter than the ones that are interpreted.

The least significant bit of the address of a stored instruction has been used for coding part of the instruction in the above embodiments. Consequently, an instruction had to be allocated to an even address or to an odd address, depending on the instruction. Instead of using the least significant bit of an address, one or more of the most significant bits of an address can be used for the same purpose. The program memory is then divided into ranges and an instruction is stored in one of the ranges in dependence on the instruction. This can be employed for instructions that are categorized into distinct groups, e.g. instructions operating on integer numbers versus instructions operating on floating point numbers. The corresponding instructions of each of the groups are encoded into the same shorter bit pattern and instructions of the first group are stored at addresses where the most significant bit is '0' whereas instructions of the second group are stored at addresses where the most significant bit is T. For example, the opcode for the ADD-instruction for integer numbers is '00000001' whereas the opcode for the ADD-instruction for floating point numbers is '10000001'. The shorter bit pattern is the same for both, i.e. '0000001'. An ADD-instruction operating on integer numbers is stored in the lower part of the memory at an address with a most significant bit '0', and an ADD-instruction operating on floating point numbers is stored in the higher part of the memory at an address with a most significant bit ' 1 ' . When more than one of the most significant bits of the address are employed, ranges are also defined in the program memory for storing instructions of respective types.

Claims

CLAIMS:

1. An apparatus comprising a program memory for storing instructions at particular addresses in the program memory and also comprising a processor for executing a particular instruction stored in the program memory, characterized in that the apparatus also comprises a decoder for decoding the particular instruction on the basis of the address of the particular instruction.

2. An apparatus as claimed in Claim 1, wherein the decoder is arranged to extend the particular instruction with one or more additional bits on the basis of the address of the particular instruction.

3. An apparatus as claimed in Claim 2, wherein the particular instruction comprises an instruction opcode and wherein the decoder is arranged to extend the instruction opcode of the particular instruction with one additional bit on the basis of the address of the particular instruction in order to generate an extended instruction opcode whose least significant bit is formed by the additional bit.

4. An apparatus as claimed in Claim 3, wherein the decoder is arranged to assign the value of the least significant bit of the address of the particular instruction to the least significant bit of the extended instruction opcode.

5. A method of executing a program, instructions of which are stored at particular addresses in a program memory, the method comprising the steps of: reading a particular instruction from the program memory, and executing the particular instruction by means of a processor, characterized in that, prior to the execution of the particular instruction, the particular instruction is decoded on the basis of the address of the particular instruction.

6. A method as claimed in Claim 5, wherein decoding the particular instruction includes extending the particular instruction with one or more additional bits on the basis of the address of the particular instruction.

7. A decoder for decoding a particular instruction stored at an address in a memory characterized in that the decoder is arranged to decode the particular instruction on the basis of the address of the particular instruction.

8. A decoder as claimed in claim 7, wherein the particular instruction comprises an instruction opcode, wherein the decoder is arranged to extend the instruction opcode with an additional bit on the basis of the address of the particular instruction to generate an extended instruction opcode of which the least significant bit is formed by the additional bit, and wherein the decoder is arranged to assign the value of the least significant bit of the address of the particular instruction to the least significant bit of the extended instruction opcode.

A processor including a decoder as claimed in claim 7 or in claim 8.

10. A system for generating an executable program, the system comprising: translation means for translating a source program into a sequence of instructions, and - encoding means for encoding the instructions into respective bit patterns to be stored in a program memory, characterized in that the encoding means is arranged to encode a particular instruction into a shortened bit pattern and to allocate this shortened bit pattern to an address in the program memory on the basis of the instruction.

11. A system as claimed in Claim 10, wherein the particular instruction comprises an instruction opcode and wherein the encoding means is arranged to obtain the shortened bit pattern by removing the least significant bit from the bit pattern representing the instruction opcode of the particular instruction and to allocate the shortened bit pattern to an address whose least significant bit has the same value as the removed least significant bit.