WO2000003429A1 - Thin-layered semiconductor structure comprising a heat distribution layer - Google Patents

Thin-layered semiconductor structure comprising a heat distribution layer Download PDF

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Publication number
WO2000003429A1
WO2000003429A1 PCT/FR1999/001659 FR9901659W WO0003429A1 WO 2000003429 A1 WO2000003429 A1 WO 2000003429A1 FR 9901659 W FR9901659 W FR 9901659W WO 0003429 A1 WO0003429 A1 WO 0003429A1
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Prior art keywords
layer
substrate
semiconductor structure
semiconductor
intermediate zone
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PCT/FR1999/001659
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French (fr)
Inventor
Jean-Pierre Joly
Michel Bruel
Claude Jaussaud
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Commissariat A L'energie Atomique
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Priority to EP99929439A priority Critical patent/EP1103072A1/en
Priority to JP2000559589A priority patent/JP2002525839A/en
Publication of WO2000003429A1 publication Critical patent/WO2000003429A1/en
Priority to US10/928,057 priority patent/US7300853B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a thin film semiconductor structure and methods of making such a structure.
  • thin layer semiconductor structure means a structure having a thin semiconductor layer on the surface in which electronic devices will be manufactured (this layer is called the active layer) and a substrate playing a mechanical support role.
  • This substrate is generally electrically insulated from the surface layer.
  • the substrate is made either of a solid insulating material (a dielectric in the case of SOS), or of a conductive or semiconductor material. In the latter case, it may be the same material as that of the surface layer (case of SOI), generally isolated from the surface layer by an insulating layer.
  • the mechanical substrate usually consists of a silicon substrate with a layer of silica on the surface, but it can also consist of a solid substrate of molten silica (silicon on quartz).
  • Thin layer ser ⁇ conductive structures such as SOI structures are increasingly used to make electronic devices.
  • SOI structures are used in particular to fabricate VLSI logic and analog circuits or to fabricate power components.
  • An SOI structure (or substrate) has several advantages compared to a solid silicon substrate. One of these advantages is that the insulator underlying the silicon layer makes it possible to reduce the stray capacitances of the devices produced in the silicon layer, and this all the more so as this insulator is thick.
  • a process that has become conventional for producing an SOI substrate is the SIMOX (Separation by IMplanted OXygen) process.
  • the insulator is a buried layer of silicon oxide Si0 2 obtained by uniform implantation of oxygen in a silicon substrate.
  • Wafer Bonding This technique is now competed with by other methods of the type called "Wafer Bonding" according to English terminology, (and which will be designated subsequently by the name of molecular adhesion), for example the BSOI method ( described by J. HAISMA et al. in Jap. J. Appl. Phys., vol. 28, page L 725, 1989) or the UNIBOND process (described by M. BRUEL in Electron. Lett., vol. 31, page 1201 , 1995).
  • the SIMOX technique is still widely used. It is based on a very high dose oxygen implantation. It allows the production of buried layers of silica only for thicknesses between 100 and 400 nm.
  • the major drawback of this technique is its cost due to ion implantation at high doses, and the need to use non-standard microelectronics equipment.
  • Molecular adhesion type techniques do not have this drawback and, in principle, also make it possible to modulate the thicknesses of the layers as well as the nature of the material constituting the insulator.
  • the UNIBOND process also allows lower cost and better homogeneity of the silicon layer.
  • amorphous silica Si02 as the base material for the buried insulation layer. This material is a good insulator, is easy to manufacture and gives very good interfaces with silicon because it has few fixed charges and interface states. It also has a low dielectric constant, which is a favorable factor for the speed of the components because of the reduction in stray capacitances.
  • silica has a major drawback: its very low thermal conductivity which is of the order of 0.02 W.rn ⁇ .K "1. This results in significant transient and localized heating, which is quite troublesome for the proper functioning of the One method to reduce this heating is to reduce the thickness of the buried silica layer.
  • this reduction in thickness has the drawbacks on the one hand of increasing the parasitic capacities (therefore of reducing the speed of the components) and, on the other hand, to reduce the electrical resistance.
  • the reduction in thickness of the insulating layer is not easy to obtain in the implementation of processes of the molecular adhesion type where good quality bonding is obtained much more easily with layers whose thickness exceeds 300 n.
  • Sic type structures on silicon or AsGa on silicon with generally an intermediate insulating layer are also Sic type structures on silicon or AsGa on silicon with generally an intermediate insulating layer. These structures are often used for the production of microwave power components. As a result, the heat dissipation in the component is enormous and the thermal conductivity of the silicon and / or of the dielectrics used is insufficient to ensure a junction temperature which is not prohibitive.
  • a thin layer semiconductor structure having several layers between the semiconductor surface layer, from which the electronic components will be produced, and the support substrate so as to decouple the functions thermal conductivity and electrical insulation.
  • This decoupling makes it possible to optimize, by a choice of suitable materials, these two functions, it being understood that these materials must also allow a good interface quality (mechanical strength).
  • the material in contact with the semiconductor layer must also have an interface of good electrical quality.
  • the layer in contact with the semiconductor surface layer can be produced by means of an insulating layer offering good electrical insulation and good electrical interface quality.
  • a layer of a material having thermal conductivity is used to remedy the problem of overheating produced by electronic components.
  • Another layer can be used to ensure the quality bond with the support substrate if the layer of good thermal conductivity does not allow it. It can be of low thermal conductivity. If this layer is insulating, its role can also be to maintain a sufficient thickness of insulator of low permittivity under the surface semiconductor layer in order to keep low parasitic capacities for the electronic components and to allow an easy bonding in the case of the use of the molecular adhesion technique.
  • the subject of the invention is therefore a semiconductor structure in a thin layer comprising a semiconductor surface layer separated from a support substrate by an intermediate zone, the intermediate zone being a multilayer electrically insulating the semiconductor surface layer from the support substrate, having an electrical quality d 'interface considered to be sufficiently good with the semiconductor surface layer and comprising at least a first layer, of thermal conductivity satisfactory for ensuring that the electronic device or devices which are to be developed from the semiconductor surface layer function as correct, characterized in that the intermediate zone also comprises a second layer, insulating and of low dielectric constant, located between the first support layer and substrate.
  • the thickness of the first layer is chosen as a function of the size of the heat dissipation zones of the electronic devices.
  • a thickness of the same order of magnitude or greater than the dimension of the largest heat dissipation zone will advantageously be chosen as the thickness for the first layer.
  • this must be as thin as possible to optimize the role of the first layer.
  • the second layer may be capable of ensuring an adhesion considered to be satisfactory between the intermediate zone and the support substrate.
  • Good adhesion is understood to mean mechanical adhesion with the least possible macroscopic defects (that is to say localized lack of adhesion).
  • the intermediate zone may comprise a third layer, insulating between the first layer and the semiconductor surface layer, said third layer conferring on the intermediate zone said electrical interface quality. If the semiconductor structure is an SOI structure, the third layer is advantageously a layer of silicon oxide obtained for example by thermal oxidation.
  • the second layer may be a layer of silicon oxide.
  • the first layer may not be insulating. Its thickness is adjusted according to the heat generation zones in the semiconductor layer. It can in particular be multilayer. More precisely, for the layer of good thermal conductivity to play its role effectively in the diffusion of the heat generated in the components, its thickness must be sufficient. Conversely, the thickness of any intermediate layers of relatively low thermal conductivity between this layer and the semiconductor layer should be minimized. In practice, the respective thicknesses of these layers necessary for proper thermal operation will depend on the size of the components and their operation (size of the heat dissipation zones) and on the thermal conductivities of the different materials (semiconductor layer, dissipative layer, layers and substrate).
  • the first layer may consist of a material chosen from polycrystalline silicon, diamond, alumina, silicon nitride, aluminum nitride, boron nitride, silicon carbide.
  • the first layer may be in contact with the semiconductor surface layer and be able to impart said electrical interface quality.
  • the semiconductor structure being an SOI structure
  • the first layer can be a layer of cubic silicon carbide.
  • the second layer of the intermediate zone has a sufficient thickness of insulator of low dielectric constant so that the stray capacitances present between the semiconductor surface layer and the support substrate are sufficiently low to ensure a operation considered to be correct of the electronic device or devices which must be produced from the semiconductor surface layer.
  • the subject of the invention is also a method of manufacturing a semiconductor structure as defined above, characterized in that it comprises the following steps:
  • the production of said semiconductor surface layer may include reducing the thickness of the first substrate.
  • Bonding of the first substrate on the second substrate can be achieved by molecular adhesion.
  • the step of manufacturing the layers of the intermediate zone can comprise the deposition of at least one bonding layer to allow bonding by molecular adhesion.
  • said bonding layer is a layer of silicon oxide.
  • the first layer may be a layer of a material chosen from polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive sputtering, silicon nitride deposited by CVD, aluminum nitride deposited by CVD, boron nitride deposited by CVD and the silicon carbide deposited by CVD.
  • the reduction of the thickness of the first substrate can be obtained by the use of one or more techniques among: rectification, chemical attack, polishing, separation following a heat treatment along a cleavage plane induced by ion implantation.
  • FIG. 1 shows, in transverse view, a semiconductor structure with a heat distribution layer according to the present invention
  • FIG. 2A to 2D illustrate different stages of a first method of producing a semiconductor structure according to the present invention
  • FIG. 3A and 3B illustrate different stages of a second method of producing a semiconductor structure according to the present invention.
  • Figure 1 shows a first example of a semiconductor structure according to the invention.
  • This structure comprises a support substrate 1 for example of silicon, a surface layer 2 of silicon and a intermediate zone 3.
  • the intermediate zone 3 comprises at least one layer 4 of good thermal conductivity, an insulating layer 5 giving good electrical quality of the interface with the surface semiconductor layer 2 and an insulating layer 6, which can be of low thermal conductivity , adhering to the support substrate 1.
  • layer 6 of silica In the case of an SOI structure implementing the molecular adhesion process, it is possible in particular to produce layer 6 of silica. This layer 6 can of course be a multilayer.
  • the layer 4 of good thermal conductivity makes it possible to have a good electrical interface directly with the surface layer of silicon 2, the layer 5 can be omitted.
  • the structure according to the invention makes it possible to keep the materials and the thicknesses allowing both easy manufacture and good functioning of the electronic devices which will be produced on or in the semiconductor surface layer.
  • Layer 4 acts as a heat distributor and makes it possible to reduce the rise in temperature at the level of the heat emitting device while making it possible to keep the underlying layer or layers of low thermal conductivity and relatively thick.
  • the insulating layer 5 can also be an insulating multilayer.
  • the advantage of the invention from the thermal point of view can be shown by the following example relating to an SOI structure.
  • a localized heating of 0.2 ⁇ m in diameter is assumed, roughly corresponding to the heating created by an advanced generation transistor.
  • the resulting heating was calculated by fixing the nature (silica) and the thickness of the materials of layers 5 and ⁇ (respectively 0.1 and 0.3 ⁇ m) and we varied the nature and thickness of layer 4.
  • layer 4 an insulating material and if possible a low dielectric constant. This in fact makes it possible to reduce the capacitances and the dielectric losses.
  • FIGS. 2A to 2D A first method for producing a semiconductor structure according to the present invention will now be described in relation to FIGS. 2A to 2D.
  • FIG. 2A shows a first substrate 10, for example made of silicon or Sic, on one side of which a layer 15 of an insulating material has been produced, with the substrate 10 having an electrical interface quality considered to be sufficiently good.
  • the layer 15 is a layer of silica obtained by thermal oxidation.
  • a layer 14 having a satisfactory thermal conductivity is then deposited on the layer 15.
  • the materials capable of being used there may be mentioned polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive sputtering from an aluminum target, nitride silicon, aluminum nitride, boron nitride deposited by CVD and Sic deposited by CVD.
  • an insulating layer 16 ′ which can facilitate bonding can optionally be deposited, preferably a layer of silica deposited for example by CVD, unless layer 14 allows direct bonding with a second substrate 11.
  • the silicon substrate 10 has a layer 17 of microcavities arranged parallel to the face of the substrate on which the insulating layers 15, 14 and 16 ′ have been obtained.
  • This layer of microcavities 17 delimits in the substrate 10 a layer 12 intended to become the semiconductor surface layer of the structure.
  • the microcavities were obtained by ion implantation of hydrogen under the conditions described in document FR-A-2 681 472 in order to obtain a separation into two parts of the substrate 10 along a cleavage plane during a treatment. posterior thermal.
  • the ion implantation operation can be carried out before or after obtaining the insulating layers 15, 14 and 16 ′ or between the deposition of one of these layers and the deposition of another layer.
  • FIG. 2B shows a second substrate 11, for example made of silicon, serving as a support substrate, on one face of which a bonding layer 16 "has been produced.
  • This bonding layer is preferably a layer of silica produced by thermal oxidation. 'is only necessary if the nature of the substrate 11 does not allow direct bonding with the layer 16'.
  • FIG. 2C illustrates the step of bonding, by molecular adhesion, of the two substrates by bringing the free and prepared faces into contact with the bonding layers 16 'and 16 ".
  • An appropriate heat treatment (see document FR-A-2 681 472) then makes it possible to obtain the separation into two parts of the substrate 10 along the layer of microcavities 17.
  • the structure shown in FIG. 2D is then obtained, which is an SOI structure comprising a support substrate 11 and a silicon surface layer 12 separated by an intermediate zone 13.
  • the zone 13 comprises an electrical interface layer 15, a layer 14 of satisfactory thermal conductivity and a bilayer 16 (formed of the layers 16 'and 16 "in silica) ensuring good adhesion with the substrate 11.
  • the free face of the surface layer 12 can then be conditioned by polishing and cleaning.
  • FIG. 3A shows a first substrate 20, for example made of silicon, on one face of which a material of good thermal conductivity has been produced, for example by epitaxy, to obtain a corresponding layer 24.
  • the epitaxy material can be cubic silicon carbide produced according to known techniques.
  • an insulating layer 26 is then deposited, for example a layer of silica.
  • the silicon substrate 20 has a layer 27 of microcavities arranged parallel to the face of the substrate on which the insulating layers 24 and 26 have been deposited.
  • This layer of microcavities 27 delimits in the substrate 20 a layer 22 intended to become the layer semiconductor surface of the SOI structure.
  • the layer 27 of microcavities was produced under the conditions described in the document FR-A-2 681 472.
  • the two substrates are then bonded, by molecular adhesion, by bringing the free face of the layer 26 into contact (see FIG. 3A) with a free face of the substrate 21.
  • the result obtained is shown in FIG. 3B.
  • a suitable heat treatment step then makes it possible to obtain the separation into two parts of the substrate 20 along the layer of microcavities 27.
  • the ionic implantation of hydrogen in the silicon carbide when this material is used, makes it perfectly insulating. This provides an SOI structure of the required quality.

Abstract

The invention concerns a thin layered semiconductor structure comprising a surface semiconductor layer (2) separated from a support substrate (1) by an intermediate zone (3), said intermediate zone (3) being a multilayer electrically insulating the surface semiconductor layer from the support substrate. The intermediate zone has an interface electrical property considered to be sufficiently good with the surface semiconductor layer and comprises at least a first layer, having suitable thermal conductivity for ensuring the proper functioning of the electronic device(s) which are to be produced from the surface semiconductor layer (2), the intermediate zone further including a second layer, insulating and with low dielectric constant, located between the first layer and the support substrate.

Description

STRUCTURE SEMICONDUCTRICE EN COUCHE MINCE COMPORTANT UNE COUCHE DE REPARTITION DE CHALEUR SEMICONDUCTOR THIN-LAYER STRUCTURE COMPRISING A HEAT-DISTRIBUTING LAYER
Domaine techniqueTechnical area
La présente invention concerne une structure semiconductrice en couche mince et des procédés de réalisation d'une telle structure.The present invention relates to a thin film semiconductor structure and methods of making such a structure.
Par structure semiconductrice en couche mince, on entend une structure possédant en surface une fine couche semiconductrice dans laquelle seront fabriqués des dispositifs électroniques (cette couche est dite couche active) et un substrat jouant un rôle mécanique de support. Ce substrat est généralement isolé électriquement de la couche de surface. Le substrat est constitué soit d'un matériau massif isolant (un diélectrique dans le cas du SOS), soit d'un matériau conducteur ou semiconducteur. Dans ce dernier cas, il peut s'agir du même matériau que celui de la couche de surface (cas du SOI), isolé généralement de la couche de surface par une couche d'isolant. Dans le cas du SOI, le substrat mécanique est usuellement constitué d'un substrat de silicium avec une couche de silice en surface, mais il peut aussi être constitué d'un substrat massif de silice fondu (silicium sur quartz) . On connaît également d'autres structures se iconductrices en couche mince comme l'AsGa sur silicium, le SiC sur silicium ou le GaN sur saphir, etc. Ces structures sont réalisées soit par des techniques dites de "Wafer Bonding", soit par hétéroépitaxie . Etat de la technique antérieureThe term “thin layer semiconductor structure” means a structure having a thin semiconductor layer on the surface in which electronic devices will be manufactured (this layer is called the active layer) and a substrate playing a mechanical support role. This substrate is generally electrically insulated from the surface layer. The substrate is made either of a solid insulating material (a dielectric in the case of SOS), or of a conductive or semiconductor material. In the latter case, it may be the same material as that of the surface layer (case of SOI), generally isolated from the surface layer by an insulating layer. In the case of SOI, the mechanical substrate usually consists of a silicon substrate with a layer of silica on the surface, but it can also consist of a solid substrate of molten silica (silicon on quartz). Other thin-layer ic conductive structures are also known, such as AsGa on silicon, SiC on silicon or GaN on sapphire, etc. These structures are produced either by so-called "Wafer Bonding" techniques, or by heteroepitaxy. State of the art
Les structures serαiconductrices en couche mince comme par exemple les structures SOI sont de plus en plus utilisées pour réaliser des dispositifs électroniques. Les structures SOI sont utilisées en particulier pour fabriquer des circuits VLSI logiques et analogiques ou pour fabriquer des composants de puissance. Une structure (ou substrat) SOI présente plusieurs avantages par rapport à un substrat massif de silicium. L'un de ces avantages est que l'isolant sous- jacent à la couche de silicium permet de diminuer les capacités parasites des dispositifs élaborés dans la couche de silicium, et cela d'autant plus que cet isolant est épais.Thin layer serα conductive structures such as SOI structures are increasingly used to make electronic devices. SOI structures are used in particular to fabricate VLSI logic and analog circuits or to fabricate power components. An SOI structure (or substrate) has several advantages compared to a solid silicon substrate. One of these advantages is that the insulator underlying the silicon layer makes it possible to reduce the stray capacitances of the devices produced in the silicon layer, and this all the more so as this insulator is thick.
Un procédé devenu classique de réalisation d'un substrat SOI est le procédé SIMOX (Séparation by IMplanted OXygen) . Selon ce procédé, l'isolant est une couche enterrée d'oxyde de silicium Si02 obtenue par implantation uniforme d'oxygène dans un substrat de silicium. Cette technique est maintenant concurrencée par d'autres procédés du type appelé "Wafer Bonding" selon la terminologie anglo-saxonne, (et que l'on désignera par la suite sous l'appellation d'adhésion moléculaire) , par exemple le procédé BSOI (décrit par J. HAISMA et al. dans Jap. J. Appl. Phys . , vol. 28, page L 725, 1989) ou le procédé UNIBOND (décrit par M. BRUEL dans Electron. Lett., vol. 31, page 1201, 1995).A process that has become conventional for producing an SOI substrate is the SIMOX (Separation by IMplanted OXygen) process. According to this method, the insulator is a buried layer of silicon oxide Si0 2 obtained by uniform implantation of oxygen in a silicon substrate. This technique is now competed with by other methods of the type called "Wafer Bonding" according to English terminology, (and which will be designated subsequently by the name of molecular adhesion), for example the BSOI method ( described by J. HAISMA et al. in Jap. J. Appl. Phys., vol. 28, page L 725, 1989) or the UNIBOND process (described by M. BRUEL in Electron. Lett., vol. 31, page 1201 , 1995).
La technique SIMOX est encore largement utilisée. Elle est basée sur une implantation d'oxygène à très forte dose. Elle permet la fabrication de couches enterrées de silice uniquement pour des épaisseurs comprises entre 100 et 400 nm. L'inconvénient majeur de cette technique est son coût dû à l'implantation ionique à forte dose, et la nécessité de recourir à des équipements non standard en microélectronique. Les techniques de type à adhésion moléculaire ne présentent pas cet inconvénient et permettent en outre, dans le principe, de moduler les épaisseurs de couches ainsi que la nature du matériau constituant l'isolant. Le procédé UNIBOND permet en outre un moindre coût et une meilleurs homogénéité de la couche de silicium.The SIMOX technique is still widely used. It is based on a very high dose oxygen implantation. It allows the production of buried layers of silica only for thicknesses between 100 and 400 nm. The major drawback of this technique is its cost due to ion implantation at high doses, and the need to use non-standard microelectronics equipment. Molecular adhesion type techniques do not have this drawback and, in principle, also make it possible to modulate the thicknesses of the layers as well as the nature of the material constituting the insulator. The UNIBOND process also allows lower cost and better homogeneity of the silicon layer.
Tous les substrats SOI actuels utilisent la silice amorphe Si02 comme matériau de base de la couche d'isolant enterré. Ce matériau est un bon isolant, est facile à fabriquer et donne de très bonnes interfaces avec le silicium du fait qu'il possède peu de charges fixes et d'états d'interface. Il a de plus une faible constante diélectrique, ce qui est un facteur favorable pour la rapidité des composants à cause de la diminution des capacités parasites.All current SOI substrates use amorphous silica Si02 as the base material for the buried insulation layer. This material is a good insulator, is easy to manufacture and gives very good interfaces with silicon because it has few fixed charges and interface states. It also has a low dielectric constant, which is a favorable factor for the speed of the components because of the reduction in stray capacitances.
La silice présente toutefois un gros inconvénient : sa très faible conductibilité thermique qui est de l'ordre de 0,02 W.rn^.K"1. Ceci entraîne un échauffement transitoire et localisé important, tout à fait gênant pour le bon fonctionnement des composants. Une méthode pour réduire cet échauffement est de diminuer l'épaisseur de la couche de silice enterrée. Cependant, cette diminution d'épaisseur a pour inconvénients d'une part d'augmenter les capacités parasites (donc de diminuer la rapidité des composants) et, d'autre part, de diminuer la tenue électrique. Par ailleurs, la diminution d'épaisseur de la couche d'isolant n'est pas aisée à obtenir dans la mise en œuvre des procédés du type à adhésion moléculaire où une bonne qualité de collage est obtenue beaucoup plus facilement avec des couches dont l'épaisseur dépasse 300 n . Il a donc été envisagé de remplacer la silice par un autre matériau isolant présentant une meilleure conductibilité thermique. On peut se référer à ce sujet aux documents EP-A-0 707 338, EP-A-0 570 321, EP-A-0 317 445 et WO-A-91/11822. Les matériaux proposés (par exemple le diamant) ne présentent pas une bonne interface avec le silicium du point de vue électrique. Pour cela, une mince couche de silice est ajoutée pour réaliser l'interface avec le silicium superficiel. Ces solutions sont certes efficaces du point de vue thermique, mais elles ne sont pas facilement applicables en association avec les techniques de collage par adhésion moléculaire. Il est en effet extrêmement difficile de coller les matériaux de forte conductibilité thermique tels qu'envisagés.However, silica has a major drawback: its very low thermal conductivity which is of the order of 0.02 W.rn ^ .K "1. This results in significant transient and localized heating, which is quite troublesome for the proper functioning of the One method to reduce this heating is to reduce the thickness of the buried silica layer. However, this reduction in thickness has the drawbacks on the one hand of increasing the parasitic capacities (therefore of reducing the speed of the components) and, on the other hand, to reduce the electrical resistance. Furthermore, the reduction in thickness of the insulating layer is not easy to obtain in the implementation of processes of the molecular adhesion type where good quality bonding is obtained much more easily with layers whose thickness exceeds 300 n. It has therefore been envisaged to replace the silica with another insulating material having better thermal conductivity. We can refer to this subject in documents EP-A-0 707 338, EP-A-0 570 321, EP-A-0 317 445 and WO-A-91/11822. The proposed materials (for example diamond) do not have a good interface with silicon from the electrical point of view. For this, a thin layer of silica is added to form the interface with the surface silicon. These solutions are certainly effective from the thermal point of view, but they are not easily applicable in combination with bonding techniques by molecular adhesion. It is indeed extremely difficult to bond the materials of high thermal conductivity as envisaged.
Il existe également les structures de type Sic sur silicium ou AsGa sur silicium avec généralement une couche isolante intermédiaire. Ces structures sont souvent utilisées pour la réalisation de composants hyperfréquence de puissance. De ce fait, la dissipation thermique dans le composant est énorme et la conductibilité thermique du silicium et/ou des diélectriques utilisés est insuffisante pour assurer une température de jonction qui ne soit pas rédhibitoire .There are also Sic type structures on silicon or AsGa on silicon with generally an intermediate insulating layer. These structures are often used for the production of microwave power components. As a result, the heat dissipation in the component is enormous and the thermal conductivity of the silicon and / or of the dielectrics used is insufficient to ensure a junction temperature which is not prohibitive.
Exposé de l'inventionStatement of the invention
Pour remédier à ce problème, il est proposé, selon la présente invention, une structure semiconductrice en couche mince possédant plusieurs couches entre la couche superficielle semiconductrice, à partir de laquelle seront élaborés les composants électroniques, et le substrat support de façon à découpler les fonctions de conductibilité thermique et d'isolation électrique. Ce découplage permet d'optimiser, par un choix de matériaux adéquats ces deux fonctions, étant bien entendu que ces matériaux doivent' permettre également une bonne qualité d'interface (tenue mécanique). Le matériau en contact avec la couche de semiconducteur doit en outre présenter une interface de bonne qualité électrique. Ainsi, la couche en contact avec la couche superficielle semiconductrice peut être réalisée au moyen d'une couche isolante offrant une bonne isolation électrique et une bonne qualité électrique d'interface. Une couche d'un matériau présentant une conductibilité thermique est utilisée pour remédier au problème de 1 'échauffement produit par les composants électroniques. Une autre couche peut être utilisée pour assurer la liaison de qualité avec le substrat support si la couche de bonne conductibilité thermique ne le permet pas. Elle peut être de faible conductibilité thermique. Si cette couche est isolante, son rôle peut être également de maintenir une épaisseur suffisante d'isolant de faible permittivité sous la couche superficielle semiconductrice afin de garder de faibles capacités parasites pour les composants électroniques et de permettre un collage aisé dans le cas de l'utilisation de la technique d'adhésion moléculaire.To remedy this problem, it is proposed, according to the present invention, a thin layer semiconductor structure having several layers between the semiconductor surface layer, from which the electronic components will be produced, and the support substrate so as to decouple the functions thermal conductivity and electrical insulation. This decoupling makes it possible to optimize, by a choice of suitable materials, these two functions, it being understood that these materials must also allow a good interface quality (mechanical strength). The material in contact with the semiconductor layer must also have an interface of good electrical quality. Thus, the layer in contact with the semiconductor surface layer can be produced by means of an insulating layer offering good electrical insulation and good electrical interface quality. A layer of a material having thermal conductivity is used to remedy the problem of overheating produced by electronic components. Another layer can be used to ensure the quality bond with the support substrate if the layer of good thermal conductivity does not allow it. It can be of low thermal conductivity. If this layer is insulating, its role can also be to maintain a sufficient thickness of insulator of low permittivity under the surface semiconductor layer in order to keep low parasitic capacities for the electronic components and to allow an easy bonding in the case of the use of the molecular adhesion technique.
L'invention a donc pour objet une structure semiconductrice en couche mince comprenant une couche superficielle semiconductrice séparée d'un substrat support par une zone intermédiaire, la zone intermédiaire étant une multicouche isolant électriquement la couche superficielle semiconductrice du substrat support, présentant une qualité électrique d'interface considérée comme suffisamment bonne avec la couche superficielle semiconductrice et comprenant au moins une première couche, de conductibilité thermique satisfaisante pour assurer un fonctionnement considéré comme correct du ou des dispositifs électroniques qui doivent être élaborés à partir de la couche superficielle semiconductrice, caractérisée en ce que la zone intermédiaire comprend en outre une deuxième couche, isolante et de faible constante diélectrique, située entre la première couche et le substrat support. Avantageusement, l'épaisseur de la première couche est choisie en fonction de la dimension des zones de dissipation thermique des dispositifs électroniques. A titre d'exemple, on choisira avantageusement comme épaisseur pour la première couche, une épaisseur du même ordre de grandeur ou supérieure à la dimension de la plus grande zone de dissipation thermique. Dans le cas de l'utilisation d'une troisième couche, celle-ci doit être la plus mince possible pour optimiser le rôle de la première couche .The subject of the invention is therefore a semiconductor structure in a thin layer comprising a semiconductor surface layer separated from a support substrate by an intermediate zone, the intermediate zone being a multilayer electrically insulating the semiconductor surface layer from the support substrate, having an electrical quality d 'interface considered to be sufficiently good with the semiconductor surface layer and comprising at least a first layer, of thermal conductivity satisfactory for ensuring that the electronic device or devices which are to be developed from the semiconductor surface layer function as correct, characterized in that the intermediate zone also comprises a second layer, insulating and of low dielectric constant, located between the first support layer and substrate. Advantageously, the thickness of the first layer is chosen as a function of the size of the heat dissipation zones of the electronic devices. As an example, a thickness of the same order of magnitude or greater than the dimension of the largest heat dissipation zone will advantageously be chosen as the thickness for the first layer. In the case of the use of a third layer, this must be as thin as possible to optimize the role of the first layer.
La deuxième couche peut être apte à assurer une adhérence considérée comme satisfaisante entre la zone intermédiaire et le substrat support. On entend par bonne adhérence une adhérence mécanique avec le moins possible de défauts macroscopiques (c'est-à-dire des manques d'adhérence localisés). La zone intermédiaire peut comprendre une troisième couche, isolante entre la première couche et la couche superficielle semiconductrice, ladite troisième couche conférant à la zone intermédiaire ladite qualité électrique d'interface. Si la structure semiconductrice est une structure SOI, la troisième couche est avantageusement une couche d'oxyde de silicium obtenue par exemple par oxydation thermique.The second layer may be capable of ensuring an adhesion considered to be satisfactory between the intermediate zone and the support substrate. Good adhesion is understood to mean mechanical adhesion with the least possible macroscopic defects (that is to say localized lack of adhesion). The intermediate zone may comprise a third layer, insulating between the first layer and the semiconductor surface layer, said third layer conferring on the intermediate zone said electrical interface quality. If the semiconductor structure is an SOI structure, the third layer is advantageously a layer of silicon oxide obtained for example by thermal oxidation.
Si la structure semiconductrice est une structure SOI, la deuxième couche peut être une couche d'oxyde de silicium. La première couche peut ne pas être isolante. Son épaisseur est ajustée en fonction des zones de génération de chaleur dans la couche semiconductrice. Elle peut notamment être multicouche. De façon plus précise, pour que la couche de bonne conductibilité thermique joue efficacement son rôle dans la diffusion de la chaleur générée dans les composants, son épaisseur devra être suffisante. A l'inverse, l'épaisseur de couches intermédiaires éventuelles de relativement faible conductibilité thermique entre cette couche et la couche semiconductrice devra être minimisée. Dans la pratique, les épaisseurs respectives de ces couches nécessaires à un bon fonctionnement thermique dépendront de la taille des composants et de leur fonctionnement (taille des zones de dissipation thermique) et des conductibilités thermiques des différents matériaux (couche semiconductrice, couche dissipatrice, sous-couches et substrat) . La première couche peut être constituée d'un matériau choisi parmi le silicium polycristallin, le diamant, l'alumine, le nitrure de silicium, le nitrure d'aluminium, le nitrure de bore, le carbure de silicium.If the semiconductor structure is an SOI structure, the second layer may be a layer of silicon oxide. The first layer may not be insulating. Its thickness is adjusted according to the heat generation zones in the semiconductor layer. It can in particular be multilayer. More precisely, for the layer of good thermal conductivity to play its role effectively in the diffusion of the heat generated in the components, its thickness must be sufficient. Conversely, the thickness of any intermediate layers of relatively low thermal conductivity between this layer and the semiconductor layer should be minimized. In practice, the respective thicknesses of these layers necessary for proper thermal operation will depend on the size of the components and their operation (size of the heat dissipation zones) and on the thermal conductivities of the different materials (semiconductor layer, dissipative layer, layers and substrate). The first layer may consist of a material chosen from polycrystalline silicon, diamond, alumina, silicon nitride, aluminum nitride, boron nitride, silicon carbide.
La première couche peut être en contact avec la couche superficielle semiconductrice et être apte à conférer ladite qualité électrique d'interface. La structure semiconductrice étant une structure SOI, la première couche peut être une couche de carbure de silicium cubique. Avantageusement, la deuxième couche de la zone intermédiaire présente une épaisseur suffisante d'isolant de faible constante diélectrique pour que les capacités parasites présentes entre la couche superficielle semiconductrice et le substrat support soient suffisamment faibles pour assurer un fonctionnement considéré comme correct du ou des dispositifs électroniques qui doivent être élaborés à partir de la couche superficielle semiconductrice.The first layer may be in contact with the semiconductor surface layer and be able to impart said electrical interface quality. The semiconductor structure being an SOI structure, the first layer can be a layer of cubic silicon carbide. Advantageously, the second layer of the intermediate zone has a sufficient thickness of insulator of low dielectric constant so that the stray capacitances present between the semiconductor surface layer and the support substrate are sufficiently low to ensure a operation considered to be correct of the electronic device or devices which must be produced from the semiconductor surface layer.
L'invention a aussi pour objet un procédé de fabrication d'une structure semiconductrice telle que définie ci-dessus, caractérisé en ce qu'il comprend les étapes suivantes :The subject of the invention is also a method of manufacturing a semiconductor structure as defined above, characterized in that it comprises the following steps:
- fabrication des couches de la zone intermédiaire sur une face d'un premier substrat destiné à fournir ladite couche superficielle semiconductrice et/ou sur une face d'un deuxième substrat destiné à fournir le substrat support de la structure,manufacturing the layers of the intermediate zone on one face of a first substrate intended to provide said semiconductor surface layer and / or on one face of a second substrate intended to provide the support substrate for the structure,
- collage du premier substrat sur le deuxième substrat, lesdites faces étant mises en vis-à- vis,bonding of the first substrate to the second substrate, said faces being placed opposite,
- réalisation de ladite couche superficielle semiconductrice.- Realization of said semiconductor surface layer.
La réalisation de ladite couche superficielle semiconductrice peut comprendre la réduction de l'épaisseur du premier substrat.The production of said semiconductor surface layer may include reducing the thickness of the first substrate.
Le collage du premier substrat sur le deuxième substrat peut être réalisé par adhésion moléculaire. Dans ce cas, l'étape de fabrication des couches de la zone intermédiaire peut comprendre le dépôt d'au moins une couche de collage pour permettre le collage par adhésion moléculaire. Avantageusement, ladite couche de collage est une couche d'oxyde de silicium. La première couche peut être une couche d'un matériau choisi parmi le silicium polycristallin déposé par LPCVD, le diamant déposé par PECVD, l'alumine déposée par pulvérisation cathodique réactive, le nitrure de silicium déposé par CVD, le nitrure d'aluminium déposé par CVD, le nitrure de bore déposé par CVD et le carbure de silicium déposé par CVD.Bonding of the first substrate on the second substrate can be achieved by molecular adhesion. In this case, the step of manufacturing the layers of the intermediate zone can comprise the deposition of at least one bonding layer to allow bonding by molecular adhesion. Advantageously, said bonding layer is a layer of silicon oxide. The first layer may be a layer of a material chosen from polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive sputtering, silicon nitride deposited by CVD, aluminum nitride deposited by CVD, boron nitride deposited by CVD and the silicon carbide deposited by CVD.
La réduction de l'épaisseur du premier substrat peut être obtenue par l'utilisation d'une ou plusieurs techniques parmi : la rectification, l'attaque chimique, le polissage, la séparation suite à un traitement thermique le long d'un plan de clivage induit par implantation ionique.The reduction of the thickness of the first substrate can be obtained by the use of one or more techniques among: rectification, chemical attack, polishing, separation following a heat treatment along a cleavage plane induced by ion implantation.
Brève description des dessinsBrief description of the drawings
L'invention sera mieux comprise et d'autres avantages et particularités apparaîtront à la lecture de la description qui va suivre, donnée à titre d'exemple non limitatif, accompagnée des figures annexées parmi lesquelles :The invention will be better understood and other advantages and features will appear on reading the description which follows, given by way of nonlimiting example, accompanied by the appended figures among which:
- la figure 1 montre, en vue transversale, une structure semiconductrice à couche de répartition de chaleur selon la présente invention, - les figures 2A à 2D illustrent différentes étapes d'un premier procédé de réalisation d'une structure semiconductrice selon la présente invention,- Figure 1 shows, in transverse view, a semiconductor structure with a heat distribution layer according to the present invention, - Figures 2A to 2D illustrate different stages of a first method of producing a semiconductor structure according to the present invention,
- les figures 3A et 3B illustrent différentes étapes d'un deuxième procédé de réalisation d'une structure semiconductrice selon la présente invention.- Figures 3A and 3B illustrate different stages of a second method of producing a semiconductor structure according to the present invention.
Description détaillée de modes de réalisation de l'inventionDetailed description of embodiments of the invention
La figure 1 montre un premier exemple de structure semiconductrice selon l'invention. Cette structure comporte un substrat support 1 par exemple en silicium, une couche superficielle 2 en silicium et une zone intermédiaire 3. La zone intermédiaire 3 comporte au moins une couche 4 de bonne conductibilité thermique, une couche isolante 5 conférant une bonne qualité électrique de l'interface avec la couche semiconductrice superficielle 2 et une couche isolante 6, pouvant être de faible conductibilité thermique, adhérant au substrat support 1.Figure 1 shows a first example of a semiconductor structure according to the invention. This structure comprises a support substrate 1 for example of silicon, a surface layer 2 of silicon and a intermediate zone 3. The intermediate zone 3 comprises at least one layer 4 of good thermal conductivity, an insulating layer 5 giving good electrical quality of the interface with the surface semiconductor layer 2 and an insulating layer 6, which can be of low thermal conductivity , adhering to the support substrate 1.
Dans le cas d'une structure SOI mettant en œuvre le procédé d'adhésion moléculaire, on peut en particulier réaliser la couche 6 en silice. Cette couche 6 peut bien sûr être une multicouche.In the case of an SOI structure implementing the molecular adhesion process, it is possible in particular to produce layer 6 of silica. This layer 6 can of course be a multilayer.
Lorsque la couche 4 de bonne conductibilité thermique permet d'avoir directement une bonne interface électrique avec la couche superficielle en silicium 2, la couche 5 peut être omise.When the layer 4 of good thermal conductivity makes it possible to have a good electrical interface directly with the surface layer of silicon 2, the layer 5 can be omitted.
La structure selon l'invention permet de garder les matériaux et les épaisseurs permettant à la fois une fabrication aisée et un bon fonctionnement des dispositifs électroniques qui seront réalisés sur ou dans la couche superficielle semiconductrice.The structure according to the invention makes it possible to keep the materials and the thicknesses allowing both easy manufacture and good functioning of the electronic devices which will be produced on or in the semiconductor surface layer.
La couche 4 (ou les couches 4) agit comme répartiteur de la chaleur et permet de diminuer l'élévation de la température au niveau du dispositif émetteur de chaleur tout en permettant de garder la ou les couches sous-jacentes de faible conductibilité thermique et de relativement forte épaisseur.Layer 4 (or layers 4) acts as a heat distributor and makes it possible to reduce the rise in temperature at the level of the heat emitting device while making it possible to keep the underlying layer or layers of low thermal conductivity and relatively thick.
La couche isolante 5 peut également être une multicouche isolante.The insulating layer 5 can also be an insulating multilayer.
L'intérêt de l'invention du point de vue thermique peut être montré grâce à l'exemple suivant se rapportant à une structure SOI . On suppose un échauffement localisé de 0,2 μm de diamètre, correspondant à peu près à 1 ' échauffement créé par un transistor de génération avancée. On a calculé 1 ' échauffement résultant en fixant la nature (silice) et l'épaisseur des matériaux des couches 5 et β (respectivement 0,1 et 0,3 μm) et on a fait varier la nature et l'épaisseur de la couche 4. On a utilisé pour cela un modèle très simple, assimilant la structure à une structure hémisphérique. On constate que l'adjonction d'une couche de répartition 4 d'épaisseur modérée (de l'ordre de la dimension du dispositif électronique) fabriquée dans des matériaux divers de conductibilités thermiques variées, mais néanmoins toujours supérieures à celles de la silice, permet de s'approcher assez vite de 1 ' échauffement correspondant à la présence de la seule couche de silice 5 de 0,1 μm d' épaisseur.The advantage of the invention from the thermal point of view can be shown by the following example relating to an SOI structure. A localized heating of 0.2 μm in diameter is assumed, roughly corresponding to the heating created by an advanced generation transistor. The resulting heating was calculated by fixing the nature (silica) and the thickness of the materials of layers 5 and β (respectively 0.1 and 0.3 μm) and we varied the nature and thickness of layer 4. We used for this a very simple model, assimilating the structure to a hemispherical structure. It can be seen that the addition of a distribution layer 4 of moderate thickness (of the order of the dimension of the electronic device) made of various materials of various thermal conductivities, but nevertheless always greater than those of silica, makes it possible to approach fairly quickly the heating corresponding to the presence of the single layer of silica 5 0.1 μm thick.
Du point de vue rapidité du dispositif électronique, on a intérêt à choisir pour la couche 4 un matériau isolant et si possible de faible constante diélectrique. Ceci permet en effet de diminuer les capacités et les pertes diélectriques.From the point of view of the speed of the electronic device, it is advantageous to choose for layer 4 an insulating material and if possible a low dielectric constant. This in fact makes it possible to reduce the capacitances and the dielectric losses.
Un premier procédé de réalisation d'une structure semiconductrice selon la présente invention va maintenant être décrit en relation avec les figures 2A à 2D.A first method for producing a semiconductor structure according to the present invention will now be described in relation to FIGS. 2A to 2D.
La figure 2A montre un premier substrat 10 par exemple en silicium ou en Sic sur une face duquel on a fabriqué une couche 15 d'un matériau isolant présentant avec le substrat 10 une qualité électrique d'interface considérée comme suffisamment bonne. De préférence, la couche 15 est une couche de silice obtenue par oxydation thermique. On dépose ensuite sur la couche 15 une couche 14 possédant une conductibilité thermique satisfaisante. Parmi les matériaux susceptibles d'être utilisés, on peut citer le silicium polycristallin déposé par LPCVD, le diamant déposé par PECVD, l'alumine déposé par pulvérisation cathodique réactive à partir d'une cible d'aluminium, le nitrure de silicium, le nitrure d'aluminium, le nitrure de bore déposés par CVD et le Sic déposé par CVD. Sur la couche 14, on peut éventuellement déposer une couche 16' isolante et facilitant le collage, de préférence une couche de silice déposée par exemple par CVD, sauf si la couche 14 permet un collage direct avec un deuxième substrat 11.FIG. 2A shows a first substrate 10, for example made of silicon or Sic, on one side of which a layer 15 of an insulating material has been produced, with the substrate 10 having an electrical interface quality considered to be sufficiently good. Preferably, the layer 15 is a layer of silica obtained by thermal oxidation. A layer 14 having a satisfactory thermal conductivity is then deposited on the layer 15. Among the materials capable of being used, there may be mentioned polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by reactive sputtering from an aluminum target, nitride silicon, aluminum nitride, boron nitride deposited by CVD and Sic deposited by CVD. On layer 14, an insulating layer 16 ′ which can facilitate bonding can optionally be deposited, preferably a layer of silica deposited for example by CVD, unless layer 14 allows direct bonding with a second substrate 11.
Le substrat en silicium 10 présente une couche 17 de microcavités disposée parallèlement à la face du substrat sur laquelle ont été obtenues les couches isolantes 15, 14 et 16' . Cette couche de microcavités 17 délimite dans le substrat 10 une couche 12 destinée à devenir la couche superficielle semiconductrice de la structure. Les microcavités ont été obtenues par implantation ionique d'hydrogène dans les conditions décrites dans le document FR-A-2 681 472 afin d'obtenir une séparation en deux parties du substrat 10 le long d'un plan de clivage lors d'un traitement thermique postérieur. L'opération d'implantation ionique peut être effectuée avant ou après l'obtention des couches isolantes 15, 14 et 16' ou entre le dépôt de l'une de ces couches et le dépôt d'une autre couche.The silicon substrate 10 has a layer 17 of microcavities arranged parallel to the face of the substrate on which the insulating layers 15, 14 and 16 ′ have been obtained. This layer of microcavities 17 delimits in the substrate 10 a layer 12 intended to become the semiconductor surface layer of the structure. The microcavities were obtained by ion implantation of hydrogen under the conditions described in document FR-A-2 681 472 in order to obtain a separation into two parts of the substrate 10 along a cleavage plane during a treatment. posterior thermal. The ion implantation operation can be carried out before or after obtaining the insulating layers 15, 14 and 16 ′ or between the deposition of one of these layers and the deposition of another layer.
La figure 2B montre un deuxième substrat 11 par exemple en silicium, servant de substrat support, sur une face duquel on a fabriqué une couche de collage 16". Cette couche de collage est de préférence une couche de silice réalisée par oxydation thermique. Elle n'est nécessaire que si la nature du substrat 11 ne permet pas un collage direct avec la couche 16'.FIG. 2B shows a second substrate 11, for example made of silicon, serving as a support substrate, on one face of which a bonding layer 16 "has been produced. This bonding layer is preferably a layer of silica produced by thermal oxidation. 'is only necessary if the nature of the substrate 11 does not allow direct bonding with the layer 16'.
La figure 2C illustre l'étape de collage, par adhésion moléculaire, des deux substrats par mise en contact des faces libres et préparées des couches de collage 16' et 16". Un traitement thermique approprié (voir le document FR-A-2 681 472) permet ensuite d'obtenir la séparation en deux parties du substrat 10 le long de la couche de microcavités 17. On obtient alors la structure représentée à la figure 2D, qui est une structure SOI comprenant un substrat support 11 et une couche superficielle 12 en silicium séparés par une zone intermédiaire 13. La zone 13 comprend une couche d'interface électrique 15, une couche 14 de conductibilité thermique satisfaisante et une bicouche 16 (formée des couches 16' et 16" en silice) assurant une bonne adhérence avec le substrat 11.FIG. 2C illustrates the step of bonding, by molecular adhesion, of the two substrates by bringing the free and prepared faces into contact with the bonding layers 16 'and 16 ". An appropriate heat treatment (see document FR-A-2 681 472) then makes it possible to obtain the separation into two parts of the substrate 10 along the layer of microcavities 17. The structure shown in FIG. 2D is then obtained, which is an SOI structure comprising a support substrate 11 and a silicon surface layer 12 separated by an intermediate zone 13. The zone 13 comprises an electrical interface layer 15, a layer 14 of satisfactory thermal conductivity and a bilayer 16 (formed of the layers 16 'and 16 "in silica) ensuring good adhesion with the substrate 11.
La face libre de la couche superficielle 12 peut ensuite être conditionnée par polissage et nettoyage.The free face of the surface layer 12 can then be conditioned by polishing and cleaning.
Un deuxième procédé de réalisation d'une structure semiconductrice selon la présente invention va maintenant être décrit en relation avec les figures 3A et 3B. La figure 3A montre un premier substrat 20 par exemple en silicium sur une face duquel on a réalisé, par exemple par épitaxie un matériau de bonne conductibilité thermique pour obtenir une couche correspondante 24. Le matériau épitaxie peut être du carbure de silicium cubique élaboré selon les techniques connues. Sur la couche 24, on dépose ensuite une couche isolante 26, par exemple une couche de silice.A second method for producing a semiconductor structure according to the present invention will now be described in relation to FIGS. 3A and 3B. FIG. 3A shows a first substrate 20, for example made of silicon, on one face of which a material of good thermal conductivity has been produced, for example by epitaxy, to obtain a corresponding layer 24. The epitaxy material can be cubic silicon carbide produced according to known techniques. On the layer 24, an insulating layer 26 is then deposited, for example a layer of silica.
Comme précédemment le substrat en silicium 20 présente une couche 27 de microcavités disposée parallèlement à la face du substrat sur laquelle ont été déposées les couches isolantes 24 et 26. Cette couche de microcavités 27 délimite dans le substrat 20 une couche 22 destinée à devenir la couche superficielle semiconductrice de la structure SOI. Comme précédemment, la couche 27 de microcavités a été réalisée dans les conditions décrites dans le document FR-A-2 681 472.As previously, the silicon substrate 20 has a layer 27 of microcavities arranged parallel to the face of the substrate on which the insulating layers 24 and 26 have been deposited. This layer of microcavities 27 delimits in the substrate 20 a layer 22 intended to become the layer semiconductor surface of the SOI structure. As before, the layer 27 of microcavities was produced under the conditions described in the document FR-A-2 681 472.
Un deuxième substrat 21 par exemple en silicium, servant de substrat support, a été préparé.A second substrate 21, for example made of silicon, serving as a support substrate, was prepared.
On réalise ensuite le collage des deux substrats, par adhésion moléculaire, par mise en contact de la face libre de la couche 26 (voir la figure 3A) avec une face libre du substrat 21. Le résultat obtenu est représenté à la figure 3B.The two substrates are then bonded, by molecular adhesion, by bringing the free face of the layer 26 into contact (see FIG. 3A) with a free face of the substrate 21. The result obtained is shown in FIG. 3B.
Une étape de traitement thermique approprié permet ensuite d'obtenir la séparation en deux parties du substrat 20 le long de la couche de microcavités 27. Dans cet exemple de réalisation, il est avantageux de réaliser l'étape d'implantation ionique après l' épitaxie de la couche isolante 24. En effet, l'implantation ionique d'hydrogène dans le carbure de silicium, lorsque ce matériau est utilisé, rend celui-ci parfaitement isolant. Ceci permet d'obtenir une structure SOI de la qualité requise.A suitable heat treatment step then makes it possible to obtain the separation into two parts of the substrate 20 along the layer of microcavities 27. In this embodiment, it is advantageous to carry out the step of ion implantation after the epitaxy. of the insulating layer 24. In fact, the ionic implantation of hydrogen in the silicon carbide, when this material is used, makes it perfectly insulating. This provides an SOI structure of the required quality.
On constate aussi que, dans cet exemple de réalisation, il n'y a pas de couche particulière pour obtenir l'interface électrique avec la couche de silicium superficielle. En effet, la couche 24 de bonne conductibilité thermique étant obtenue par épitaxie, l'interface avec la couche superficielle semiconductrice est a priori de qualité électrique satisfaisante. We also note that, in this exemplary embodiment, there is no particular layer for obtaining the electrical interface with the surface silicon layer. Indeed, the layer 24 of good thermal conductivity being obtained by epitaxy, the interface with the semiconductor surface layer is a priori of satisfactory electrical quality.

Claims

REVENDICATIONS
1. Structure semiconductrice en couche mince comprenant une couche superficielle semiconductrice (2, 12, 22) séparée d'un substrat support (1, 11, 21) par une zone intermédiaire (3, 13, 33), la zone intermédiaire (3, 13, 33) étant une multicouche isolant électriquement la couche superficielle semiconductrice du substrat support, présentant une qualité électrique d'interface considérée comme suffisamment bonne avec la couche superficielle semiconductrice et comprenant au moins une première couche, de conductibilité thermique satisfaisante pour assurer un fonctionnement considéré comme correct du ou des dispositifs électroniques qui doivent être élaborés à partir de la couche superficielle semiconductrice (2, 12, 22), caractérisée en ce que la zone intermédiaire comprend en outre une deuxième couche, isolante et de faible constante diélectrique, située entre la première couche et le substrat support.1. Thin-layer semiconductor structure comprising a semiconductor surface layer (2, 12, 22) separated from a support substrate (1, 11, 21) by an intermediate zone (3, 13, 33), the intermediate zone (3, 13, 33) being a multilayer electrically insulating the semiconductor surface layer of the support substrate, having an electrical quality of interface considered as sufficiently good with the semiconductor surface layer and comprising at least a first layer, of satisfactory thermal conductivity to ensure a functioning considered as correct of the electronic device or devices which must be produced from the semiconductor surface layer (2, 12, 22), characterized in that the intermediate zone also comprises a second layer, insulating and of low dielectric constant, located between the first layer and the support substrate.
2. Structure semiconductrice selon la revendication 1, caractérisée en ce que l'épaisseur de la première couche est choisie en fonction de la dimension des zones de dissipation thermique des dispositifs électroniques.2. Semiconductor structure according to claim 1, characterized in that the thickness of the first layer is chosen according to the size of the heat dissipation zones of the electronic devices.
3. Structure semiconductrice selon la revendication 1, caractérisée en ce que la deuxième couche est apte à assurer une adhérence considérée comme satisfaisante entre la zone intermédiaire et le substrat support.3. Semiconductor structure according to claim 1, characterized in that the second layer is capable of ensuring an adhesion considered to be satisfactory between the intermediate zone and the support substrate.
4. Structure semiconductrice selon la revendication 1, caractérisée en ce que la zone intermédiaire (3, 13) comprend une troisième couche (5, 15) , isolante, entre la première couche et la couche superficielle semiconductrice (2, 12), ladite troisième couche conférant à la zone intermédiaire ladite qualité électrique d'interface.4. Semiconductor structure according to claim 1, characterized in that the intermediate zone (3, 13) comprises a third layer (5, 15), insulating, between the first layer and the semiconductor surface layer (2, 12), said third layer conferring said electrical interface quality on the intermediate zone.
5. Structure semiconductrice selon la revendication 4, caractérisée en ce que, la structure semiconductrice étant une structure SOI, la troisième couche (5, 15) est une couche d'oxyde de silicium.5. Semiconductor structure according to claim 4, characterized in that, the semiconductor structure being an SOI structure, the third layer (5, 15) is a layer of silicon oxide.
6. Structure semiconductrice selon la revendication 5, caractérisée en ce que la troisième couche (5, 15) est une couche d'oxyde de silicium obtenue par oxydation thermique.6. Semiconductor structure according to claim 5, characterized in that the third layer (5, 15) is a layer of silicon oxide obtained by thermal oxidation.
7. Structure semiconductrice selon l'une quelconque des revendications 1 à 6, la structure semiconductrice étant une structure SOI, caractérisée en ce que la deuxième couche (6, 16) est une couche d'oxyde de silicium.7. Semiconductor structure according to any one of claims 1 to 6, the semiconductor structure being an SOI structure, characterized in that the second layer (6, 16) is a layer of silicon oxide.
8. Structure semiconductrice selon l'une quelconque des revendications 1 à 7, caractérisée en ce que la première couche (4, 14) est constituée d'un matériau choisi parmi le silicium polycristallin, le diamant, l'alumine, le nitrure de silicium, le nitrure d'aluminium, le nitrure de bore et le carbure de silicium.8. Semiconductor structure according to any one of claims 1 to 7, characterized in that the first layer (4, 14) consists of a material chosen from polycrystalline silicon, diamond, alumina, silicon nitride , aluminum nitride, boron nitride and silicon carbide.
9. Structure semiconductrice selon la revendication 1, caractérisée en ce que la première couche (24) est en contact avec la couche superficielle semiconductrice (22) et est apte à conférer ladite qualité électrique d'interface.9. Semiconductor structure according to claim 1, characterized in that the first layer (24) is in contact with the semiconductor surface layer (22) and is capable of imparting said electrical interface quality.
10. Structure semiconductrice selon la revendication 9, caractérisée en ce que, la structure semiconductrice étant une structure SOI, ladite première couche (24) est une couche de carbure de silicium cubique.10. Semiconductor structure according to claim 9, characterized in that, the semiconductor structure being an SOI structure, said first layer (24) is a layer of cubic silicon carbide.
11. Structure semiconductrice selon l'une quelconque des revendications 1 à 10, caractérisée en ce que la deuxième couche de la zone intermédiaire présente une épaisseur suffisante d'isolant de faible constante diélectrique pour que les capacités parasites présentes entre la couche superficielle semiconductrice (2, 12, 22) et le substrat support (1, 11, 21) soient suffisamment faibles pour assurer un fonctionnement considéré comme correct du ou des dispositifs électroniques qui doivent être élaborés à partir de la couche superficielle semiconductrice (2, 12, 22) .11. Semiconductor structure according to any one of claims 1 to 10, characterized in that the second layer of the intermediate zone has a sufficient thickness of insulator of low dielectric constant so that the parasitic capacitances present between the semiconductor surface layer (2, 12, 22) and the support substrate (1, 11, 21) are sufficiently weak to ensure a functioning considered as correct of the electronic device or devices which must be produced from the semiconductor surface layer (2, 12, 22).
12. Procédé de fabrication d'une structure semiconductrice selon la revendication 1, caractérisé en ce qu'il comprend les étapes suivantes :12. Method for manufacturing a semiconductor structure according to claim 1, characterized in that it comprises the following steps:
- fabrication des couches de la zone intermédiaire sur une face d'un premier substrat destiné à fournir ladite couche superficielle semiconductrice et/ou sur une face d'un deuxième substrat destiné à fournir le substrat support de la structure,manufacturing the layers of the intermediate zone on one face of a first substrate intended to provide said semiconductor surface layer and / or on one face of a second substrate intended to provide the support substrate for the structure,
- collage du premier substrat sur le deuxième substrat, lesdites faces étant mises en vis-à- vis,bonding of the first substrate to the second substrate, said faces being placed opposite,
- réalisation de ladite couche superficielle semiconductrice.- Realization of said semiconductor surface layer.
13. Procédé selon la revendication 12, caractérisé en ce que la réalisation de ladite couche superficielle semiconductrice comprend la réduction de l'épaisseur du premier substrat.13. The method of claim 12, characterized in that the production of said semiconductor surface layer comprises reducing the thickness of the first substrate.
14. Procédé selon l'une des revendications 12 ou 13, caractérisé en ce que le collage du premier substrat sur le deuxième substrat est réalisé par adhésion moléculaire.14. Method according to one of claims 12 or 13, characterized in that the bonding of the first substrate on the second substrate is carried out by molecular adhesion.
15. Procédé selon la revendication 14, caractérisé en ce que l'étape de fabrication des couches de la zone intermédiaire comprend le dépôt d'au moins une couche de collage pour permettre le collage par adhésion moléculaire. 15. The method of claim 14, characterized in that the step of manufacturing the layers of the intermediate zone comprises depositing at least one bonding layer to allow bonding by molecular adhesion.
16. Procédé selon la revendication 15, caractérisé en ce que ladite couche de collage est une couche d'oxyde de silicium.16. Method according to claim 15, characterized in that said bonding layer is a layer of silicon oxide.
17. Procédé selon l'une quelconque des revendications 12 à 16, caractérisé en ce que la première couche est une couche d'un matériau choisi parmi le silicium polycristallin déposé par LPCVD, le diamant déposé par PECVD, l'alumine déposée par pulvérisation cathodique réactive, le nitrure de silicium déposé par CVD, le nitrure d'aluminium déposé par CVD, le nitrure de bore déposé par CVD et le carbure de silicium déposé par CVD.17. Method according to any one of claims 12 to 16, characterized in that the first layer is a layer of a material chosen from polycrystalline silicon deposited by LPCVD, diamond deposited by PECVD, alumina deposited by sputtering reactive, silicon nitride deposited by CVD, aluminum nitride deposited by CVD, boron nitride deposited by CVD and silicon carbide deposited by CVD.
18. Procédé selon l'une quelconque des revendications 13 à 17, caractérisé en ce que la réduction de l'épaisseur du premier substrat (10) est obtenue par l'utilisation d'une ou plusieurs techniques parmi : la rectification, l'attaque chimique, le polissage, la séparation suite à un traitement thermique le long d'un plan de clivage induit par implantation ionique. 18. Method according to any one of claims 13 to 17, characterized in that the reduction in the thickness of the first substrate (10) is obtained by the use of one or more techniques among: rectification, etching chemical, polishing, separation following a heat treatment along a cleavage plane induced by ion implantation.
PCT/FR1999/001659 1998-07-10 1999-07-08 Thin-layered semiconductor structure comprising a heat distribution layer WO2000003429A1 (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004075287A1 (en) * 2003-02-12 2004-09-02 S.O.I.Tec Silicon On Insulator Technologies Semiconductor structure on an extremely rough substrate
US7045878B2 (en) 2001-05-18 2006-05-16 Reveo, Inc. Selectively bonded thin film layer and substrate layer for processing of useful devices
US7081657B2 (en) 2001-05-18 2006-07-25 Reveo, Inc. MEMS and method of manufacturing MEMS
US7145219B2 (en) 2001-09-12 2006-12-05 Reveo, Inc. Vertical integrated circuits
US7163826B2 (en) 2001-09-12 2007-01-16 Reveo, Inc Method of fabricating multi layer devices on buried oxide layer substrates
US8114754B2 (en) 2009-11-18 2012-02-14 S.O.I.Tec Silicon On Insulator Technologies Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods
US8765508B2 (en) 2008-08-27 2014-07-01 Soitec Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2809867B1 (en) * 2000-05-30 2003-10-24 Commissariat Energie Atomique FRAGILE SUBSTRATE AND METHOD FOR MANUFACTURING SUCH SUBSTRATE
FR2816445B1 (en) * 2000-11-06 2003-07-25 Commissariat Energie Atomique METHOD FOR MANUFACTURING A STACKED STRUCTURE COMPRISING A THIN LAYER ADHERING TO A TARGET SUBSTRATE
FR2826378B1 (en) 2001-06-22 2004-10-15 Commissariat Energie Atomique UNIFORM CRYSTALLINE ORIENTATION COMPOSITE STRUCTURE AND METHOD FOR CONTROLLING THE CRYSTALLINE ORIENTATION OF SUCH A STRUCTURE
JP5032743B2 (en) * 2002-09-18 2012-09-26 ソワテク Formation of relaxed useful layers from wafers without a buffer layer
US6982210B2 (en) 2003-07-10 2006-01-03 S.O.I.Tec Silicon On Insulator Technologies S.A. Method for manufacturing a multilayer semiconductor structure that includes an irregular layer
JP4641817B2 (en) * 2005-02-09 2011-03-02 株式会社神戸製鋼所 Manufacturing method of laminated substrate for semiconductor device and semiconductor device
JP4956649B2 (en) 2010-07-06 2012-06-20 三井造船株式会社 Silicon carbide substrate, semiconductor device and SOI wafer
FR2967812B1 (en) 2010-11-19 2016-06-10 S O I Tec Silicon On Insulator Tech ELECTRONIC DEVICE FOR RADIOFREQUENCY OR POWER APPLICATIONS AND METHOD OF MANUFACTURING SUCH A DEVICE

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0553854A2 (en) * 1992-01-31 1993-08-04 Canon Kabushiki Kaisha Semiconductor wafer, and process for production thereof
EP0570321A2 (en) * 1992-05-15 1993-11-18 International Business Machines Corporation Bonded wafer structure having a buried insulator layer
WO1994015359A1 (en) * 1992-12-18 1994-07-07 Harris Corporation Silicon on diamond circuit structure and method of making same
EP0707338A2 (en) * 1994-10-13 1996-04-17 STMicroelectronics S.r.l. Wafer of semiconductor material for fabricating integrated semiconductor devices, and process for its fabrication
WO1996015557A1 (en) * 1994-11-14 1996-05-23 North Carolina State University Silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein and methods of forming same
US5773151A (en) * 1995-06-30 1998-06-30 Harris Corporation Semi-insulating wafer

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH067594B2 (en) * 1987-11-20 1994-01-26 富士通株式会社 Method for manufacturing semiconductor substrate
SE465492B (en) * 1990-01-24 1991-09-16 Asea Brown Boveri Semiconductor component containing a diamond layer arranged between a substrate and an active layer and process prior to its preparation

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0553854A2 (en) * 1992-01-31 1993-08-04 Canon Kabushiki Kaisha Semiconductor wafer, and process for production thereof
EP0570321A2 (en) * 1992-05-15 1993-11-18 International Business Machines Corporation Bonded wafer structure having a buried insulator layer
WO1994015359A1 (en) * 1992-12-18 1994-07-07 Harris Corporation Silicon on diamond circuit structure and method of making same
EP0707338A2 (en) * 1994-10-13 1996-04-17 STMicroelectronics S.r.l. Wafer of semiconductor material for fabricating integrated semiconductor devices, and process for its fabrication
WO1996015557A1 (en) * 1994-11-14 1996-05-23 North Carolina State University Silicon carbide semiconductor devices having buried silicon carbide conduction barrier layers therein and methods of forming same
US5773151A (en) * 1995-06-30 1998-06-30 Harris Corporation Semi-insulating wafer

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
DI CIOCCIO L ET AL: "Silicon carbide on insulator formation by the Smart-Cut(R) process", MATERIALS SCIENCE AND ENGINEERING B, vol. 46, no. 1-3, April 1997 (1997-04-01), pages 349-356, XP004085343 *

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7045878B2 (en) 2001-05-18 2006-05-16 Reveo, Inc. Selectively bonded thin film layer and substrate layer for processing of useful devices
US7081657B2 (en) 2001-05-18 2006-07-25 Reveo, Inc. MEMS and method of manufacturing MEMS
US7145219B2 (en) 2001-09-12 2006-12-05 Reveo, Inc. Vertical integrated circuits
US7163826B2 (en) 2001-09-12 2007-01-16 Reveo, Inc Method of fabricating multi layer devices on buried oxide layer substrates
WO2004075287A1 (en) * 2003-02-12 2004-09-02 S.O.I.Tec Silicon On Insulator Technologies Semiconductor structure on an extremely rough substrate
US8765508B2 (en) 2008-08-27 2014-07-01 Soitec Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters
US9793360B2 (en) 2008-08-27 2017-10-17 Soitec Methods of fabricating semiconductor structures or devices using layers of semiconductor material having selected or controlled lattice parameters
US8114754B2 (en) 2009-11-18 2012-02-14 S.O.I.Tec Silicon On Insulator Technologies Methods of fabricating semiconductor structures and devices using glass bonding layers, and semiconductor structures and devices formed by such methods
US8461014B2 (en) 2009-11-18 2013-06-11 Soitec Methods of fabricating semiconductor structures and devices with strained semiconductor material
US8487295B2 (en) 2009-11-18 2013-07-16 Soitec Semiconductor structures and devices including semiconductor material on a non-glassy bonding layer

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