WO1999066704A1 - Daa circuitry and method for connecting phone lines having a dc holding - Google Patents
Daa circuitry and method for connecting phone lines having a dc holding Download PDFInfo
- Publication number
- WO1999066704A1 WO1999066704A1 PCT/US1999/011377 US9911377W WO9966704A1 WO 1999066704 A1 WO1999066704 A1 WO 1999066704A1 US 9911377 W US9911377 W US 9911377W WO 9966704 A1 WO9966704 A1 WO 9966704A1
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- WIPO (PCT)
- Prior art keywords
- circuitry
- holding circuit
- circuit
- phone line
- external
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M11/00—Telephonic communication systems specially adapted for combination with other electrical systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M11/00—Telephonic communication systems specially adapted for combination with other electrical systems
- H04M11/06—Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors
Definitions
- This invention relates to the field of digital access arrangement circuitry. More particularly, this invention relates to digital access arrangement circuitry for connecting to a variety of phone line standards.
- the digital access arrangement circuitry may further include isolation barrier utilizing a capacitor coupled isolation barrier.
- DAA circuitry may be used to terminate the telephone connections at a phone line user's end to provide a communication path for signals to and from the phone lines.
- DAA circuitry includes the necessary circuitry to terminate the telephone connections at the user's end and may include, for example, an isolation barrier, DC termination circuitry, AC termination circuitry, ring detection circuitry, and processing circuitry that provides a communication path for signals to and from the phone lines.
- governmental regulations specify the telephone interface requirements and specifications for a variety of parameters including AC termination, DC termination, ringer impedance, ringer threshold, etc.
- Federal Communications Commission (FCC) Part 68 governs the interface requirements for telephones in the United States.
- FCC Federal Communications Commission
- the interface requirements world wide are not standardized, and thus, in countries other than the United States the applicable standards may include the TBR21, NET4, JATE, and various country specific PTT specifications. Because the interface requirements are not standardized from country to country, often different DAA circuitry is required for use in each country in order to comply with the appropriate standard. The requirement for different DAA circuitry, however, limits the use of one phone line interface in a variety of countries.
- a modem in a laptop computer configured for interfacing with a phone line in one country may not necessarily operate properly in another country.
- the requirement for different DAA circuitry in various countries hinders the design of a single integrated cost effective DAA solution for use world wide.
- the telephone interface requirements generally include specifications for DC termination of the telephone line.
- the DC impedance that the DAA circuitry presents to the telephone line may be required by regulations to be less than the AC impedance that the DAA circuitry presents to the telephone line (typically « 600 ⁇ ). Consequently, inductive behavior is required from the section of the DAA circuitry that sinks DC loop current, which is typically called the DC termination or DC holding circuitry. This inductive behavior of the DC holding circuitry should provide both high impedance and low distortion for voiceband signals.
- the DC termination specifications may also include limits for the maximum current and power dissipation. For example, the TBR-21 specification requires the DC holding circuit to limit DC current to less than 60 mA with a maximum power dissipation of approximately 2 watts.
- bipolar transistor e.g., P P transistor
- P P transistor bipolar transistor
- the design of a DC holding circuit for use with multiple standards may be further complicated in that the various international specifications may conflict with regards to off-hook settling times and pulse dialing templates (which may require fast settling time constants) and high speed interface designs (such as for use in modems) which require very low frequency operation (i.e. approximately as low as 10 Hz). Furthermore, it is desirable to implement such DC holding circuits in a manner that does not cause excessive distortion at low and high frequencies. It is also desirable that the DAA circuitry act as an isolation barrier since an electrical isolation barrier must exist in communication circuitry which connects directly to the standard two-wire public switched telephone network and that is powered through a standard residential wall outlet.
- an isolation barrier capable of withstanding 1000 volts rms at 60 Hz with no more than 10 milliamps current flow, must exist between circuitry directly connected to the two wire telephone network and circuitry directly connected to the residential wall outlet.
- the above-referenced problems are addressed by the present invention, which provides a reliable, inexpensive, DAA circuit that may be utilized with multiple telephone interface standards and which also provides an isolation system that is substantially immune to noise that affects the timing and/or amplitude of the signal that is transmitted across the isolating element, thus permitting an input signal to be accurately reproduced at the output of the isolation system.
- the present invention provides digital direct access arrangement (DAA) circuitry that may be used to terminate the telephone connections at the user's end to provide a communication path for signals to and from the phone lines.
- DAA digital direct access arrangement
- the invention provides a means for providing DC termination for a variety of international phone standards.
- the invention may also be utilized with means for transmitting and receiving a signal across a capacitive isolation barrier.
- a DC holding circuit in which a programmable DC current limiting mode is available.
- power may be dissipated in devices external to a DAA integrated circuit.
- much of the power may be dissipated in external passive devices, such as resistors.
- a DC holding circuit is provided that has switchable time constants. A first time constant may be utilized during a first operation phase immediately after off-hook conditions to allow for fast settling times. Then, a second operation phase is entered in which a second time constant may be utilized. During the second operation phase the DC holding circuit operates slower to create improved low frequency performance.
- a communication system comprising phone line side circuitry that may be coupled to phone lines and powered side circuitry that may be coupled to the phone line side circuitry through an isolation barrier.
- the system may further include a DC holding circuit within the phone line side circuitry, the DC holding circuit being programmable in response to data transmitted across the isolation barrier to operate the DC holding circuit in a plurality of modes.
- the DC holding circuit may be operable in at least a first mode to meet a first phone line interface standard and a second mode to meet a second phone line interface standard, the second phone line interface standard having a DC current limit requirement.
- a method of providing a communication system that may be coupled to a phone line.
- the method may include coupling an isolation barrier between powered circuitry and phone line side circuitry and forming a DC holding circuit within the phone line side circuitry, the DC holding circuit comprising a phone line side integrated circuit and external circuitry external to the integrated circuit.
- the method may further comprise providing a programmable circuit for switching the DC holding circuit between at least a first and second mode of operation, the first mode of operation for at least a first phone line interface standard and the second mode of operation for at least a second phone line interface standard, the second standard having a DC termination current limit.
- the method may further include coupling the internal circuitry and external circuitry so that if the DC holding circuit is operated in the second mode of operation more power may be dissipated in the external circuitry during the second mode of operation than during the first mode of operation.
- a DC holding circuit for reducing power dissipation requirements of an integrated circuit a communication system that may be connected to phone lines is provided.
- the DC holding circuit may include at least one switchable circuit, the switchable circuit having a first state for a non-current limiting mode of operation and a second state for a current limiting mode of operation; external circuitry external to the integrated circuit; and internal circuitry within the integrated circuit, the external circuitry and the internal circuitry being coupled together wherein the external circuitry dissipates more power in the current limiting mode than in the non-current limiting mode.
- a method of providing a DC holding circuit is provided. The method may include forming the DC holding circuit with internal circuitry internal to an integrated circuit and external circuitry external to the integrated circuit.
- the method may further include providing a programmable circuit for switching the DC holding circuit between at least a first and second mode of operation, the first mode of operation for at least a first phone line interface standard and the second mode of operation for at least a second phone line interface standard, the second standard having a DC termination current limit.
- the method may further include coupling the internal circuitry and external circuitry so that if the DC holding circuit is operated in the second mode of operation more power may be dissipated in the external circuitry during the first mode of operation than during the second mode of operation.
- a method of forming a DC holding circuit may include providing integrated circuitry and non-integrated circuitry to comprise the DC holding circuit, the DC holding circuit capable of meeting at least at least a first and second phone line interface standards, the at least two phone line interface standards having differing current limit specifications, the second standard limiting DC current to a lower amount than the first standard.
- the method may further comprise utilizing at least one switchable circuit so that the DC holding circuit may be programmed for at least one of the phone line interface standards, and coupling the integrated circuitry and the non-integrated circuitry together so that when the DC holding circuit is programmed for the second phone line interface standard, at least one circuit element of the external circuitry will receive additional DC current as compared to when the DC holding circuit is programmed for the first phone line interface standard.
- a DC holding circuit compatible with a phone line standard having current limit requirements for reducing power dissipation requirements of an integrated circuit within a communication system that may be connected to phone lines.
- the DC holding circuit may comprise external circuitry external to the integrated circuit and internal circuitry within the integrated circuit, the external circuitry and the internal circuitry being coupled together wherein the external circuitry dissipates more power in at least one mode of operation.
- the method includes forming the DC holding circuit with internal circuitry internal to an integrated circuit and external circuitry external to the integrated circuit, the DC holding circuit compatible with at least one phone line interface standard having a DC current limit requirement.
- the method may further include coupling the internal circuitry and external circuitry so that more power may be dissipated in the external circuitry than in the internal circuitry.
- a method of operating a DC holding circuit is also provided. The method includes providing integrated circuitry and non-integrated circuitry to comprise the DC holding circuit, coupling the integrated circuitry and the non-integrated circuitry, and dissipating more power in the external circuitry than in the internal circuitry if the DC holding circuit is utilized for a phone line interface standard having a DC current limit requirement.
- a communication system may included phone line side circuitry that may be coupled to phone lines, and powered side circuitry that may be coupled to the phone line side circuitry through an isolation barrier.
- the system may also include a DC holding circuit within the phone line side circuitry, the DC holding circuit being switchable to operate in a plurality of phases, the DC holding circuit operable in at least a first phase having a first time constant and at least a second phase having a second time constant.
- a method of providing a communication system may include coupling an isolation barrier between powered circuitry and phone line side circuitry, operating a DC holding circuit in first and second off-hook phases, and utilizing a first DC holding circuit time constant during the first phase.
- the method may further include utilizing a second DC holding circuit time constant during the second phase, wherein the first time constant provides fast settling of the
- a DC holding circuit for a communication system that may be connected to phone lines.
- the DC holding circuit may further comprise at least a first circuit within the DC holding circuit, the first circuit affecting the settling time of the DC holding circuit and at least one switchable circuit, the switchable circuit having a first state for a first phase of operation of the DC holding circuit and a second state for a second phase of operation of the DC holding circuit, the at least one switchable circuit coupled to the first circuit.
- the circuit may also include at least one switched element selectively connectable to the first circuit by the switchable circuit, a time constant of the DC holding circuit changing depending upon the state of the at least one switchable circuit.
- a method of providing a DC holding circuit is provided.
- the method may further include forming the DC holding circuit with internal circuitry internal to an integrated circuit and external circuitry external to the integrated circuit, providing a programmable circuit for switching the DC holding circuit between at least a first and second phase of operation, and configuring the DC holding circuit to allow for the DC holding circuit to operate faster during the first phase and slower during the second phase.
- a method of operating a DAA circuit may comprise providing a DC holding circuit, utilizing a first time constant of the DC holding circuit during a first phase of operation of the DC holding circuit, and utilizing a second time constant of the DC holding circuit during a second phase of operation of the DC holding circuit, settling times of the DC holding circuit being faster during the first phase than during the second.
- Figure 1 is a block diagram of a telephone set illustrating a typical application of the present invention.
- Figure 2 is a general block diagram of digital DAA circuitry including phone line side circuitry, an isolation barrier, and powered side circuitry according to the present invention.
- Figure 3 is a general block diagram of transmit and receive signal paths within digital
- Figure 4 is a general circuit diagram of digital DAA circuitry implemented with two integrated circuits (ICs), a capacitive isolation barrier, and external circuitry according to the present invention.
- Figure 5A-5D are DC termination characteristic curves of various DC termination modes of the present invention.
- Figure 6 is a general block diagram of a technique for implementing current limiting according to the present invention.
- Figure 7 is a circuit diagram of a DC holding circuit according to the present invention.
- Figure 8 is graph of current characteristics of a distortion limiting technique according to the present invention.
- Figure 1 illustrates a typical application for the present invention: a telephone that includes circuitry powered by a source external to the phone system.
- a basic telephone circuit 118 is powered by the "battery" voltage that is provided by the public telephone system and does not have a separate power connection.
- Many modern phones 110 include radio (cordless), speakerphone, or answering machine features that require an external source of power 112, typically obtained by plugging the phone (or a power supply transformer/rectifier) into a typical 110-volt residential wall outlet.
- isolation barrier 120 In order to protect public phone system 114 (and to comply with governmental regulations), it is necessary to isolate "powered circuitry” 116 that is externally powered from “isolated circuitry” 118 that is connected to the phone lines, to prevent dangerous or destructive voltage or current levels from entering the phone system. (Similar considerations exist in many other applications as well, including communication, medical and instrumentation applications in which this invention may be beneficially applied.)
- the required isolation is provided by isolation barrier 120.
- the signal that passes through the isolation barrier 120 is an analog voice signal in a typical telephone application, but it may also be a digital signal or a multiplexed signal with both analog and digital components in various applications.
- isolation barrier 120 may be unidirectional (in either direction), but in many applications, including telephony, bidirectional communication is required. Bidirectional communication may be provided using a pair of unidirectional isolator channels, or by forming a single isolation channel and multiplexing bidirectional signals through the channel.
- the primary requirements placed on isolation barrier 120 are that it effectively prevents harmful levels of electrical power from passing across it, while accurately passing the desired signal from the powered side 122 to the isolated side 124, or in the reverse direction if desired.
- FIG. 2 is a general block diagram of digital DAA circuitry 110 including phone line side circuitry 118, an isolation barrier 120, and powered side circuitry 116 according to the present invention.
- the isolation barrier 120 may include one or more capacitors and allow for the transmission of digital information between the isolation interface 1614 in the phone line side circuitry and the isolation interface 1610 in the powered side circuitry.
- the phone line side circuitry 118 may be connected to phone lines of a telephone network system, and the powered side circuitry 116 may be connected to external controllers, such as digital signal processors (DSP), that may be part of a communication device, such as a phone or modem.
- DSP digital signal processors
- the powered side circuitry 116 may communicate with the external controller through a digital interface 1606 and a control interface 1608.
- the digital interface 1606 may have a number of external pins providing a serial port interface to the external controller, such as a master clock input pin (MCLK), a serial port bit clock output (SCLK), a serial port data IN pin (SDI), a serial port data OUT pin (SDO), a frame sync output pin (FSYNC_bar) (it is noted that the suffix "_bar” is used to denote a signal that is typically asserted when at a low logic level), and a secondary transfer request input pin (FC).
- MCLK master clock input pin
- SCLK serial port bit clock output
- SDI serial port data IN pin
- SDO serial port data OUT pin
- FSYNC_bar frame sync output pin
- control interface 1608 may have a number of external pins providing control and status information to and from the external controller, such as a ring detect status pin (RGDT_bar), an off-hook status pin (OFHK_bar), a reset pin (RESET_bar), and multiple mode select pins (MODE).
- RGDT_bar ring detect status pin
- OFHK_bar off-hook status pin
- REET_bar reset pin
- MODE multiple mode select pins
- the digital interface 1606 and the control interface 1608 are connected to the isolation interface 1610 so that control, status, signal and other desired information may be transmitted to and received from the phone line side circuitry 118 across the isolation barrier 120.
- the phone line side circuitry 118 may communicate with the phone lines through hybrid and DC termination circuitry 1617 (the DC termination circuitry provides an internal power supply voltage), and determine ring-detect and off-hook status information through off-hook/ring-detect block 1620.
- the hybrid and DC termination circuitry 1617 and the off-hook/ring-detect block 1620 are connected to the isolation interface 1614 so that control, status, signal and other desired information may be transmitted to and received from the powered side circuitry 116 across the isolation barrier 120.
- the hybrid portion of the hybrid and DC termination circuitry 1617 has an output pin QE2 (pin QE2 is also utilized for DC termination functions as described below) and an input pin (RX) that may connect to external telephone interface circuitry such as hook-switch circuitry and a diode bridge.
- the hybrid circuitry may function to split the differential signal existing on the phone, which typically includes both transmit and receive analog information, into an internal transmit signal (TX ⁇ -,.) and receive signal (RX JNT ).
- TX ⁇ -,. transmit signal
- RX JNT receive signal
- the QE2 output pin is used to transmit analog information to the phone lines
- the RX pin is labeled to indicate that it is used to receive analog information from the phone lines.
- the hybrid and DC termination circuitry 1617 may have a number of external pins that also connect to external telephone interface circuitry such as hook-switch circuitry and a diode bridge as shown in Figures 2 and 4.
- the hybrid and DC termination circuitry 1617 may have a DC termination pin (DCT), a voltage regulator pin (VREG), two external resistor pins (REXT and REXT2), two filter pins (FILT and FILT2) and a isolated ground pin (IGND).
- the DC termination circuitry terminates the DC voltage on the phone line and provides an internal power supply for the phone line side circuitry 118.
- the DC termination pin receives a portion of the phone line DC current with the remainder flowing through pins QE2 and QB2, depending upon the termination mode and DC current level.
- the voltage regulator pin VREG
- the voltage regulator pin allows external regulator circuitry, such as a capacitor, to be connected to the DC termination circuitry 1617. External resistors and a capacitor may be connected to the two external resistor pins (REXT and REXT2) to set the real and complex AC termination impedance respectively.
- the filter pin FILT (along with the capacitor C5) sets the time constant for the DC termination circuit.
- the filter pin FILT2 sets the off hook/on hook transient responses for pulse dialing.
- the isolated ground pin IGND may be connected to the system ground for the powered side circuitry 116 through a capacitor within the isolation barrier 120 and may also be connected to the phone line through a ground connection within external diode bridge circuitry.
- the off-hook/ring-detect block 1620 may have external input pins allowing status information to be provided concerning phone line status information (RNG1, RNG2), such as ring and caller identification signals.
- RNG1 phone line status information
- RNG2 ring and caller identification signals
- the first ring detect pin (RNG1) may connect to the tip (T) lead of the phone line through a capacitor and resistor
- the second ring detect pin (RNG2) may connect to the ring (R) lead of the phone line through a capacitor and resistor.
- off-hook/ring-detect block 1620 may have external output pins (QB, QE) that control external off-hook circuitry to enter, for example, an off-hook state or a limited power mode to get caller identification information. More particularly, the output pins (QB, QE) may be connected to the base and emitter, respectively, of a bipolar transistor within external hook-switch circuitry.
- Figure 3 is a general block diagram of internal transmit (TX) and receive (RX) signal paths within digital DAA circuitry 110 according to the present invention. In the embodiment depicted, information may communicated in either direction across the isolation barrier 120. It is noted that Figure 3 does not depict all of the functional blocks within powered side circuitry 116 and phone line side circuitry 118. It is also noted that the blocks depicted may be implemented as numerous additional blocks carrying out similar functions. In the embodiment of Figure 3, communications from the phone line side circuitry
- a delta-sigma analog-to-digital converter (ADC) 1710 receives an internal analog receive signal (RX ⁇ ), which may be provided for example by hybrid circuitryl617.
- RX ⁇ an internal analog receive signal
- the output of delta-sigma ADC 1710 is oversampled digital data stream in a pulse density modulation format.
- the decoder/encoder circuitry 1708 processes and formats this digital information as desired before sending it across the isolation barrier 120 as encoded digital information. For example, decoder/encoder 1708 may multiplex control data with the digital stream before it is sent across the isolation barrier 120.
- This control data may be any desired information, such as ring detect signals, off-hook detect signals, other phone line status information or data indicative of the country in which the DAA will be utilized (so that the appropriate phone line interface standards will be satisfied).
- the decoder/encoder 1706 decodes this encoded digital information received across the isolation barrier 120.
- the digital filter 1702 processes this decoded digital stream and converts it into internal digital receive data (RX D ) that may be provided through the digital interface 1606 to an external controller.
- a delta-sigma modulator 1704 receives an internal digital transmit signal (TX D ), which may be provided for example from an external controller through digital interface 1606.
- TX D an internal digital transmit signal
- the output of delta-sigma modulator 1704 is an oversampled digital data stream in a pulse density modulation format.
- the decoder/encoder circuitry 1706 processes and formats this digital information as desired before sending it across the isolation barrier 120 as encoded digital information.
- decoder/encoder 1706 may multiplex control data with the digital stream. This control data may be any desired information, such as ring detect signals, off-hook detect signals, or other phone line status information.
- decoder/encoder 1706 may add framing information for synchronization purposes to the digital stream before it is sent across the isolation barrier 120. Still further, decoder/encoder 1706 may format the digital data stream so that a clock signal may be recovered within the phone line side circuitry 118. Within phone line side circuitry 118, the decoder/encoder 1708 may recover a clock signal and may decode the encoded digital information received across the isolation barrier 120 to obtain framing, control or status information.
- the digital-to-analog converter (DAC) 1712 converts the decoded digital stream and converts it into internal analog transmit data (TX INJ ) that may be provided as an analog signal through the hybrid circuitry 1617 and ultimately to the phone lines.
- TX INJ internal analog transmit data
- FIG 4 is a general circuit diagram of digital DAA circuitry 110 implemented with a two integrated circuits (ICs) and a capacitive isolation barrier 120 according to the present invention.
- powered side circuitry 116 may include a powered side integrated circuit (IC) 1802A
- phone line side circuitry 118 may include a phone line side IC 1802B.
- External circuitry such as hook-switch circuitry 1804 and diode bridge circuitry 1806, is also shown connected to external pins of the phone line side IC 1802B.
- external pins 1810 of the powered side IC 1802 A are connected to an external digital signal processor (DSP) and the external pins 1808 are connected to an external application specific IC (ASIC) or controller.
- DSP digital signal processor
- ASIC application specific IC
- the isolation barrier 120 may include a first capacitor (Cl) connecting an external signal (CIA) pin on the powered side IC 1802 A to an external signal (C1B) pin on the phone line side IC 1802B.
- the isolation barrier 120 may have a second capacitor (C2) connecting the isolated ground (IGND) pin on the phone line side IC 1802B to the system ground (GND) pin on the powered side IC 1802A.
- the isolated ground (IGND) pin may be connected to node 1812 within diode circuitry 1806 (and thereby be connected to the phone line) and the remaining ground connections of the external circuitry of the phone line side circuitry 118.
- Typical component values for the various external capacitors, resistors, transistors, and diodes for the circuit of Figure 4 are shown in Table 1.
- a variety of characteristics of the DAA may be programmable in order to achieve compliance with a variety of regulatory standards.
- the DC termination characteristics, AC termination characteristics, ringer impedance, or billing tone detector of the DAA circuitry 110 may be programmable in order to achieve compliance with a variety of regulatory standards.
- the DC current limiting requirements of French and TBR21 standards may be programmable obtained.
- the low voltage requirements of Japan, Italy, Norway, and other countries may also be programmable obtained.
- four DC termination modes (modes 0, 1, 2, and 3) may be programmed by setting two bits of a programmable register through use of the serial port data IN pin (SDI).
- mode 2 is the standard loop voltage mode having no current limiting and with the transmit signal limited to -1 dBm. This mode is utilized to satisfy FCC and many European country requirements.
- Figure 5C illustrates the I-V characteristics of mode 2.
- the DC voltage across the TIP and Ring lines is plotted as a function of the DC loop current from the phone line. Within the operating range of 15mA to 100mA, the DC impedance of the DC holding circuit is approximately 50 ⁇ (the slope of the I-V curve).
- the low voltage standards required for some countries (for example Norway) will be met by the low voltage mode 0 shown in Figure 5A with the transmit signal limited to -5.22 dBm.
- FIG. 5D illustrates the I-V characteristics of mode 3 which is a current limiting mode as required in France and under the TBR21 standard.
- a first segment A of the I-V curve operates at a 50 ⁇ impedance and a second segment B of the I-V curve operates at a 3200 ⁇ impedance so that the DC termination will current limit before reaching 60mA (i.e. less than 60mA at approximately 35 volts or less.
- the crossover point between the two portions A and B of the curve is indicated as point C.
- a third segment D of the I-V curve of Figure 5D operates at an 800 ⁇ impedance.
- the data for the particular country the DAA will be utilized within may be transmitted across the capacitive barrier 120 with the various other DAA control signals.
- the phone line side circuitry 118 can then be programmably configured to satisfy the different various international DC termination requirements.
- a digitally programmable system is provided in which control bits can be provided across the isolation barrier to program the phone line side circuitry 118 in a manner such that a wide variety of phone line interface standards can be satisfied.
- the programmable nature of the phone line side circuitry 118 may minimize the need for changing the external components utilized for coupling the phone line side circuitry 118 to the phone line TIP and RING lines. In this manner a single DAA system may be utilized in a cost effective software programmable manner for world wide use.
- the DC termination or DC holding circuit of the present invention provides a variety of improvements over the prior art.
- the phone line side circuitry 118 must dissipate up to approximately two watts of power.
- Typical non current limiting specifications such as FCC standards will result in only a fraction of that amount of power dissipation to occur.
- the circuit of Figure 6 provides a mechanism in which the increased power dissipation requirements of current limiting standards may be achieved by dissipating the additional power external to the integrated circuit. In this manner, a single DAA system may be utilized for both current limiting DC termination standards and non-current limiting standards without requiring excessive power dissipation within an integrated circuit.
- a phone line side integrated circuit 1802B includes DC termination or DC holding circuitry 600 which is coupled to the DCT, QE2 and QB2 pins.
- the DCT pin is coupled to a resistor RA, for example a 1600 ⁇ resistor.
- the QB2 pin is coupled to a resistor RB, for example a 1600 ⁇ resistor.
- each resistor RA and RB may be formed from a plurality of resistors such as resistors Rl, Rl 1, and R17, and R4, R19, and R20 respectively as shown in Figure 4.
- Resistors RA and RB are coupled to the hookswitch circuitry such as shown in Figure 6.
- the QE2 and QB2 pins are coupled to the emitter and base of transistor Q4 respectively.
- the DC current on from the phone line may be directed through resistors RA and RB in varying amounts through control of transistor Q4 in order to adjust the DC impedance seen by the phone lines.
- the 50 ⁇ impedance section of the I-V curve of Figure 5D (segment A) may be obtained when the transistor Q4 is fully on and the bulk of the DC current passes through transistor Q4.
- the 3200 ⁇ impedance section of the I-V curve of Figure 5D (segment B) may be obtained while the transistor Q4 is being turned off and thus actively steering current through resistors RA and RB.
- the 800 ⁇ impedance section of the I- V curve of Figure 5D may be obtained when the transistor Q4 is fully turned off and thus the DC current is split between the resistors RA and RB.
- the DC termination mode may be selectably programmed through the powered side circuitry 116 and control information transmitted across the capacitive barrier 120 to the DC holding circuitry 600. More particularly, the DC holding circuitry controls transistor Q4 depending upon the selected mode.
- additional current may be steered to the resistors RA and RB. In this manner the higher impedance needed for current limiting specifications such as the 3200 ⁇ impedance section of the I-V curve of Figure 5D may be accurately achieved. Further, the additional power dissipation is performed external to the phone line side integrated circuit 1802B by resistor RA, resistor RB, and transistor Q4.
- resistor RA and resistor RB may each dissipate up to approximately three-fourths of a Watt, transistor Q4 up to one-half Watt while the integrated circuit need only dissipate up to three-tenths of a Watt.
- This technique is particularly advantageous in that much of the power is dissipated in passive elements (resistors) rather than solely in active devices.
- more than 50% of the DC power dissipated by the DC holding circuit may be dissipated in devices external to the integrated circuit 1802B, and more particularly, more than 50% of the DC power may be dissipated in passive resistor devices.
- FIG. 7 illustrates portions of the DAA system with like reference numbers and letters as shown in Figure 4.
- Figure 7 includes circuitry both internal and external to the phone side integrated circuit 1802B. More particularly, Figure 7 includes the RX, DCT, QB2, QE2, and FILT pins and associated internal and external circuits (the hookswitch circuitry is not being shown).
- the DC holding circuit 700 includes switches SI, S2, S3, S4, S5, S6, and S7. As discussed in detail below, the switches may be utilized to select the current limiting or non- current limiting modes of operation, to switchably operate the DC holding circuit in order to achieve fast settling times and low frequency operation and to select the low voltage modes of operation.
- the DC holding circuit 700 also includes a current limiting circuit block 705, a distortion adjustment circuit block 710, and a voltage selection circuit block 715.
- the current limiting circuit block 705 operates in conjunction with proper selection of switches to implement the higher effective impedance of the DC holding circuit to achieve the desired current limiting effect at a selected current limiting crossover point.
- the external transistor Q4 is controlled so that in the current limiting mode of operation current may be steered to both resistors RB (which as described above may each be formed from multiple resistors) so that power may be dissipated external to the integrated circuit 1802B.
- the distortion adjustment circuit block 710 operates to lower the total harmonic distortion at the crossover point.
- the voltage selection circuit block 715 is utilized to select either of the low voltage modes (modes 0 and 1) or the standard voltage mode (mode 2 or 3)
- the remaining portions of the DC holding circuit 700 operate in both current limiting and non-current limiting modes as a second order (two pole) system with external capacitors C12 and C5 affecting the frequency of the poles.
- the components of the DC holding circuit may be configured in a wide variety of manners to obtain the advantages of the invention disclosed herein and the embodiment of Figure 7 is merely exemplary. Likewise a wide variety of component values may be utilized. In one embodiment, the component values may be selected as shown below in Table 2. The transistors may be sized as labeled " X" in Figure 7.
- switch S3 When the DC holding circuit 700 of Figure 7 is operating in the non-current limiting mode (modes 0, 1, or 2), switch S3 is open. During the current limiting mode of operation (mode 3) switch S3 is closed. As will be described in more detail below, switches SI, S2, and S4 operate to selectably control time constants of the DC holding circuit 700 for use with PTT specifications which may conflict with very low frequency operations. Switches S5 and S6 are utilized to select the low voltage modes of operation (modes 0 and 1). More particularly, in standard voltage level operation (modes 2 and 3) both switches S5 and S6 are closed. In low voltage mode 0, switches S5 and S6 are both opened. In low voltage mode 1, switch S5 is open and switch S6 is closed.
- the selection of the state of the switches S5 and S6 will vary the resistance seen at the negative input of op amp OA2, thus changing the DC voltage at the DCT pin, which in turn changes the voltage between the TIP and RING lines for a given amount of DC loop current.
- the DC voltage at the DCT pin is 2.8V, in mode 1 3.1V and in modes 2 and 3 4.0V.
- switch S3 is closed and in the non-current limiting modes (modes 0-3) switch S3 is opened.
- the operation of the current limiting mode is discussed below with the time constant control switches set to a operate in SI open, S2 closed and S4 open (time constant phase 1) for illustrative purposes.
- the current limiting mode may also be operated with the time constant phase 2 (S 1 closed, S2 open and S4 closed) selected.
- the DC impedance of the DC holding circuit 700 of Figure 7 is approximately 50 ⁇ when utilizing the illustrative component values of Tables 1 and 2. This impedance value is obtained as explained below.
- the op amp circuitry of OA1 and OA2 attempt to force the DCT pin to track the AC signal on the TIP and RING lines with the resistor ratios selected in the illustrative embodiment.
- the op amp circuitry also attempts to prevent the AC current component in the current through transistor Ml (and transistor M3 which is tied to the gate of transistor Ml).
- I(M1) (V lrae (DC) - V hooksw ⁇ tch (DC) - V dl0de b ⁇ dge (DC) - V DCT (DC))/RA, where V h00ksw ⁇ tch (DC) is the DC drop across the hookswitch circuitry, V dl0de b ⁇ dge (DC) is the DC drop across the diode bridge circuitry and V DCT is the DC voltage at the DCT pin.
- the switch S3 When the current limiting mode of operation is entered, the switch S3 will be closed. This will allow current to sink through resistor R108 and transistor M10. Thus, the gate voltage on transistors Ml and M3 will not necessarily be the same. More particularly, when switch S3 is closed the current limiting effect will begin to occur as a function of the value of the DC current source II since the current limiting circuit block 705 will attempt to maintain II > I(M2) + I(M4). When the loop current is low, and thus the gate voltages on transistors M2 and M4 is at a level such that II > I(M2) + I(M4), current is not sunk through transistor M10 and the current limiting block 705 does not have an effect.
- the location of the crossover point C (the point of change of DC impedance) of Figure 5D is thus dependent upon the value of II.
- II may be 430 ⁇ A to achieve a current limiting crossover point at approximately 45mA of DC loop current.
- the current limiting technique discussed above has potential to increase the harmonic distortion at the crossover (or "knee") point of the DC I-V curve of Figure 5D. More particularly, though ideally the current through transistor M3 has no AC component, in practice non-ideal circuit components, mismatches, etc. will result in some AC component of the current through M3. Thus, the total phone line current, i LINE , will include the DC loop current of the holding circuit, the AC phone signal, and AC component of the current in M3. Distortion in the AC component of the current in M3 will therefore add harmonic distortion to the phone line signal.
- the current limiting techniques discussed above will add distortion to the AC component of the M3 current when the DC loop current is located at the crossover point or close to it.
- the AC component of the transistor M3 current will have result of repeatedly turning on and off the current limiting effect. This will result in the AC component of the current in transistor M3 to also be repeatedly limited or not limited, thus distorting the AC component.
- the AC component of the current through transistor M3 may be clipped as shown by curve A of Figure 8. As shown in Figure 8, the clipping of curve A will occur when the total current through M3 exceeds the value of the current limit level, II.
- the distortion adjustment circuit block 710 of Figure 7 compensates for this clipping effect through control of transistor Ml 4 which is also coupled to the QE2 pin.
- the distortion adjustment circuit block 710 operates in the mode 3 current limiting mode through the closure of switch S7. In other modes, switch S7 is opened and the distortion adjustment circuit block 710 does not affect the DC holding circuitry.
- the distortion adjustment circuit block 710 operates such that the current through transistor M14 has a response opposite to that of the current through transistor M3 such as shown by curve B of Figure 8. Because both transistors M3 and M14 are coupled to the QE2 pin, the total AC component effect of the current through transistors M3 and M14 will sum together.
- curves A and B Figure 8 demonstrate opposite clipping effects, the summation of these currents will be relatively free of clipping and the associated distortion, at least to a first order.
- the current response of curve B is obtained through the current steering relationship of transistors M3, M12, Ml 1 and Ml 4.
- the value of 12 may be chosen such that 12 is greater than I(M3)/10 at the crossover point.
- the DC holding circuit 700 of Figure 7 is further advantageous in that it is a second order DC holding circuit. More particularly, a first and second pole in the frequency response of the circuit is provided through the use of capacitors C5 and C12 respectively.
- the first pole results from the filtering action at the RX pin resulting from capacitor C5 and the associated resistors coupled to the RX pin.
- This filtering action is relatively sufficient at high frequencies (for example 100 Hz or greater) to result in very little AC signals on the common gate line of transistors Ml and M3 (and thus low AC current components through those transistors). However, at low frequencies more AC current components will be present in transistors Ml and M3 which would result in distortion at low frequencies.
- Improved frequency response may be obtained by adding a second frequency pole to the system.
- another stage of low pass filtering could be added between the gates of transistor Ml and M3 to more heavily filter the gate signal on transistor M3.
- the additional low pass filtering may be provided through the use capacitor C12 coupled to the QE2 pin.
- the use of the filter capacitor C12 coupled to the QE2 pin also provides noise filtering of the large PMOS device M7 which is used as a large current sinking device.
- a second order DC holding circuit is provided.
- the use of a second order frequency response circuit provides a DC holding circuit which may have greater than 60dB THD at 100 Hz, 20mA, -ldBm.
- the second order DC holding circuit is shown in one implementation to have two filter capacitors (C5 and C12) placed external to the phone side integrated circuit 1802B, however, other circuit techniques may be utilized to achieve a second order DC holding circuit. It is desirable that the frequency poles by low frequency poles, such as at or below 300 Hz, and more particularly below 50 Hz.
- the first filter resulting from capacitor C5 provides a first pole at 16 Hz (a low pass filter effect on the gate of transistor Ml).
- the second filter resulting from capacitor C12 provides a second pole at 0.44 Hz.
- the DC holding circuit present a impedance at DC and at AC frequencies the DC circuitry is removed from the signal path.
- One way to achieve such performance would be to provide a DC circuit which operates very slowly such that it is cut off at frequencies above several hertz. This may be particularly important when transmitting very low frequency modem signals (down to approximately 10 hertz) which have low distortion requirements such as greater than 75dB THD for frequencies greater than 300Hz (full scale), 60dB THD for frequencies greater than 100Hz (full scale), and), and 80dB THD for frequencies greater than 100Hz (at -9dBm)
- the use of very slow DC holding circuitry would conflict with phone line interface standards in many PTT specifications. For example, some interface standards which require rapid on-hook and off-hook switching.
- the settling time for switching between on-hook and off-hook conditions may be required to be greater than 90% loop current settling in 20msec from an off hook event.
- Such time constraints may be particularly important for pulse dialing.
- the present invention may include the use of switchable time constants which affect the speed of the DC holding circuitry.
- the DC holding circuitry may be operated in a first phase (phase 1) which has a fast settling time and in a second phase (phase 2) which has slow settling time to allow low frequency operation.
- the DC holding circuit may be utilized to meet the standards for rapid on/off-hook operation (such as in pulse dialing) and then after the phone line goes off-hook the DC holding circuit may be switched to slower circuit operation to allow low frequency phone line signal operation. In this manner a DC holding circuit having a variable operating frequency is provided.
- phase of operation high speed phase 1 or low speed phase 2 is controlled by switches SI, S2, and S4.
- switch SI is closed, S2 opened and S4 closed.
- Closing switch SI and opening switch S2 results in removing the first frequency pole (caused by capacitor C5) from the DC holding circuit.
- closing switch 4 increasing the second frequency pole to 360 Hz since the time constant of the loop current settling is now set by capacitor C12 and resistor 110 in parallel with resistor R109.
- the value of the capacitor and resistors may be selected (as shown above) to provide proper settling within a few milliseconds to give fast pulse dialing settling. It is noted that during phase 1, capacitors C5 and C12 will charge to their appropriate values.
- phase 2 may be set to activate at approximately 200msec after off-hook conditions occur.
- the switching between phase 1 and phase 2 conditions may be utilized with all of the modes of operation (modes 0-3) described above.
- the first phase may be a fast mode of operation used during the transmission of signaling information such as establishment of off-hook conditions or pulse dialing.
- the second phase may be a slow mode of operation used for the transmission of phone user data (such as, for example, voice data or modem data).
- the DC holding circuit may be in the first phase until some time period after off-hook conditions are last detected (for example 200 msec). Thereafter the DC holding circuit may be switched to the second phase.
- the time constant of the circuit for establishing off-hook conditions (the first phase) may be relatively fast or short, typically less than 10 msec, more preferably less than 5 msec and in the illustrative embodiment less than 1 msec.
- the time constant of the circuit during user data transmission (the second phase) may be relatively slow or long, typically greater than 100 msec, more preferably greater than 200 msec and in the illustrative embodiment approximately 400 msec. Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU40953/99A AU4095399A (en) | 1998-06-16 | 1999-05-21 | Daa circuitry and method for connecting phone lines having dc holding |
EP99924456A EP1088440A4 (en) | 1998-06-16 | 1999-05-21 | Daa circuitry and method for connecting phone lines having a dc holding |
JP2000555418A JP4024477B2 (en) | 1998-06-16 | 1999-05-21 | DAI circuit for telephone line connection with DC holding action and method therefor |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/097,621 | 1998-06-16 | ||
US09/098,489 US6498825B1 (en) | 1997-04-22 | 1998-06-16 | Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with programmable current limiting |
US09/097,621 US6201865B1 (en) | 1997-04-22 | 1998-06-16 | Digital access arrangement circuitry and method for connecting to phone lines having a DC holding circuit with switchable time constants |
US09/098,489 | 1998-06-16 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1999066704A1 true WO1999066704A1 (en) | 1999-12-23 |
Family
ID=26793480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1999/011377 WO1999066704A1 (en) | 1998-06-16 | 1999-05-21 | Daa circuitry and method for connecting phone lines having a dc holding |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1088440A4 (en) |
JP (1) | JP4024477B2 (en) |
KR (1) | KR100423246B1 (en) |
AU (1) | AU4095399A (en) |
WO (1) | WO1999066704A1 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1089551A2 (en) * | 1999-09-30 | 2001-04-04 | Ricoh Company, Ltd. | Network system and method for automatically interfacing with communication apparatus of different standard |
KR100321901B1 (en) * | 2000-03-15 | 2002-01-26 | 김종백 | A Control Device And A Method Of An Isolator Type |
EP1524840A1 (en) * | 2003-10-18 | 2005-04-20 | Samsung Electronics Co., Ltd. | Terminal equipment suitable for use in a plurality of PSTNs |
US6968055B1 (en) | 2003-03-26 | 2005-11-22 | Silicon Laboratories Inc. | DC holding circuit |
US7145992B2 (en) | 1999-09-30 | 2006-12-05 | Ricoh Company, Ltd. | Network system and method for automatically interfacing with communication apparatus of different standard |
Citations (4)
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US5068659A (en) * | 1988-03-15 | 1991-11-26 | Kabushiki Kaisha Toshiba | Delta-sigma modulation analog to digital converter |
US5506900A (en) * | 1993-02-17 | 1996-04-09 | Silicon Systems, Inc. | Temperature compensation for trans-hybrid loss in a miniaturized data access arrangement |
US5654984A (en) * | 1993-12-03 | 1997-08-05 | Silicon Systems, Inc. | Signal modulation across capacitors |
US5790656A (en) * | 1995-09-29 | 1998-08-04 | Rockwell International Corporation | Data access arrangement with telephone interface |
Family Cites Families (1)
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US5465298A (en) * | 1994-04-14 | 1995-11-07 | Cermetek Microelectronics | Solid state isolation device using opto-isolators |
-
1999
- 1999-05-21 JP JP2000555418A patent/JP4024477B2/en not_active Expired - Fee Related
- 1999-05-21 AU AU40953/99A patent/AU4095399A/en not_active Abandoned
- 1999-05-21 WO PCT/US1999/011377 patent/WO1999066704A1/en active IP Right Grant
- 1999-05-21 KR KR10-2000-7014204A patent/KR100423246B1/en not_active IP Right Cessation
- 1999-05-21 EP EP99924456A patent/EP1088440A4/en not_active Withdrawn
Patent Citations (4)
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US5068659A (en) * | 1988-03-15 | 1991-11-26 | Kabushiki Kaisha Toshiba | Delta-sigma modulation analog to digital converter |
US5506900A (en) * | 1993-02-17 | 1996-04-09 | Silicon Systems, Inc. | Temperature compensation for trans-hybrid loss in a miniaturized data access arrangement |
US5654984A (en) * | 1993-12-03 | 1997-08-05 | Silicon Systems, Inc. | Signal modulation across capacitors |
US5790656A (en) * | 1995-09-29 | 1998-08-04 | Rockwell International Corporation | Data access arrangement with telephone interface |
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Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1089551A2 (en) * | 1999-09-30 | 2001-04-04 | Ricoh Company, Ltd. | Network system and method for automatically interfacing with communication apparatus of different standard |
EP1089551A3 (en) * | 1999-09-30 | 2003-12-10 | Ricoh Company, Ltd. | Network system and method for automatically interfacing with communication apparatus of different standard |
US7145992B2 (en) | 1999-09-30 | 2006-12-05 | Ricoh Company, Ltd. | Network system and method for automatically interfacing with communication apparatus of different standard |
KR100321901B1 (en) * | 2000-03-15 | 2002-01-26 | 김종백 | A Control Device And A Method Of An Isolator Type |
US6968055B1 (en) | 2003-03-26 | 2005-11-22 | Silicon Laboratories Inc. | DC holding circuit |
EP1524840A1 (en) * | 2003-10-18 | 2005-04-20 | Samsung Electronics Co., Ltd. | Terminal equipment suitable for use in a plurality of PSTNs |
EP2120445A1 (en) * | 2003-10-18 | 2009-11-18 | Samsung Electronics Co., Ltd. | Terminal equipment suitable for use in a plurality of PSTNs |
US7634078B2 (en) | 2003-10-18 | 2009-12-15 | Samsung Electronics Co., Ltd. | Communication terminal device adapted to physical characteristics of telecommunication network and method for adapting communication terminal device to physical characteristics of telecommunication network |
EP2209296A3 (en) * | 2003-10-18 | 2011-03-02 | Samsung Electronics Co., Ltd. | Terminal equipment suitable for a plurality of PSTNs |
US8014515B2 (en) | 2003-10-18 | 2011-09-06 | Samsung Electronics Co., Ltd. | Communication terminal device adapted to physical characteristics of telecommunication network and method for adapting communication terminal device to physical characteristics of telecommunication network |
US8014514B2 (en) | 2003-10-18 | 2011-09-06 | Samsung Electronics Co., Ltd. | Communication terminal device adapted to physical characteristics of telecommunication network and method for adapting communication terminal device to physical characteristic of telecommunication network |
Also Published As
Publication number | Publication date |
---|---|
JP2002518944A (en) | 2002-06-25 |
EP1088440A1 (en) | 2001-04-04 |
JP4024477B2 (en) | 2007-12-19 |
EP1088440A4 (en) | 2005-07-13 |
KR20010052867A (en) | 2001-06-25 |
KR100423246B1 (en) | 2004-03-18 |
AU4095399A (en) | 2000-01-05 |
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