WO1999063589A1

WO1999063589A1 - Pad grid array and a method for producing such a pad grid array

Info

Publication number: WO1999063589A1
Application number: PCT/EP1999/003801
Authority: WO
Inventors: Rolf Aschenbrenner; Joachim KLÖSER; Erik Jung; Luc Boone; Marcel Heerman; Jozef Van Puymbroeck
Original assignee: Siemens S.A.; De Steur, Hubert
Priority date: 1998-06-02
Filing date: 1999-06-01
Publication date: 1999-12-09

Abstract

According to the invention, an electrically insulating substrate (S1) is provided with a plurality of longitudinally extended, elevated waves (W1) on the underside thereof. The conductor pattern is applied on the underside of the substrate by means of laser structuring such that the terminal pads (P1) are arranged in a flat manner in the grid array, and each is situated in the crest area of a wave. The inventive pad grid array can be produced with a fine grid of, for example, 250 νm.

Description

description

Pad grid array and method for producing such a pad grid array

Integrated circuits are getting more and more connections and are being miniaturized more and more. The difficulties with solder paste application and assembly expected with this increasing miniaturization are to be remedied by new housing shapes, whereby single, Few or multi-chip modules in the Ball Grid Array Package should be emphasized (DE-Z produc- tronic 5, 1994, pages 54, 55). These modules are based on a plated-through substrate on which the chips are contacted, for example, via contact wires or by means of flip chip assembly. On the underside of the substrate is the Ball Grid Array (BGA), which is often referred to as a Solder Grid Array or a Solder Bump Array. The ball grid array comprises solder bumps arranged flat on the underside of the substrate, which allow surface mounting on the printed circuit boards or assemblies. Due to the flat arrangement of the solder bumps, large numbers of connections can be realized in a coarse grid of, for example, 1.27 mm.

With the so-called MID technology (MID = Molded Interconnection Devices), injection molded parts with integrated conductor tracks are used instead of conventional printed circuits. High-quality thermoplastics that are suitable for injection molding three-dimensional substrates are the basis of this technology. Thermoplastics of this type are distinguished from conventional substrate materials for printed circuits by better mechanical, chemical, electrical and environmental properties. With a special direction of MID technology, the so-called SIL technology (SIL = injection molded parts with integrated conductor tracks), the structuring takes place tion of a metal layer applied to the injection molded parts without the usual masking technique by means of a special laser structuring process. Several mechanical and electrical functions can be integrated into the three-dimensional injection molded parts with structured metallization. The housing support functions simultaneously take over guides and snap connections, while the metallization layer also serves as an electromagnetic shield in addition to the wiring and connection function and ensures good heat dissipation. For the production of electrically conductive cross connections between two wiring systems on opposite surfaces of the injection molded parts, corresponding through holes are already produced during injection molding. The inner walls of these via holes are then also coated with a metal layer when the injection molded parts are metallized. Further details on the production of three-dimensional injection molded parts with integrated conductor tracks can be found, for example, in DE-A-37 32 249 or EP-A-0 361 192.

A chip housing is known from WO-A-89/10005, the carrier body of which consists of a plastic and is provided on its underside with four ribs which are arranged and integrally molded on the edge. The actual wiring here consists of a flexible circuit, which is applied to the top or the bottom of the carrier body and wound around the ribs on the edge, corresponding external connections being formed in the apex region of the ribs. The flexible wiring carries one or more IC chips, which are then arranged on the top or the bottom of the carrier body, depending on the embodiment.

A single-chip module is known from WO-A-89/00346, in which the injection-molded, three-dimensional sub- strat bumps formed from an electrically insulating polymer on the underside of the substrate during injection molding, which can optionally also be arranged flat. An IC chip is arranged on the upper side of this substrate, the connections of which are connected via fine bond wires to conductor tracks formed on the upper side of the substrate. These conductor tracks are in turn connected via plated-through holes to associated external connections formed on the bumps.

A so-called polymer stud grid array (PSGA) is known from WO-A-96/096 46, which combines the advantages of a ball grid array (BGA) with the advantages of MID technology. The designation of the new design as the Polymer Stud Grid Array (PSGA) was based on the Ball Grid Array (BGA), the term "polymer stud" referring to polymer bumps molded during injection molding of the substrate. The new one for single, Few - or multi-chip modules suitable design includes - an injection molded, three-dimensional substrate made of an electrically insulating polymer, polymer bumps arranged flat on the underside of the substrate and molded during injection molding, on the polymer bumps formed by a solderable end surface, at least on the outer connections Conductors formed on the underside of the substrate, which connect the external connections to internal connections, and at least one chip arranged on the substrate, the connections of which are electrically conductively connected to the internal connections.

In addition to the simple and inexpensive production of the polymer bumps when the substrate is injection molded, the production of the external connections on the polymer bumps can also be carried out with minimal effort together with the production which is customary for MID technology or SIL technology the conductors are made. Thanks to the laser fine structuring preferred for SIL technology, the external connections on the polymer bumps with high numbers of connections can be realized in a fine grid. At the current state of injection molding technology, however, a grid of 0.8 mm and a diameter of the polymer bumps of 0.3 mm must be regarded as the lower limit, since with further miniaturization the injection mold in the area of the polymer bumps can no longer be safely filled with plastic.

The invention specified in claims 1 and 11 is based on the problem of creating a new housing shape which on the one hand has the advantages of the polymer stud grid array (PSGA) and on the other hand further miniaturization with a grid of connection pads of less than 0, 8 mm allows.

The invention is based on the knowledge that a substrate with elongated waves compared to

Polymer Stud Grid Array (PSGA) substrate can be realized in a much finer geometry. When injection molding a substrate, the areas of the injection mold corresponding to the shafts can be filled with plastic much more easily than the areas of an injection mold corresponding to the polymer bumps. It should also be emphasized that the injection mold suitable for producing a corrugated substrate can be produced much more simply and cost-effectively than the injection mold required for producing a substrate of a polymer stud grid array. The formation of the conductor pattern with the connection pads on the corrugated underside of the substrate can easily be carried out by laser structuring in the required fineness. If the apex areas of the waves are seen in the longitudinal direction of the waves with the connection pads of the conductor pattern, then pad grid arrays can be realized with a fine grid of, for example, 250 μm.

Advantageous embodiments of the pad grid array according to the invention are specified in claims 2 to 10.

Advantageous refinements of the method according to the invention for producing a pad grid array are specified in claims 11 to 13.

Claim 2 relates to the remodeling of the pad grid array to a solder grid array. Since the required distance between the new housing shape and a printed circuit board is already ensured by the waves, the solder bumps have the sole task of electrically connecting the connection pads to the assigned connections of the printed circuit board. According to claim 3, tin-lead alloys are particularly suitable for such solder connections.

The embodiment according to claim 4 facilitates the formation of the solder bumps by remelting an electrolytically applied solder layer, since the conductor areas, which are reduced in width, prevent the liquid solder from flowing off via the conductor tracks. The reduced-width conductor areas can be formed according to claims 5 and 6 in a simple manner by constricting the conductor tracks or through holes made in the central area of the conductor tracks. The geometry of the connection pads and the conductor regions reduced in width enables an optimal formation of the solder bumps by remelting the electrolytically applied solder layer. Claim 8 provides preferred grid dimensions of the connection pads which are matched to a substrate provided with waves.

The development according to claim 9 enables an additional supply of solder in the formation of solder bumps by remelting electrolytically applied solder layers. This results in optimal conditions if the geometry of the corresponding solder feed structures specified in claim 10 is observed.

The embodiment of the method according to the invention for producing a pad grid array according to claim 12 enables a particularly simple formation of solder bumps on the connection pads by remelting electrolytically applied solder layers. This remelting can be carried out quickly and selectively with the aid of a laser beam.

Embodiments of the invention are shown in the drawing and are described in more detail below.

Show it

1 shows a perspective illustration of an injection-molded substrate provided with waves, FIG. 2 to FIG. 5 shows different process stages in the production of a pad grid array provided with solder bumps on the substrate according to FIG. 1,

FIG. 6 shows a first possibility for realizing the connection pads and their connection to the further conductor tracks,

Figure 7 shows a second possibility for the implementation of the connection pads and their connection with the further conductor lines and FIG. 8 shows a comparison of the waveforms of a pad grid array suitable for flip-chip mounting and a pad grid array suitable for surface mounting.

FIG. 1 shows a perspective illustration of an electrically insulating substrate S1, which is provided on its underside, which faces upwards in the drawing, with a multiplicity of raised waves W1 running parallel to one another. The waves Wl are formed by integrally molded ribs of the substrate S1 produced by injection molding. High-temperature resistant thermoplastics, such as polyetherimide, polyether sulfone or liquid crystalline polymers, are suitable as substrate materials.

A pad grid array is to be formed on the underside of the substrate shown in FIG. 1, the connection pads of which should lie in the apex region of the waves W1 at the locations marked with stars. The grid of the connection pads indicated by the stars can be realized, for example, in dimensions between 250 μm and 500 μm.

When producing a pad grid array, the substrate S1 shown in cross section in FIG. 2 is first metallized over the entire surface by chemical copper deposition, whereupon the desired conductor pattern including the connection pads is produced by laser structuring on the underside of the substrate S1. For example, an Nd: YAG laser with a wavelength of 1.06 μm is used for this laser structuring. The chemically deposited copper layer is then strengthened by the electrolytic deposition of copper to complete the conductor pattern. The electrolytic metal deposition on the conductor pattern is achieved, for example, by cathodic contacting in the Drawing, not shown, enables the collecting line, which connects all conductive areas of the conductor pattern to one another and is later separated, for example with the aid of a laser beam. The conductor pattern shown in FIG. 3 comprises the connection pads P1 located in the apex regions of the waves W1 and the conductor lines LZ leading away from them, as well as further structures which are evident, for example, from FIGS. 7 and 8, which will be explained later.

According to FIG. 4, a solder layer LO is then applied to the conductor pattern by electrolytic deposition. In the exemplary embodiment described, the solder layer LO is a tin-lead alloy which is deposited in a thickness between 15 μm and 50 μm.

Subsequently, the electrodeposited solder is remelted by heating to a temperature above the melting point, the solder bumps LH1 shown in FIG. 5 forming automatically due to the surface tension of the liquid solder on the connection pads P1. In the exemplary embodiment described, the remelting is carried out with the aid of a laser beam indicated by an arrow LST in FIG. 5 and is selectively limited to the connection pads P1 and their closer surroundings, which are yet to be explained with reference to FIGS. 7 and 8. This laser remelting, which in comparison to known remelting processes only requires a minimal temperature load on the substrate S1, is again carried out, for example, with the aid of an Nd.YAG laser with a wavelength of 1.06 μm.

FIG. 6 shows a first possibility for the formation of the connection pads P1 and their immediate surroundings. The geometry is shown as a development of the conductor pattern. The connection between the connection Pads Pl and the further conductor tracks LZ are made via constricted conductor areas LB1, which have a width between 10 μm and 40 μm and a length between 100 μm and 500 μm with dimensions of the connection pads Pl between I00xl00μm ^{2 and} 250x250μm ² . These constricted conductor areas LB1 prevent the liquid solder from flowing off via the conductor tracks LZ when the electrolytically applied solder layer LO (see FIG. 6) melts. In addition, the solder layer LO on the conductor areas LB1 creates an additional solder volume for the

Formation of the solder bump LH1 (see FIG. 5) is provided. A further increase in the volume of the solder bumps LH1 (cf. FIG. 5) can be brought about in a comparable manner by means of the solder feed structures LS shown in dash-dot lines in FIG. 7, which lead away from the individual connection pads P1. Accordingly, these solder feed structures LS, like the conductor areas LB1, have a width between 10 μm and 40 μm and a length between 100 μm and 500 μm. In addition, one of the solder supply structures LS leading away from the individual connection pads Pl can be connected to the collecting line mentioned earlier, which is cathodically contacted to the conductor pattern during electrolytic metal deposition and is later separated from the rest of the conductor pattern. If the solder bumps LH1 are formed by remelting the solder layer LO with the aid of a laser beam LST (cf. FIGS. 4 and 5), the laser beam LST, which is out of focus, is in each case selectively via the connection pad P1, the conductor region LB1 and possibly via the solder feed structures LS rastered. Since scanning can be carried out in less than 0.1 seconds, remelting takes place practically simultaneously.

FIG. 7 shows a second possibility for the formation of the connection pads designated here with P10 and their immediate surroundings. Here, in the connection area between connection pad P10 and a further line hole LZ is inserted in the middle of the This results in width-reduced conductor areas LB2 on both sides of the hole L. Additional solder supply structures LS are again indicated in FIG. 8 by dash-dotted lines.

The above-described pad grid arrays or the solder grid arrays created after the application of solder bumps LH1 or LH2 (see FIGS. 5 or 6) can be used both for flip-chip mounting and for surface mounting. However, the waves of the substrate have to be shaped to different heights. FIG. 8 shows a comparison between waves W3 suitable for flip-chip mounting and the much higher waves W4 suitable for surface mounting. This is a theoretical comparison, since with a pad grid array all connection pads must lie in one plane and all waves of a substrate must always be the same height.

It should also be pointed out that the waves formed on the underside of a substrate can also have shapes other than those shown in the drawing and can, for example, be concentric with one another. In addition, the waves do not have to have a constant height when viewed in the longitudinal direction. Seen in the longitudinal direction, for example, the waves could each have indentations or notches between two connection pads. This measure further increases the elasticity of the connection pads on the shafts, i.e. Mechanical stresses caused by temperature fluctuations or the like can be avoided even better.

Claims

claims

1. Pad grid array, with an electrically insulating substrate (Sl; S2), - a plurality of elongated, raised waves (Wl; W3; W4) on the underside of the substrate (Sl; S2), and one on the underside of the substrate (Sl) applied conductor pattern, the connection pads (Pl; P2; P10) of the conductor pattern being arranged flat in the grid array and each lying in the apex region of a wave (Wl; W3; W4), and wherein - the waves (Wl) integrally formed ribs of the substrate (Sl) are formed.

2. Pad grid array according to Claim 1, characterized in that solder bumps (LHL) are applied to the connection pads (Pl; P10).

3. Pad grid array according to claim 2, characterized in that the solder bumps (LHl) consist of a tin-lead alloy.

4. Pad grid array according to one of the preceding claims, characterized g e k e n n z e i c h n e t that the connection pads (Pl; P10) are each connected via a width-reduced conductor area (LBl; LB2) with the further conductor runs (LZ) of the conductor pattern.

5. Pad grid array according to claim 4, characterized in that the reduced conductor areas (LBl) are formed by a constriction of the conductor lines (LZ).

6. Pad grid array according to claim 4, characterized in that the width-reduced conductor areas (LBZ) are formed by holes (L) made in the central area of the conductor tracks (LZ).

7. Pad grid array according to one of claims 4 to 6, characterized in that the connection pads (Pl; P2; P10) have dimensions in their area between 100xl00zw ² and 250X250-? M ² and that the conductor areas are reduced in width (LBl) have a width between 10 and 40 μm and a length between 100 and 500 μm.

8. Pad grid array according to one of the preceding claims, characterized in that the connection pads (Pl; P2, P10) are arranged in a grid dimension between 250 μm and 500 μm in the grid array.

9. Pad grid array according to one of claims 4 to 8, characterized in that each of the individual connection pads (Pl; P2; P10) each has at least one solder feed structure (width-wise compared to the width of the conductor tracks (LZ)) ( LS) leads away.

10. Pad grid array according to one of the preceding claims, characterized in that the solder feed structures (LS) have a width between 10 and 40 μm and a length between 100 μm and 500 μm.

11. A method for producing a pad grid array comprising the following steps:

Production of an electrically insulating substrate (S1; S2), the underside of which has a plurality of elongated, raised integrally formed waves (W1; W3; W4), Applying a metallization to the substrate (S1; S2),

Laser structuring of the metallization on the underside of the substrate (S1) to form a conductor pattern, the connection pads (Pl; PIO) of which are arranged in the grid array and each lie in the apex region of a wave (* W1; W3; W4).

12. The method according to claim 11, characterized in that a solder (LO) is electrolytically applied to the conductor pattern and that the solder (LO) at least in the region of the connection pads (Pl; PIO) to form solder bumps (LHl; LH2) are remelted.

13. The method according to claim 12, characterized in that the solder (LO) is remelted with the aid of a laser beam (LST).