WO1999060618A1

WO1999060618A1 - Semiconductor device and method of manufacture thereof

Info

Publication number: WO1999060618A1
Application number: PCT/JP1999/002564
Authority: WO
Inventors: Kouichi Ikeda; Takeshi Ikeda
Original assignee: T.I.F. Co., Ltd.
Priority date: 1998-05-19
Filing date: 1999-05-18
Publication date: 1999-11-25
Also published as: JPH11330256A; TW457425B

Abstract

A method of manufacturing a semiconductor device of high packing density, which includes a simplified process but is capable of decreasing the fraction defective. A plurality of identical memory chips (1) are formed on a semiconductor wafer (2), and a go/no-go test is conducted on all the memory chips (1). The semiconductor wafer (2) is cut into pieces that each consists of one, or two, or four good memory chips (1) and they are mounted on a substrate (4) to form a memory module (10).

Description

Description Semiconductor device and method of manufacturing the same

Technical field

The present invention relates to a semiconductor device that can be mounted on a memory substrate, a motherboard, or the like, and a method for manufacturing the same. Background art

A semiconductor chip such as a memory chip cut from a semiconductor wafer is generally mounted on a printed circuit board or the like in a packaged state. However, since the outer dimensions of the knockout are considerably larger than the size of various semiconductor chips themselves, there are certain restrictions on the number of packages that can be mounted on a printed circuit board or the like.

On the other hand, recently, a multi-chip module in which a plurality of semiconductor chips are mounted on a substrate

—M (M CM) is spreading. By using this multi-chip module, it is possible to (1) reduce the mounting area and thus the weight, (2) achieve high performance and high speed through high-density wiring and chip mounting, and (3) ensure high reliability. become.

By the way, in the above-described multi-chip module capable of high-density mounting, since a plurality of semiconductor chips are mounted on one substrate, the failure rate of each semiconductor chip is accumulated, and the failure rate of the module as a whole increases. For example, when four memory chips are mounted on one module substrate, even if one memory chip is defective, the entire module will be defective. Therefore, it was necessary to carry out repair work to replace the defective memory chip or to dispose of the entire module as a defective product, resulting in a low yield and a lot of waste. Also, when a plurality of semiconductor chips are mounted on one substrate, each semiconductor chip is mounted on the substrate one by one, which complicates the manufacturing process.

Disclosure of the invention

The present invention has been created in view of the above points, An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can reduce the defect rate in manufacturing a semiconductor device that can be mounted and can simplify the process.

In the present invention, after forming a plurality of identical semiconductor chips (preferably, memory chips) on a semiconductor wafer or after performing wiring, resin sealing, and terminal formation on these semiconductor chips, A semiconductor device is formed by performing a pass / fail inspection and cutting a semiconductor chip into one or more units according to the result. Since semiconductor chips are separated according to the results of the pass / fail inspection, when a semiconductor device composed of a plurality of semiconductor chips and capable of high-density mounting is manufactured, some of the semiconductor chips in the semiconductor devices are not acceptable. Since the semiconductor device is a non-defective product, the entire semiconductor device does not become defective, and the defect rate in manufacturing the semiconductor device can be reduced. Further, since a semiconductor device including a plurality of semiconductor chips can be used in a subsequent process, the subsequent process is simplified as compared with a case where a plurality of semiconductor devices including a single semiconductor chip are combined. can do.

In particular, when the mounting process consisting of wiring, resin sealing, and terminal formation is performed on each semiconductor chip formed on the semiconductor wafer, and this mounting process is performed after each semiconductor chip is cut individually This allows further simplification of the process.

Also, the separation of semiconductor chips, especially memory chips, according to the results of pass / fail inspection

If 4 are possible, 4 are bundled together, if 4 is not possible and 2 is possible, 2 is bundled together, and if 2 is not possible, 1 each It is preferable to do this. In this way, by giving priority to multi-cavity production, a semiconductor device in a larger unit (four-cavity production) can be efficiently manufactured without waste. BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a diagram showing a manufacturing process of the memory module of the first embodiment,

FIG. 2 is a diagram schematically showing a memory chip formed on a semiconductor wafer,

FIG. 3 is a diagram showing an example of a method for separating memory chips formed on a semiconductor wafer,

FIG. 4 is a diagram showing a manufacturing process of the memory module of the second embodiment, Figure 5 is an enlarged cross-sectional view of a memory chip mounted with CSP.

FIG. 6 is a diagram showing a connection state between the mutually connected memory chips. BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, the memory module of the first embodiment to which the present invention is applied will be specifically described with reference to the drawings. FIG. 1 is a diagram showing a manufacturing process of the memory module of the present embodiment.

First, as shown in FIGS. 1 (a) and 1 (b), a semiconductor wafer 2 which is, for example, a silicon single crystal flake is introduced, and the same memory chip 1 is formed on the semiconductor wafer 2 (first step). ). Each area surrounded by a dotted line in FIG. 1B shows one unit of the memory chip 1 (minimum unit of division), and a plurality of memory chips 1 are formed on the semiconductor wafer 2.

FIG. 2 is a diagram schematically showing a memory chip 1 formed on a semiconductor wafer 2. As shown in FIG. 2, the memory chip 1 includes a semiconductor wafer 2 having a predetermined size and a plurality of chip pads 3 formed on the surface of the semiconductor wafer 2. The chip pad 3 is a connection terminal for making an electrical connection with a substrate on which the memory chip 1 is mounted.

With the plurality of memory chips 1 formed on the semiconductor wafer 2 in this manner, next, a pass / fail inspection is performed on each of the memory chips 1 (second step). For example, various functional tests are performed by pressing a test probe against a chip pad 3 formed on each memory chip 1 to make electrical contact therewith. Inspection efficiency is improved by performing the pass / fail inspection of each memory chip 1 on the whole semiconductor wafer 2 as a unit, that is, by conducting pass / fail inspection of a plurality of memory chips 1 formed on the semiconductor wafer 2 at one time. ing.

Next, based on the results of the pass / fail inspection in the second step, as shown in Fig. 1 (c), one or more (two or four) memory chips 1 determined to be non-defective are taken as a unit. Separate (third step).

FIG. 3 is a diagram illustrating an example of a method for separating a plurality of memory chips 1 formed on a semiconductor wafer 2. FIG. 3 (a) shows each memory chip in the second step described above. FIG. 9 is a diagram showing the results of a pass / fail inspection of the memory chip 1, in which a mark 〇 indicates a memory chip 1 determined to be good, and a mark X indicates a memory chip 1 determined to be defective. FIG. 3B is a diagram showing how the memory chip 1 determined to be non-defective in FIG. 3A is cut out, and a range surrounded by a solid line indicates a unit of cutting. As described above, the memory chip 1 is divided into one or more (two or four) units, but it is preferable to divide as many units as possible. Therefore, the segmentation method shown in Fig. 3 (b) is divided into four when four memory chips 1 can be cut out, and two when four memory chips 1 cannot be cut out. If one memory chip 1 cannot be cut out, the procedure is to cut out only one. When this separation method is applied to the results of the pass / fail inspection shown in Fig. 3 (a), as shown in Fig. 3 (b), one set of four memory chips 1 is Three sets are obtained by cutting one memory chip 1, and three sets are obtained by cutting one memory chip 1. In this way, one or more semiconductor devices are manufactured.

Next, as shown in Fig. 1 (d), the divided memory chip 1 is mounted on the substrate 4, and finally, the memory module 10a having four memory chips 1 and the memory module having two memory chips 1 are obtained. Complete one of the module 10b and the memory module 10c taken out (fourth step). For example, as a mounting method on the substrate 4, a chip pad 3 formed on the memory chip 1 and an electrode (not shown) formed on the substrate 4 are connected using a bonding wire.

A memory module 10a having four memory chips 1 is a substrate on which the memory module 10a is mounted, assuming that the bit configuration of each memory chip 1 is 16M x 4 bits, for example. Can be used as any of 16MX16-bit, 32-Mx8-bit, and 64Mx4-bit memory elements, depending on the wiring method of c) Can be handled in the same way as a single memory element, so that the process of mounting on another substrate or the like can be simplified.

Similarly, a memory module 10b including two memory chips 1 implements the memory module 10b when the bit configuration of each memory chip 1 is 16M x 4 bits. Depending on the wiring method of the board to be mounted, it can be used as either a 16 MX 8-bit or a 32 MX 4-bit memory element. In addition, since the memory module 10b can be handled in the same manner as a single memory element, the process of mounting the memory module on another substrate or the like can be simplified.

As described above, a plurality of the same memory chips 1 are formed on the semiconductor wafer 2, and only those which are determined to be non-defective by the quality inspection are cut out of the memory chips 1 to manufacture the memory module 10. As a result, the entire memory module 10 does not become defective because some of the memory chips 1 included in the memory module 10 are defective. Can be reduced.

Further, since the pass / fail inspection of the plurality of memory chips 1 formed on the semiconductor wafer 2 is performed at once for the entire semiconductor wafer 2, the efficiency of the inspection can be increased. Furthermore, the memory chip 1 is cut from the semiconductor wafer 2 in units of one or more (two or four), but as many as possible are cut into one unit, that is, four chips are cut as much as possible. Thus, the memory module 10a having four memory chips 1 can be efficiently manufactured.

In addition, the memory module 10a and the memory module 10b are mounted in such a manner that a plurality of the memory chips 1 formed on the semiconductor wafer 2 are collectively cut and separated-that is, a plurality of the memory chips 1 are connected to each other. Since they are mounted in a state, the memory chips 1 are cut out one by one from the semiconductor wafer 2, and compared with the case where the memory modules are formed by mounting the memory chips 1 at intervals, the components of the high-density mounting are reduced. The size can be reduced. In addition, since a plurality of semiconductor chips 1 can be mounted at one time, the manufacturing process can be simplified.

Next, a memory module according to a second embodiment of the present invention will be described. The memory module of the present embodiment is manufactured by a chip size package (CSP; Chip Size Package) mounting technology. FIG. 4 is a diagram showing a manufacturing process of the memory module of the present embodiment.

First, as shown in FIGS. 4 (a) and (b), a semiconductor wafer 12 is introduced. The same memory chip 11 is formed on the semiconductor wafer 12 (first step). Each of a plurality of regions surrounded by a dotted line in FIG. 4 (b) indicates one unit (minimum unit of division) of the memory chip 11 after CSP mounting. Next, as shown in FIG. 4C, CSP mounting is performed on the entire semiconductor wafer 12 in a state where a plurality of memory chips 11 are formed, and after forming wiring and resin sealing, forming terminals. (Second step). FIG. 5 is an enlarged cross-sectional view of the memory chip 11 mounted with CSP. As shown in Fig. 5, CSP-mounted memory chip 11 is composed of semiconductor wafer 12, wiring board 13, via 'post 14, norya' metal 15, resin layer 16, and solder ball It is composed including 1 7.

The wiring pattern 13 is formed by processing a metal thin film formed on the surface of the semiconductor wafer 12 with a resist, and then performing an electrolytic plating process. The via post 14 is connected to the wiring pattern 13, and a barrier metal 15 is formed on the top of the via post 14. The resin layer 16 seals the surface of the semiconductor wafer 12. The resin layer 16 has a thickness substantially equal to the height of the via post 14, and the barrier metal 15 is exposed to the outside when the resin is sealed. The solder ball 17 is a connection terminal for making an electrical connection with a substrate on which the memory chip 11 is mounted.

With the plurality of memory chips 11 thus formed on the semiconductor wafer 12 mounted on the CSP, a pass / fail inspection of each memory chip 11 is performed (third step). For example, various functional tests are performed by pressing a test probe against a solder ball 17 formed corresponding to each memory chip 11 to make it electrically contact. By performing the pass / fail inspection of the memory chip 11 on the whole semiconductor wafer 12 as a unit, that is, by performing pass / fail inspection of a plurality of memory chips 11 formed on the semiconductor wafer 12 at once, the inspection efficiency is improved. Is being improved.

Next, based on the results of the pass / fail inspection in the third step, as shown in FIG. 4 (d), one or more memory chips 11 after the mounting of the CSPs determined to be non-defective are mounted.

(2 or 4) are divided into units, and finally, a memory module 20a with four memory chips 11 and a memory module with two memory chips 11

Complete one of the memory modules 20 c that has been taken out. Process). As a specific dividing method, the dividing method shown in FIG. 3 in the first embodiment described above is applied.

As described above, after forming the same memory chips 11 on the semiconductor wafer 12, the CSP mounting is performed, and among the memory chips 11 after the CSP mounting, the memory chips 11 are determined to be non-defective by the quality inspection. The memory module 20 as a semiconductor device is manufactured by cutting only the memory module 20.Since some of the memory chips 11 included in the memory module 20 are defective, the entire memory module 20 is defective. Therefore, the defect rate when manufacturing the memory module 20 can be reduced.

In addition, as the memory module 20a and the memory module 20b, a plurality of memory chips 11 cut out from the semiconductor wafer 12 are mounted. For this reason, compared to the case where memory chips 11 are cut out from the semiconductor wafer 12 one by one and then mounted at intervals between the memory chips 1, memory components are reduced by high-density mounting. Becomes possible. In particular, since CSP mounting is used, the mounting area is minimized. Further, since the memory modules 20a and the like including as many memory chips 11 as possible are cut out based on the pass / fail pattern, it is possible to efficiently manufacture the multi-cavity memory modules 20a and the like. it can. The present invention is not limited to the above embodiment, and various modifications can be made within the scope of the present invention. For example, in each of the memory chips 1 included in the semiconductor wafer 2 of the first embodiment described above, the corresponding terminals may be connected to each other by wiring in each of the memory chips 1. For example, a common power supply voltage is applied to a power supply terminal of each memory chip 1, and a common operation clock signal is input to a clock terminal. If the terminals to which the same voltage is applied or the signals to which the same signal is input are connected when forming each memory chip 1 and four or two are cut out at the same time, four or two A common voltage is applied to any one of the memory chips 1 or a common signal is input. In this way, by interconnecting the memory chips 1 with each other, the amount of wiring between the plurality of memory chips 1 and the board 4 on which the memory chips 1 are mounted can be reduced, and the mounting process can be simplified. become. However, since it is not known how to combine and cut out adjacent memory chips 1 until a pass / fail inspection is performed, as shown in FIG. 6, the same terminals of all the adjacent memory chips 1 are wired to each other. It is preferable to keep it. Further, as an example, the case where the power supply terminal and the clock terminal are connected to each other has been described, but other terminals, for example, the address terminal and the data terminal may be connected to each other. When the same address terminals are connected to each other, for example, when the bit configuration of one memory chip 1 is 16 M x 4 bits, the memory module 10 b that cuts out two memory chips 1 at the same time has 16 M x An 8-bit bit configuration can be easily realized with a small amount of wiring, and a memory module 10a that simultaneously cuts out four memory chips 1 can easily realize a 16-M x 16-bit bit configuration with a small amount of wiring. . When the same data terminals are connected to each other, for example, when the bit configuration of one memory chip 1 is 16 M x 4 bits, the memory module 10b that cuts out two memory chips 1 at the same time is 3 2 The M x 4 bit configuration can be easily realized with a small amount of wiring, and the memory module 10a that cuts out four memory chips 1 at the same time can easily realize the 64 MX 4-bit configuration with a small amount of wiring. Can be realized.

Similarly, the corresponding terminals of the respective memory chips 11 included in the semiconductor wafer 12 of the second embodiment described above may be connected to each other by wiring. However, in this case, in addition to the case of connecting the terminals of each memory chip 11 to each other on the semiconductor wafer 12, the wiring formed when performing CSP mounting (the wiring pattern 13 shown in FIG. 5) ) May be used to connect the terminals of each memory chip 11 to each other.

Further, in the above-described embodiment, the bit configuration of each memory chip 1 is 16 M × 4 bits, the force ^s may be other bit configurations, and the memory chip 1 having a different bit configuration or capacity may be used. They may be combined. Further, in the above-described embodiment, the case where a memory chip is used as a semiconductor chip and a memory module as a semiconductor device is manufactured has been described as an example. However, a semiconductor chip other than a memory chip, for example, various chips such as a processor chip and an ASIC. The present invention can be applied to the case where a semiconductor device is manufactured using a semiconductor device.

Also, in the first embodiment described above, a plurality of or one memos are cut out one by one. Although the rechip 1 is mounted on the substrate 4 to form the memory module 10, the memory chip 1 may be mounted directly on a motherboard or the like of a personal computer. Industrial applicability

As described above, according to the present invention, a semiconductor chip is separated from a semiconductor wafer in units of one or a plurality of units according to the result of a pass / fail inspection, so that a high-density mounting composed of a plurality of semiconductor chips is realized. When manufacturing possible semiconductor devices, some of the semiconductor chips in them are defective, so that the entire semiconductor device does not become defective, reducing the defect rate when manufacturing semiconductor devices. ₍ Also, since a semiconductor device composed of a plurality of semiconductor chips can be used in a subsequent step, the subsequent The process can be simplified.

Claims

The scope of the claims

1. A plurality of identical semiconductor chips are formed on a semiconductor wafer, and the semiconductor chips are formed by dividing the semiconductor chips into one or more units according to the result of a pass / fail inspection of each semiconductor chip. Semiconductor device.

2. The semiconductor device according to claim 1, wherein the semiconductor chip is a memory chip.

3. After wiring, sealing with resin, and forming terminals for a plurality of identical semiconductor chips formed on a semiconductor wafer, one or more units may be used as a unit depending on the result of the quality inspection of each semiconductor chip. A semiconductor device formed by cutting the semiconductor chip.

4. The semiconductor device according to claim 3, wherein the semiconductor chip is a memory chip.

5. A first step of forming a plurality of identical semiconductor chips on a semiconductor wafer, and a second step of performing a pass / fail inspection of each of the plurality of semiconductor chips formed on the semiconductor wafer,

A third step of separating one or more of the semiconductor chips based on a result of the pass / fail inspection;

A method for manufacturing a semiconductor device, comprising:

6. The method for manufacturing a semiconductor device according to claim 5, wherein the semiconductor chip is a memory chip.

7. The separation of the plurality of semiconductor chips performed after the pass / fail inspection is performed by grouping four chips when four are possible, and two when four are impossible and two are possible. 6. The method for manufacturing a semiconductor device according to claim 5, wherein, when two pieces are impossible, one piece is performed when two pieces are impossible.

8. A first step of forming a plurality of identical semiconductor chips on a semiconductor wafer and a second step of performing wiring, resin sealing, and terminal formation on the plurality of semiconductor chips formed on the semiconductor wafer When,

A third step of performing a pass / fail inspection of each of the plurality of semiconductor chips formed on the semiconductor wafer using the terminals formed in the second step; A fourth step of separating one or more of the semiconductor chips based on the result of the pass / fail inspection;

A method for manufacturing a semiconductor device, comprising:

9. The method for manufacturing a semiconductor device according to claim 8, wherein the semiconductor chip is a memory chip.

10. The separation of a plurality of the semiconductor chips performed after the pass / fail inspection is performed by grouping four chips when four chips are possible, and when four chips are impossible and two chips are possible. 9. The method for manufacturing a semiconductor device according to claim 8, wherein two pieces are grouped together, and if two pieces are impossible, one piece is performed.