WO1999054932A1 - Leadless array package - Google Patents

Leadless array package Download PDF

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Publication number
WO1999054932A1
WO1999054932A1 PCT/US1999/003952 US9903952W WO9954932A1 WO 1999054932 A1 WO1999054932 A1 WO 1999054932A1 US 9903952 W US9903952 W US 9903952W WO 9954932 A1 WO9954932 A1 WO 9954932A1
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WO
WIPO (PCT)
Prior art keywords
base layer
integrated circuit
chip
package
leadless
Prior art date
Application number
PCT/US1999/003952
Other languages
French (fr)
Inventor
Julius A. Kovats
Paul I. Suciu
Original Assignee
Atmel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corporation filed Critical Atmel Corporation
Publication of WO1999054932A1 publication Critical patent/WO1999054932A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3442—Leadless components having edge contacts, e.g. leadless chip capacitors, chip carriers

Definitions

  • This invention relates to the field of integrated circuit packages.
  • J leads Another type of leads used are "J leads", in which the leads are tucked under the device and shaped like the letter “J” .
  • J-leads are commonly used on - 2 -
  • plastic-leaded chip carriers PLCCs
  • J-leads plastic-leaded chip carriers
  • U.S. Patent No. 5,535,101 to Miles et al discloses a leadless integrated circuit package that uses a ball grid array for mounting to the printed circuit board.
  • a ball grid array mounts to the printed circuit board using solder balls located on the underside of the package.
  • solder balls located on the underside of the package.
  • BGA ball grid array
  • the solder joints are hidden beneath the package, making visual inspection and in-situ probe testing virtually impossible.
  • the cost of a BGA system is higher because BGAs have a circuit board that holds the chip and fans out the leads .
  • BGAs take less space from an area standpoint, routing traces to them use more PCB layers. This can serve to increase the cost of the overall system.
  • the present invention is an integrated circuit package that mounts directly to a PCB, without pins, but has accessible contacts for testing and inspection.
  • the leadless package of the present invention uses contacts on the edge of the package that extend over the solder reflow pads on the end user's board to mount to the printed circuit board.
  • the leadless package has a footprint similar to a standard surface mount package. Because of the method used for mounting, larger silicon die can be used than in the standard packaging. Because there are no leads, the space which would otherwise be used by a lead frame is now useable for containing the silicon device chip.
  • the leadless array package has a substrate made of the same material as most end user's printed circuit boards so thermal mismatch, which is a common problem with surface mount components, is significantly reduced. Additionally, because the electrical contacts are on the outside perimeter of the leadless array package, inspection and testing of the package can be done much more easily than for packages that have ball-grid array type mounting systems.
  • Fig. 1 is a perspective view of a leadless array package.
  • Fig. 2 is a top view of an arrangement of leadless array packages during a manufacturing stage illustrating a first embodiment of the invention.
  • Fig. 3 is another top view of an arrangement of leadless array packages during a manufacturing stage illustrating a second embodiment of the invention.
  • Fig. 4 is a perspective view of a leadless array package illustrating the method of mounting the package on the end user's printed circuit board.
  • the leadless array package 10 is assembled in a sort of "sandwich" arrangement.
  • a base layer 21, made of a substrate material, comprises the bottom of the leadless array package.
  • An integrated circuit chip 15 is bonded on top of the base layer 21, and an encapsulant material 11 covers the top of the integrated circuit chip 15 and the base layer 21.
  • the complete leadless array package 10 is then ready to be mounted on the end user's printed circuit board.
  • the base layer 21 is made of a substrate material such as epoxy-glass or another suitable material that is commonly used for - 4 -
  • the reason for using this type of substrate material for the base layer 21 is that by using the same or similar material for the substrate as that material of which the end user's printed circuit board is made, the possibility of thermal mismatch is significantly reduced. By reducing the possibility of thermal mismatch, mechanical stresses due to differing thermal expansion coefficients are reduced, which consequently reduces the possibility of solder and wire bond failures in the chip package.
  • the base layer 21 will eventually be singulated, at the end of the manufacturing process, into individual separate base layer areas 16, one base layer area for each chip.
  • the length 14 and width 12 of each individual base layer area 16 is equivalent to the standard dimensions of a small outline integrated circuit (SOIC) chip package footprint.
  • SOIC small outline integrated circuit
  • the substrate material for the base layer 21 is generally thin, having a nominal thickness of approximately 0.38 - 0.64 millimeters.
  • the base layer is made of an 35 mm epoxy-glass tape that is packaged on a roll, similar to 35 mm movie film. The use of the epoxy-glass tape in this form makes the manufacturing process compatible with many automated handling, testing and placement systems and is also convenient for parallel testing.
  • the present invention may also be able to be used with other types of IC footprints, such as TSOP, but it must be used with an integrated circuit chip having a small lead count (32 pins or smaller) . This is because the leads of the IC chip must be on the perimeter of the TSOP.
  • IC chip in order to be accessible after mounting.
  • the number of leads are limited by the size of the perimeter of the IC chip. Even at minimum width, spacing must exist between leads to prevent shorting. To gain addi- tional space, all four sides of the chip may be used for leads, provided that the user can provide PCB routing for the leads. If the IC chip is too large, thermal mismatches between the silicon die of the chip and the base layer substrate are too great and the chip package would be very likely to crack. The proper size chip must be determined for each base layer area.
  • a series of metal bonding pads 19 on which the integrated circuit chips 15 can be mounted on top of the base layer 21 are arranged.
  • the metal bonding pads 19 are arranged to correspond to the size of the integrated circuit chip 15.
  • the metal pads 19 can be arranged to accommodate IC chips having contacts on two sides or four sides. In Fig. 2, the contacts are shown to be on two sides of the IC chip.
  • the integrated circuit chip 15 is generally smaller than the individual base layer area 16, but it can be the same size as the base layer area 16 (and hence, the same size as a standard SOIC package) . In Fig. 2, the integrated circuit chip 15 is smaller than the base layer area 16.
  • One integrated circuit chip 15 is to be mounted in each base layer area 16.
  • a large array of integrated circuit chips (such as 100 x 150 chips) can be laid out. It is advantageous to manufacture a large number of chip packages at one time, as it saves time and cost to be able to manufacture and test a large number of chip packages at once.
  • the IC chips 15 are laid out on the base layer 21, die are attached to the top side of the board and are wire bonded 13 between the metal chip pads 19 and the board contacts 23, which are on the edge of each individual base layer area 16.
  • the industry standard size chip is used, as in Fig. 2, generally there is about 1.4 mm of space between the edge of the chip 15 and the edge of the base layer 21 to allow for standard wire bond and die attachment .
  • Fig. 3 serves to illustrate the case when the size of the IC chip 15 is the same as the size of the base layer area (defined in Fig. 2 as the area having the length 14 and width 12 of the standard SOIC package) .
  • the distance between the metal chip pads 19 and the board contacts 23 is minimal and, instead of wire - 6 -
  • an encapsulant material preferably an epoxy overcoat or plastic molding, is applied over the entire array of integrated circuit chips 15 and the base layer 21.
  • this encapsulant material should be no more than 2 mm in thickness.
  • the entire base layer 21, having IC chips attached and covered by the encapsulant material 11 is partially divided into individual array packages. The partial singulation electrically isolates each individual chip package from the other chip packages so that they may be individually tested.
  • the size of the individual chip array package is the same as that of the standard dimensions of a SOIC chip package. In this way, the array package will fit in the standard size SOIC footprint .
  • the chip packages are tested.
  • these tests will consist of the standard industry production tests that are intended to determine whether there are any localized fabrication faults that will cause failure of the integrated circuit. These tests can be carried out by conventional testing equipment, such as probe cards or wafer probers and the like. Most conventional testing devices have probes that are small enough to contact the board contacts 23 (that are connected to the bonding pads) . The potential also exists for testing several of the chip packages in parallel. After the chips are tested and are found to have been in compliance with the test requirements, the base layer is completely divided into individual chip packages. This final singulation after testing is generally just a laser cut to completely separate the chip packages (all of the electrical connections between the chip packages having already been separated before testing) . - 7 -
  • the completed IC array package 10 can be installed on the end-user's printed circuit board 59.
  • the IC array package 10 is placed on top of solder pads 57 on the printed circuit board 59.
  • the solder pads 57 correspond to the board contacts 23 which are exposed on the edge of the IC array package 10.
  • Solder paste is applied to the solder pads 57 and then the printed circuit board 59 and IC array package are heated in a convection furnace.
  • the solder paste wicks up and there is solder flow 55 between the solder pads 57 and the board contacts 23. When the solder flow cools, after removal from the furnace, an electrical and mechanical connection exists between the leadless array package 10 and the printed circuit board

Abstract

A leadless array integrated circuit package that uses a standard surface mount footprint, but allows use of larger silicon die. The leadless array package (10) mounts to the end user's printed circuit board (59) by solder flow contacts (23) on the perimeter of the chip package that melds with solder paste applied to the printed circuit board (59) and heated in a furnace during package fabrication. The IC chip (15) is laid on a substrate (21) made of a printed circuit board material to reduce thermal mismatches between the leadless array package (10) and the end user's printed circuit board (59).

Description

Description
LEADLESS ARRAY PACKAGE
FIELD OF THE INVENTION
This invention relates to the field of integrated circuit packages.
BACKGROUND ART In integrated circuit fabrication, a continuing challenge is to manufacture electrical assemblies with greater densities and smaller package size. It is extremely important to utilize available space on a printed circuit board in the most efficient manner possible. The trend in integrated circuit packaging is away from traditional dual-in-line and through-hole packaging and towards surface-mount packages, such as small outline packages, ball grid arrays and chip carrier packages. Surface mounting is a process in which a packaged IC is physically mounted onto the surface of a printed circuit board (PCB) , rather than inserting leads into plated holes through the PCB. Package specifications, such as outlines, pin configuration, and dimensions are often defined by industry associations, such as JEDEC.
Most surface-mount devices use leads to mount the chip packages onto the surface of a PCB. Small outline IC packages (SOICs) and quad flat packs (QFPs) frequently use "gull wing" leads, which spread away from the device. The main advantage of the gull wing is that the solder joint can be easily inspected. The disadvantage is that the exposed leads tend to bend and break in handling prior to reflow on the system board. Another disadvantage is that the leads take additional space on the PCB since the leads are spread out.
Another type of leads used are "J leads", in which the leads are tucked under the device and shaped like the letter "J" . "J-leads" are commonly used on - 2 -
plastic-leaded chip carriers (PLCCs) . The advantages of the "J-leads" are that they occupy less board space and that the leads are protected underneath the device. However, this makes it more difficult to test, inspect or repair the device and does not allow for pow profile mounting.
Leadless integrated circuit packaging is known in the prior art. U.S. Patent No. 5,535,101 to Miles et al . discloses a leadless integrated circuit package that uses a ball grid array for mounting to the printed circuit board. A ball grid array mounts to the printed circuit board using solder balls located on the underside of the package. There are some advantages to this arrangement such as the package being smaller in size due to the lack of leads jutting out from the edge of the package. However, there are some disadvantages to the ball grid array (BGA) system. Firstly, the solder joints are hidden beneath the package, making visual inspection and in-situ probe testing virtually impossible. Also, the cost of a BGA system is higher because BGAs have a circuit board that holds the chip and fans out the leads . Although BGAs take less space from an area standpoint, routing traces to them use more PCB layers. This can serve to increase the cost of the overall system.
SUMMARY OF THE INVENTION
The present invention is an integrated circuit package that mounts directly to a PCB, without pins, but has accessible contacts for testing and inspection. The leadless package of the present invention uses contacts on the edge of the package that extend over the solder reflow pads on the end user's board to mount to the printed circuit board. The leadless package has a footprint similar to a standard surface mount package. Because of the method used for mounting, larger silicon die can be used than in the standard packaging. Because there are no leads, the space which would otherwise be used by a lead frame is now useable for containing the silicon device chip.
The leadless array package has a substrate made of the same material as most end user's printed circuit boards so thermal mismatch, which is a common problem with surface mount components, is significantly reduced. Additionally, because the electrical contacts are on the outside perimeter of the leadless array package, inspection and testing of the package can be done much more easily than for packages that have ball-grid array type mounting systems.
BRIEF DESCRIPTION OF THE DRAWINGS
Fig. 1 is a perspective view of a leadless array package.
Fig. 2 is a top view of an arrangement of leadless array packages during a manufacturing stage illustrating a first embodiment of the invention.
Fig. 3 is another top view of an arrangement of leadless array packages during a manufacturing stage illustrating a second embodiment of the invention.
Fig. 4 is a perspective view of a leadless array package illustrating the method of mounting the package on the end user's printed circuit board.
BEST MODE FOR CARRYING OUT THE INVENTION
With reference to Fig. 1, the leadless array package 10 is assembled in a sort of "sandwich" arrangement. A base layer 21, made of a substrate material, comprises the bottom of the leadless array package. An integrated circuit chip 15 is bonded on top of the base layer 21, and an encapsulant material 11 covers the top of the integrated circuit chip 15 and the base layer 21. The complete leadless array package 10 is then ready to be mounted on the end user's printed circuit board.
With reference to Fig. 2, the base layer 21 is made of a substrate material such as epoxy-glass or another suitable material that is commonly used for - 4 -
anufacturing printed circuit boards . The reason for using this type of substrate material for the base layer 21 is that by using the same or similar material for the substrate as that material of which the end user's printed circuit board is made, the possibility of thermal mismatch is significantly reduced. By reducing the possibility of thermal mismatch, mechanical stresses due to differing thermal expansion coefficients are reduced, which consequently reduces the possibility of solder and wire bond failures in the chip package. The base layer 21 will eventually be singulated, at the end of the manufacturing process, into individual separate base layer areas 16, one base layer area for each chip. The length 14 and width 12 of each individual base layer area 16 is equivalent to the standard dimensions of a small outline integrated circuit (SOIC) chip package footprint. The substrate material for the base layer 21 is generally thin, having a nominal thickness of approximately 0.38 - 0.64 millimeters. In one embodiment of this invention, the base layer is made of an 35 mm epoxy-glass tape that is packaged on a roll, similar to 35 mm movie film. The use of the epoxy-glass tape in this form makes the manufacturing process compatible with many automated handling, testing and placement systems and is also convenient for parallel testing.
The present invention may also be able to be used with other types of IC footprints, such as TSOP, but it must be used with an integrated circuit chip having a small lead count (32 pins or smaller) . This is because the leads of the IC chip must be on the perimeter of the
IC chip in order to be accessible after mounting. The number of leads are limited by the size of the perimeter of the IC chip. Even at minimum width, spacing must exist between leads to prevent shorting. To gain addi- tional space, all four sides of the chip may be used for leads, provided that the user can provide PCB routing for the leads. If the IC chip is too large, thermal mismatches between the silicon die of the chip and the base layer substrate are too great and the chip package would be very likely to crack. The proper size chip must be determined for each base layer area.
Continuing with reference to Fig. 2, on top of the base layer 21 are arranged a series of metal bonding pads 19 on which the integrated circuit chips 15 can be mounted. The metal bonding pads 19 are arranged to correspond to the size of the integrated circuit chip 15. The metal pads 19 can be arranged to accommodate IC chips having contacts on two sides or four sides. In Fig. 2, the contacts are shown to be on two sides of the IC chip. The integrated circuit chip 15 is generally smaller than the individual base layer area 16, but it can be the same size as the base layer area 16 (and hence, the same size as a standard SOIC package) . In Fig. 2, the integrated circuit chip 15 is smaller than the base layer area 16. One integrated circuit chip 15 is to be mounted in each base layer area 16. Over the entire base layer 21, a large array of integrated circuit chips (such as 100 x 150 chips) can be laid out. It is advantageous to manufacture a large number of chip packages at one time, as it saves time and cost to be able to manufacture and test a large number of chip packages at once. When the IC chips 15 are laid out on the base layer 21, die are attached to the top side of the board and are wire bonded 13 between the metal chip pads 19 and the board contacts 23, which are on the edge of each individual base layer area 16. When the industry standard size chip is used, as in Fig. 2, generally there is about 1.4 mm of space between the edge of the chip 15 and the edge of the base layer 21 to allow for standard wire bond and die attachment .
Fig. 3 serves to illustrate the case when the size of the IC chip 15 is the same as the size of the base layer area (defined in Fig. 2 as the area having the length 14 and width 12 of the standard SOIC package) . In this case, the distance between the metal chip pads 19 and the board contacts 23 is minimal and, instead of wire - 6 -
bonding, flip chip/bump technology is used to attach the IC chip 15 to the base layer area 16.
Referring back again to Fig. 2, after wire bonding and die attachment, an encapsulant material 11, preferably an epoxy overcoat or plastic molding, is applied over the entire array of integrated circuit chips 15 and the base layer 21. Generally, this encapsulant material should be no more than 2 mm in thickness. Then, the entire base layer 21, having IC chips attached and covered by the encapsulant material 11, is partially divided into individual array packages. The partial singulation electrically isolates each individual chip package from the other chip packages so that they may be individually tested. As discussed above, the size of the individual chip array package is the same as that of the standard dimensions of a SOIC chip package. In this way, the array package will fit in the standard size SOIC footprint .
After the partial division into individual chip packages described above, the chip packages are tested.
Typically, these tests will consist of the standard industry production tests that are intended to determine whether there are any localized fabrication faults that will cause failure of the integrated circuit. These tests can be carried out by conventional testing equipment, such as probe cards or wafer probers and the like. Most conventional testing devices have probes that are small enough to contact the board contacts 23 (that are connected to the bonding pads) . The potential also exists for testing several of the chip packages in parallel. After the chips are tested and are found to have been in compliance with the test requirements, the base layer is completely divided into individual chip packages. This final singulation after testing is generally just a laser cut to completely separate the chip packages (all of the electrical connections between the chip packages having already been separated before testing) . - 7 -
With reference to Fig. 4, the completed IC array package 10, can be installed on the end-user's printed circuit board 59. The IC array package 10 is placed on top of solder pads 57 on the printed circuit board 59. The solder pads 57 correspond to the board contacts 23 which are exposed on the edge of the IC array package 10. Solder paste is applied to the solder pads 57 and then the printed circuit board 59 and IC array package are heated in a convection furnace. The solder paste wicks up and there is solder flow 55 between the solder pads 57 and the board contacts 23. When the solder flow cools, after removal from the furnace, an electrical and mechanical connection exists between the leadless array package 10 and the printed circuit board

Claims

Claims
1. A leadless integrated circuit package comprising: an integrated circuit chip having a plurality of interconnection pads on a perimeter thereof; a base layer having a length and a width and having two opposed major sides including a top side having a plurality of bonding pads arranged on the perimeter of the base layer and corresponding to the interconnection pads on the integrated circuit chip, the integrated circuit chip being bonded to the top side of the base layer; an encapsulant material covering the integrated circuit chip and the top side of the base layer; and a series of board contacts arranged around the perimeter on an outer edge of the base layer and connected to the bonding pads and not being covered by the encapsulant material so that the board contacts are exposed for solder flow connection to an external circuit board.
2. A leadless integrated circuit package, as in claim 1, wherein the base layer is comprised of epoxy-glass.
3. A leadless integrated circuit package, as in claim 1, wherein the integrated circuit chip has a length and width less than or equal to the length and width of the base layer.
4. A leadless integrated circuit package, as in claim 1, wherein the length and the width of the base layer correspond to the standard length and width of a standard small outline integrated circuit (SOIC) footprint. - 9 -
5. A leadless integrated circuit package comprising: a base layer made of an insulating substrate and having two opposed sides including a top side having a plurality of bonding pads arranged on a perimeter of the base layer; an integrated circuit chip having a plurality of interconnection pads on a perimeter thereof, the integrated circuit chip having a silicon die being of the same size or smaller than the size of the base layer, the integrated circuit chip being attached to the top side of the base layer; an encapsulant material enclosing the integrated circuit chip and the top side of the base layer; and a series of board contacts arranged on the perimeter on an outer edge of the base layer connected to the bonding pads on the perimeter of the base layer and not being covered by the encapsulant material so that the board contacts are exposed for solder flow connection to an external circuit board.
6. A leadless integrated circuit package, as in claim 5, wherein the base layer is comprised of epoxy-glass.
7. A leadless integrated circuit package, as in claim 5, wherein the integrated circuit chip has a lead count of less than thirty three chip contacts. - 10 -
8. A method for constructing a leadless integrated circuit package, the method comprising the steps of: arranging a series of metal bonding pads on a top side of a base layer, the base layer being made of an insulating substrate; attaching an array of integrated circuit chips to the metal bonding pads; covering the integrated circuit chips and the base layer with an encapsulant material; separating partially and electrically isolating the base layer into individual chip packages; testing the individual chip packages on the base layer to determine whether there are any fabrication faults; and separating the base layer completely so that the chip packages are singulated into individual chip packages .
9. A method for constructing a leadless integrated circuit package, as in claim 8, wherein the integrated circuit chips and the base layer each have a length and a width, the length and the width of the integrated circuit chips being smaller than the length and the width of the base layer.
10. A method for constructing a leadless integrated circuit package, as in claim 8, wherein the integrated circuit chips and the base layer each have a length and a width, the length and the width of the integrated circuit chip being equal to the length and the width of the base layer. AMENDED CLAIMS
[received by the International Bureau on 28 May 1999 (28.05.99); original claims 1 and 5 amended; remaining claims unchanged (2 pages)]
1. A leadless integrated circuit package comprising: an integrated circuit chip having a plurality of interconnection pads on a perimeter thereof; a base layer having a length and a width and having two opposed major sides including a top side having outer edges and having a plurality of bonding pads arranged on a perimeter of the base layer and corresponding to the interconnection pads on the integrated circuit chip, the integrated circuit chip being bonded to the top side of the base layer; an encapsulant material covering the integrated circuit chip and extending to the outer edges of the top side of the base layer; and a series of board contacts arranged around the perimeter on at least one of the outer edges of the top side of the base layer and being connected to the bonding pads and not being covered by the encapsulant material so that the board contacts are exposed for solder flow connection to an external circuit board.
2. A leadless integrated circuit package, as in claim 1, wherein the base layer is comprised of epoxy-glass.
3. A leadless integrated circuit package, as in claim 1, wherein the integrated circuit chip has a length and width less than or equal to the length and width of the base layer.
4. A leadless integrated circuit package, as in claim 1, wherein the length and the width of the base layer correspond to the standard length and width of a standard small outline integrated circuit (SOIC) footprint.
5. A leadless integrated circuit package comprising: a base layer made of an insulating substrate and having two opposed sides including a top side having outer edges and having a plurality of bonding pads arranged on a perimeter of the base layer, the base layer being of a size corresponding to a standard integrated circuit footprint; an integrated circuit chip having a plurality of interconnection pads on a perimeter thereof, the integrated circuit chip having a silicon die being of the same size or smaller than the size of the base layer, the integrated circuit chip being attached to the top side of the base layer; an encapsulant material enclosing the integrated circuit chip and extending to the outer edges of the top side of the base layer; and a series of board contacts arranged around the perimeter on at least one of the outer edges of the top side of the base layer and being connected to the bonding pads on the perimeter of the base layer and not being covered by the encapsulant material so that the board contacts are exposed for solder flow connection to an external circuit board.
6. A leadless integrated circuit package, as in claim 5, wherein the base layer is comprised of epoxy-glass.
7. A leadless integrated circuit package, as in claim 5, wherein the integrated circuit chip has a lead count of less than thirty three chip contacts. STATEMENT UNDER ARTICLE 19
Applicant is amending independent claims 1 and 5 to point out that the series of board contacts are arranged around the perimeter on at least one of the outer edges of the top side of the base layer. Additionally, the amended claims specify that the encapsulant material covers the integrated circuit chip and extends to the outer edges of the top side of the base layer. However, it is also claimed that the board contacts are not covered by the encapsulant material so that the board contacts are exposed.
The cited Moriya a reference does not have the board contacts arranged on the edge of the base layer of the carrier chip. In the Moriyama reference, the board contacts are arranged on a printed circuit board that is external to the semiconductor chip carrier package and the chip carrier is mounted on the printed circuit board by electrode leads which connect to the board contacts. Additionally, in the Moriyama device, the encapsulant material covers the integrated circuit chip, but does not extend to the outer edges of the base layer as claimed in the amended claims of the present invention.
The present invention is providing a leadless array package that uses board contacts on the edge of the package that extend over solder reflow pads on an external circuit board to mount the package to the printed circuit board. This allows the chip package to use less space for mounting than in a standard surface mount package having a lead frame. Also, because there are no leads, the space which would otherwise be used by a lead frame is now useable for containing the silicon device chip, therefore allowing larger silicon die to be used than in the standard packaging structures.
PCT/US1999/003952 1998-04-21 1999-02-24 Leadless array package WO1999054932A1 (en)

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