WO1999038086A3 - Bus bridge architecture for a data processing system - Google Patents

Bus bridge architecture for a data processing system Download PDF

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Publication number
WO1999038086A3
WO1999038086A3 PCT/US1999/001890 US9901890W WO9938086A3 WO 1999038086 A3 WO1999038086 A3 WO 1999038086A3 US 9901890 W US9901890 W US 9901890W WO 9938086 A3 WO9938086 A3 WO 9938086A3
Authority
WO
WIPO (PCT)
Prior art keywords
data processing
processing system
bus
processor
secondary processor
Prior art date
Application number
PCT/US1999/001890
Other languages
French (fr)
Other versions
WO1999038086A2 (en
Inventor
Louis H Odenwald Jr
Steven R Schremmer
Original Assignee
Lsi Logic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lsi Logic Corp filed Critical Lsi Logic Corp
Publication of WO1999038086A2 publication Critical patent/WO1999038086A2/en
Publication of WO1999038086A3 publication Critical patent/WO1999038086A3/en

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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges

Abstract

The method and apparatus provides a data processing system (200). The data processing system includes a primary bus (204), a secondary bus (210), and a host processor (202) connected to the primary bus. The data processing system includes a first secondary processor (208) connected to the primary bus and the secondary bus. Additionally, a second secondary processor (210, 216) is connected to the secondary bus. The first secondary processor and the second secondary processor form cascaded processors for input/output functions. Selected functions normally performed by the second secondary processor are performed by the first secondary processor, wherein a division of workload increases performance of the data processing system. This architecture allows shifting of workload down to the secondary bus.
PCT/US1999/001890 1998-01-27 1999-01-26 Bus bridge architecture for a data processing system WO1999038086A2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/013,818 US6065085A (en) 1998-01-27 1998-01-27 Bus bridge architecture for a data processing system capable of sharing processing load among a plurality of devices
US09/013,818 1998-01-27

Publications (2)

Publication Number Publication Date
WO1999038086A2 WO1999038086A2 (en) 1999-07-29
WO1999038086A3 true WO1999038086A3 (en) 1999-11-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/001890 WO1999038086A2 (en) 1998-01-27 1999-01-26 Bus bridge architecture for a data processing system

Country Status (2)

Country Link
US (2) US6065085A (en)
WO (1) WO1999038086A2 (en)

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Publication number Publication date
US6065085A (en) 2000-05-16
WO1999038086A2 (en) 1999-07-29
US6223240B1 (en) 2001-04-24

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