WO1999032684A1 - Method for deposition of ferroelectric thin films - Google Patents
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- WO1999032684A1 WO1999032684A1 PCT/US1998/026258 US9826258W WO9932684A1 WO 1999032684 A1 WO1999032684 A1 WO 1999032684A1 US 9826258 W US9826258 W US 9826258W WO 9932684 A1 WO9932684 A1 WO 9932684A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/04—Coating on selected surface areas, e.g. using masks
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02197—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides the material having a perovskite structure, e.g. BaTiO3
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/84—Manufacture, treatment, or detection of nanostructure
- Y10S977/89—Deposition of materials, e.g. coating, cvd, or ald
- Y10S977/891—Vapor phase deposition
Definitions
- This invention relates to a method for the chemical vapor deposition of metal oxide thin films. More particularly, the present invention relates to the nucleation controlled chemical vapor deposition of metal oxide ferroelectric thin films.
- ferroelectric materials which have found wide use in random access memory applications.
- ferroelectric capacitors which typically evidence high remanent polarization, small size, low leakage current and low fatigue rate. Accordingly, workers in the art have focused their interest upon the development of suitable techniques for the growth of ferroelectric thin films evidencing optimum characteristics for use in such capacitors.
- the deposition rate of bismuth is found to be nearly independent of time from 0.5 torr to 8 torr. Early growth stages appear as islands which coalesce at longer times. Additionally, it is noted that the growth rate is significantly higher than those at equivalent partial pressures of bismuth for SBT when strontium and tantalum are present. Studies have also revealed that when SBT is deposited on bare platinum using triphenyl bismuth as a precursor, it is likely that the bismuth incorporates due to the catalytic effect of the platinum which is dependent on the nature of the platinum surface.
- Typical techniques for achieving surface roughening include reactive ion etching, inert ion milling and chemical mechanical polishing, each of which may be used to delineate patterned bottom electrodes.
- the chemical properties of the substrate may be modified by alloy deposition, deposition of seed layers which are then partially or completely in-diffused, and ion implantation with or without heat treatment.
- a nucleation step in the beginning of the deposition may be inserted either by having different physical parameters in the CVD chamber such as pressure, temperature, flow rate, deposition rate and the like, or by applying additional or different agents and/or changing the ratio of these agents which may be oxidizing or reducing in nature or having an additional activation in the beginning of the process as for example by a plasma, UV and the like.
- the resultant oxide ferroelectric thin films are suitable for use in capacitors, memory devices and the like.
- Fig. la is a front elevational view in cross-section of a typical FRAM cell including a CMOS transistor without a storage capacitor;
- Fig. lb is a front elevational view in cross section of the structure of Fig. la after the deposition thereon of a barrier layer and bottom electrode layer;
- Fig. lc is a front elevational view in cross section of the structure of Fig. lb after the patterning of the bottom electrode layer;
- Fig. Id is a front elevational view in cross section of the structure of Fig. lc after the chemical vapor deposition of a SrBi 2 Ta 2 0 9 (SBT) layer and a strontium tantalate layer;
- SBT SrBi 2 Ta 2 0 9
- Fig. le is a front elevational view in cross section of the structure of Fig. Id after the deposition thereon of a top electrode;
- the invention relates to the selective deposition of Bi-containing ferroelectric films.
- Bi-containing ferroelectric films are formed by, for example, using ⁇ - diketonate Bi precursor.
- ⁇ - diketonate Bi precursor The formation of Bi films with ⁇ -diketonate precursor is described in United States
- Patent Application USSN USSN (Attorney Docket Number ATMI-256A and ) , titled "Low
- Fig. la there is shown a front elevational view in cross-section of a typical ferroelectric random access memory cell (FRAM) .
- FRAM ferroelectric random access memory cell
- Shown in the figure is an insulating substrate 11, typically silicon dioxide (Si0 2 ) or silicon nitride (Si 3 N 4 ) , on top of a silicon substrate.
- CMOS transistor including source 12, drain 13 and gate 14.
- Source 12 and gate 14 are connected to bit line 15 and word line 16, respectively.
- Drain 13 is connected to plug 14 which is designed to serve as connection to a stack capacitor having a bottom electrode, a ferroelectric layer and an upper electrode layer.
- the vapor deposition process is normally effected at temperatures ranging from about 300-800°C in an oxygen containing ambient. Accordingly, in order to obviate oxidation of the plug, typically silicon or tungsten, during the processing, an oxygen barrier layer may be deposited as an intermediate between the bottom electrode of the stack capacitor and the plug 14.
- Fig. lb shows the structure of Fig. la after the deposition thereon of barrier layer 17. Absent this barrier layer, oxidation may occur which could cause interruption of the electrical connection between the bottom electrode and the drain. Additionally, the barrier layer tends to preclude diffusion of atoms from the electrode or the ferroelectric material into the plug. Also shown in Fig.
- lb is bottom electrode 18 of the capacitor, typically comprising a noble metal selected from among platinum, palladium, rhodium, gold and ruthenium, a conductive metal oxide selected from among ruthenium oxide, osmium oxide, rhenium oxide, rhodium oxide, iridium oxide, or mixed metal oxides such as LSCO, YBCO and metal nitrides such as titanium nitride or zirconium nitride.
- a noble metal selected from among platinum, palladium, rhodium, gold and ruthenium
- a conductive metal oxide selected from among ruthenium oxide, osmium oxide, rhenium oxide, rhodium oxide, iridium oxide, or mixed metal oxides such as LSCO, YBCO and metal nitrides such as titanium nitride or zirconium nitride.
- a metal oxide film is effected.
- This end may be attained in accordance with any of the known techniques for the deposition of metal oxide thin films on the bottom electrode.
- the noble metal bottom electrode is pretreated to effect either roughening or chemical modification.
- Roughening the surface of the bottom electrode may be effected, as for example, by reactive ion etching, inert ion milling and chemical mechanical polishing or the use of seed layers, all of which are suitable techniques for delineating patterned bottom electrodes.
- a typical procedure for attaining this end would involve placing a substrate member bearing the desired noble metal electrode in an R f sputter tool (13.56MHz) and evacuating the chamber to attain a pressure of about 5mtorr.
- a bias of about 400V is applied and at about 100 W R f power an etching rate of the order of 5nm/minute will be attained to effect etching and roughening.
- a bottom electrode so treated has a higher density of nucleation sites on the surface so treated which will enhance the incorporation efficiency of the metal deposition.
- Another technique for effecting roughening of the noble metal bottom electrode involves the use of a partially reactive adhesion barrier layer, such as titanium, under the noble metal (for example about 2-30 ⁇ m of titanium under 100 ⁇ m of platinum) , by using thicker layers of noble metal, for example about 300 ⁇ m and by depositing the noble metal at ambient temperatures, (for example about 25°C) .
- a partially reactive adhesion barrier layer such as titanium
- Other noble metal deposition parameters such as deposition rate, voltage and gas pressure in a sputter deposition process, deposition temperature or deposition ambient will influence the stress and microstructure of the noble metal and make it susceptible in various degrees to roughening either during pre-deposition annealing or in the early stages of SBT deposition.
- pre-deposition annealing the degree of roughening will be dependent upon various factors such as annealing time, annealing temperature, deposition conditions of the electrode, the metal chosen for the electrode, and the structure of the electrode, for example, platinum/titanium or platinum only.
- pre-annealing as employed herein is intended to define any extended holding time on the substrate heating longer than the time required to heat the substrate to the desired temperature.
- pre-annealing also is intended to encompass those case wherein additional heating of the substrate is effected after deposition of the bottom electrode but prior to chemical vapor deposition but for the time period required to bring the substrate to the required temperature for chemical vapor deposition.
- surface chemical properties of the noble metal may be modified by formation of noble metal alloys using one of several techniques in combination, such as alloy deposition, deposition of seed layers which are then either partially or completely in-diffused or ion implantation which also may be modified by heat treatments.
- a titanium or bismuth layer may be deposited on the noble metal layer.
- a preferred alloy for this purpose comprises 90%, by weight platinum, remainder iridium, a composition which is one of the most chemically resistant alloys. Additionally, the presence of iridium provides thermal stability at high temperatures and decreases oxygen diffusion through the platinum electrode during processing in strongly oxidizing ambients and enhances the reactivity of the precursors at the surface, so resulting in enhanced precursor reactivity at the surface with accompanying enhanced nucleation and incorporation efficiencies .
- Chemical pretreatment of the surface has also been found to influence the metal nucleation density. This end may be attained by altering the chemical reactivity of the bismuth precursor on the modified growth surface by means of a chemical pretreatment to enhance the number density of hydroxyl groups or to reduce the presence of hydrophobic species on the surface.
- This pre-treatment step and the accompany surface modification may be implemented with reactive plasmas, ion beams or gas phase chemistry to enhance uniform nucleation and film growth of SBT.
- the gas phase chemistry alluded to may be implemented by admixing of hydrogen with the oxides before the chemical vapor deposition begins. The reaction of the hydrogen with oxygen will yield water which will or may result in the presence of oh groups on the surface. Alternatively, having an alcohol present in the beginning of the processing sequence will also result in the formation of water or catalytically cleave to generate OH groups. Thus, for example, methyl alcohol and platinum will yield a methyl group and a hydroxyl group on the surface of the platinum.
- a still further technique for modifying the noble metal surface is by treatment with chemicals in liquid solutions, as for example, dissolved salts, dissolved complex compounds and organic or inorganic compounds within or without solution.
- the surface is charged either by roughening with an etching solution (HC1 + HN0 3 ) or by cleaning or by depositing metal ions or metal clusters (deposition of noble metals from solution) , or by changing the type of adsorbed molecules in order to create more nucleation sites.
- a uniform high density of nucleation sites for metals may also be attained by modifying the deposition conditions during nucleation in the beginning of the CVD process. These parameters include deposition rate, pressure, gas flow, gas composition, temperature and the oxidizing-reducing environment during nucleation of the SBT films by altering the amount of oxidizers present or the amount of reducing agents present. Typical oxidizers employed for this purpose are 0 2/ N 2 0, 0 3 , H 2 0 2 , N0 2 etc. H 2 , NH 3 , and CO are typical reducing agents for this purpose. This two stage process involving nucleation and then growth is also found to be successful in obtaining a high number of nucleation sites. Finally, the presence of plasmas either at the deposition surface or remote from the surface may be used to control this parameter because a plasma will force the precursor combustion, thereby creating nuclei.
- the bottom electrode so treated has a large number of nucleation sites which will enhance the nucleation of metal oxides during the deposition.
- the base substrate offers a small number of absorption sites and is not catalytically active under the chemical vapor deposition conditions.
- Typical materials found useful for this purpose are silicon dioxide, silicon nitride and certain metal oxides which are non-conducting oxides such as tantalum pentoxide and strontium titanium oxide (SrTi0 3 ) .
- Deposition of the desired materials may be effected in a conventional chemical vapor deposition apparatus, as for example, a warm wall reactor.
- the substrates are placed in the reaction chamber which is then sealed and the system evacuated to a pressure ranging from 0.1 to 10 torr.
- the substrate member is then heated to a temperature ranging from about 400-700°C with a gas flow ranging from about 500-10000 seem.
- Chemical precursors which are suitable for the chemical vapor deposition of SrBi 2 Ta 2 0 9 are bismuth triphenyl Bi(Ph) 3 , Sr(thd) 2 - tetraglyme and Ta (O-i-Pr) (thd) dissolved in tetrahydrofuran, isopropyl alcohol and tetragylme (THF: IPA: tetraglyme) .
- THF IPA: tetraglyme
- a suitable volume ratio for the solvent components in the THF: IPA: tetraglyme solvent composition may be an 8:2:1 volume ratio.
- Precursor solutions are mixed prior to deposition and flash evaporated upon a matrix. Typical vaporizer temperatures range from about 200-250°C.
- a preferred temperature for this step is about 210°C.
- the precursor vapor is then transported at a flow rate ranging from about 50-600 seem and preferably within the range of about 200 to 400 seem by a suitable carrier gas, such as argon, to the reaction chamber.
- the liquid delivery rate should range from about 0.05 to 1 ml per minute with a preferred range of about 0.07 to 0.25 ml per minute.
- At the inlet of the chamber it is mixed further with argon and oxygen. Coating of the substrate is then effected. Shown in Fig. Id is the structure of Fig.
- SBT metal oxide ferroelectric
- strontium tantalate layer 20 on top of the surrounding insulating material which is silicon dioxide or silicon nitride.
- the resultant structure is subjected to a high temperature anneal in the presence of oxygen to transform the as-deposited phase to the ferroelectric Aurivillius phase.
- the temperature of the anneal is about 600-820°C, preferably about 750-800°C.
- a top electrode 20a typically a noble metal electrode, is deposited upon the structure shown in Fig. Id to yield the structure shown in Fig. le.
- a further high temperature anneal is effected in the presence of oxygen at a temperature that may be different from or the same as the temperature of the first anneal step.
- This top electrode will then serve as the common plate for all capacitors.
- the substrates were chemically equivalent and included a lOOnm thickness of platinum on silicon dioxide on silicon.
- the solvent employed was tetrahydrofurane/isopropanol/tetraglyme in a volume ratio of 8:2:1.
- the concentrations of the precursors in this solvent system were: 0.15 M Sr source, 0.4 M Ta source and 0.4 M Bi source.
- Each of the precursor solutions was stored separately and mixed prior to deposition. Following, the mixture of precursors was flash evaporated upon a matrix at a vaporization temperature of about 205°C with a liquid delivery rate ranging from about 0.05 to 0.2 ml/min. The vaporized precursors were then transported by an argon carrier gas to the reaction chamber. At the inlet of the chamber, the precursor stream was mixed further with argon and oxygen.
- the CVD reactor was a warm walled reactor (T wa n is about 200°C) comprising a quartz tube having a diameter of 12.5 cm.
- substrate 1 roughened significantly more than substrate 2 in the time before deposition while the wafer heated up in an oxygen ambient.
- the root mean squared (RMS) roughness of each substrate after about 5 minutes in an oxygen ambient at about 620°C was about 11.1 nm for substrate 1 and about 1.7 nm for substrate 2 as measured by atomic force microscopy.
- Deposition conditions for both SBT films were about: 1 torr total pressure 620°C substrate temperature 900 seem total gas flow 50% 02 precursor ratios: 10.5% Sr, 81.6% Bi, 7.9% Ta 30 minutes deposition time
- the substrate in each case was arranged perpendicular to the gas flow. Following the deposition of the film, the precursor delivery was stopped and the resultant structure permitted to cool in the argon/oxygen stream.
- the resulting films evidenced composition and thickness as set forth in Table I, below:
- the method of the present invention may be employed to deposit Bi 2 0 3 only in those areas in which it is needed to form a ferroelectric SBT phase, for example, on top of a bottom electrode with a high degree of reproducibility at the appropriate composition and a homogeneous morphology.
- the method of the invention is usefully carried out so that the insulating material that surrounds the bottom electrode is not covered with Bi 2 0 3 but instead is covered only with SrO and Ta 2 0 5 .
- the significance of this finding is as follows: First, Bi 2 0 3 is known to react with Si0 2 to form bismuth silicates. Thus, if TEOS-Si0 2 is present beside the bottom electrode it would be transformed into a silicate. This would affect the stress in the entire wafer and increase the likelihood of the silicate density being different from that of TEOS-Si0 2 . Additionally, such a change in density might be accompanied by void formation.
Abstract
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Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98963041A EP1042528B1 (en) | 1997-12-23 | 1998-12-10 | Method for deposition of ferroelectric thin films |
DE69813888T DE69813888T2 (en) | 1997-12-23 | 1998-12-10 | METHOD FOR APPLYING FERROELECTRIC THIN LAYERS |
KR1020007007063A KR20010033554A (en) | 1997-12-23 | 1998-12-10 | Method for deposition of ferroelectric thin films |
JP2000525597A JP2001527281A (en) | 1997-12-23 | 1998-12-10 | Method for depositing ferroelectric thin film |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/996,574 US6010744A (en) | 1997-12-23 | 1997-12-23 | Method for nucleation controlled chemical vapor deposition of metal oxide ferroelectric thin films |
US08/996,574 | 1997-12-23 |
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WO1999032684A1 true WO1999032684A1 (en) | 1999-07-01 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/US1998/026258 WO1999032684A1 (en) | 1997-12-23 | 1998-12-10 | Method for deposition of ferroelectric thin films |
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US (1) | US6010744A (en) |
EP (1) | EP1042528B1 (en) |
JP (1) | JP2001527281A (en) |
KR (1) | KR20010033554A (en) |
DE (1) | DE69813888T2 (en) |
TW (1) | TW482827B (en) |
WO (1) | WO1999032684A1 (en) |
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EP1143501A1 (en) * | 1998-12-16 | 2001-10-10 | Tokyo Electron Limited | Method of forming thin film |
US7118726B2 (en) | 2002-12-13 | 2006-10-10 | Clark Manufacturing, Llc | Method for making oxide compounds |
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US10100409B2 (en) | 2015-02-11 | 2018-10-16 | United Technologies Corporation | Isothermal warm wall CVD reactor |
JP6467239B2 (en) * | 2015-02-16 | 2019-02-06 | 東京エレクトロン株式会社 | Ruthenium film forming method, film forming apparatus, and semiconductor device manufacturing method |
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- 1998-12-10 KR KR1020007007063A patent/KR20010033554A/en not_active Application Discontinuation
- 1998-12-10 EP EP98963041A patent/EP1042528B1/en not_active Expired - Lifetime
- 1998-12-10 JP JP2000525597A patent/JP2001527281A/en not_active Withdrawn
- 1998-12-10 WO PCT/US1998/026258 patent/WO1999032684A1/en not_active Application Discontinuation
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EP0732422A2 (en) * | 1995-03-08 | 1996-09-18 | Sharp Kabushiki Kaisha | Ferroelectric thin-film coated substrate, method for its manufacture and nonvolatile memory comprising such a substrate |
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Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
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EP1143501A1 (en) * | 1998-12-16 | 2001-10-10 | Tokyo Electron Limited | Method of forming thin film |
EP1143501A4 (en) * | 1998-12-16 | 2005-02-02 | Tokyo Electron Ltd | Method of forming thin film |
EP1077478A2 (en) * | 1999-08-18 | 2001-02-21 | Matsushita Electronics Corporation | Method of making ferroelectric thin film, ferroelectric capacitor, ferroelectric memory and method for fabricating ferroelectric memory |
EP1077478A3 (en) * | 1999-08-18 | 2004-02-04 | Matsushita Electric Industrial Co., Ltd. | Method of making ferroelectric thin film, ferroelectric capacitor, ferroelectric memory and method for fabricating ferroelectric memory |
US7220598B1 (en) | 1999-08-18 | 2007-05-22 | Matsushita Electric Industrial Co., Ltd. | Method of making ferroelectric thin film having a randomly oriented layer and spherical crystal conductor structure |
US7118726B2 (en) | 2002-12-13 | 2006-10-10 | Clark Manufacturing, Llc | Method for making oxide compounds |
US11430512B2 (en) * | 2020-06-29 | 2022-08-30 | Taiwan Semiconductor Manufacturing Company Limited | Semiconducting metal oxide memory device using hydrogen-mediated threshold voltage modulation and methods for forming the same |
Also Published As
Publication number | Publication date |
---|---|
US6010744A (en) | 2000-01-04 |
JP2001527281A (en) | 2001-12-25 |
DE69813888T2 (en) | 2004-01-29 |
EP1042528A1 (en) | 2000-10-11 |
EP1042528B1 (en) | 2003-04-23 |
DE69813888D1 (en) | 2003-05-28 |
TW482827B (en) | 2002-04-11 |
KR20010033554A (en) | 2001-04-25 |
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