WO1999028806A3 - Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio - Google Patents
Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio Download PDFInfo
- Publication number
- WO1999028806A3 WO1999028806A3 PCT/US1998/023773 US9823773W WO9928806A3 WO 1999028806 A3 WO1999028806 A3 WO 1999028806A3 US 9823773 W US9823773 W US 9823773W WO 9928806 A3 WO9928806 A3 WO 9928806A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- clock
- signal
- propagating
- frequency ratio
- synchronous clock
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU13884/99A AU1388499A (en) | 1997-12-04 | 1998-11-09 | Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio |
DE19882870T DE19882870C2 (en) | 1997-12-04 | 1998-11-09 | Method and device for forwarding a signal between synchronous clock domains operating at a non-integer frequency ratio |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/985,390 US6049887A (en) | 1997-12-04 | 1997-12-04 | Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio |
US08/985,390 | 1997-12-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1999028806A2 WO1999028806A2 (en) | 1999-06-10 |
WO1999028806A3 true WO1999028806A3 (en) | 1999-08-26 |
Family
ID=25531437
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/023773 WO1999028806A2 (en) | 1997-12-04 | 1998-11-09 | Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio |
Country Status (5)
Country | Link |
---|---|
US (1) | US6049887A (en) |
AU (1) | AU1388499A (en) |
DE (1) | DE19882870C2 (en) |
TW (1) | TW459172B (en) |
WO (1) | WO1999028806A2 (en) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7363401B1 (en) * | 1997-12-15 | 2008-04-22 | Intel Corporation | Method and apparatus for controlling bus transactions depending on bus clock frequency |
US6535565B1 (en) * | 1999-03-16 | 2003-03-18 | Level One Communications, Inc. | Receiver rate converter phase calculation apparatus and method |
US6516362B1 (en) * | 1999-08-23 | 2003-02-04 | Advanced Micro Devices, Inc. | Synchronizing data between differing clock domains |
US7007187B1 (en) * | 2000-06-30 | 2006-02-28 | Intel Corporation | Method and apparatus for an integrated circuit having flexible-ratio frequency domain cross-overs |
US7333516B1 (en) * | 2000-07-20 | 2008-02-19 | Silicon Graphics, Inc. | Interface for synchronous data transfer between domains clocked at different frequencies |
US6748039B1 (en) * | 2000-08-11 | 2004-06-08 | Advanced Micro Devices, Inc. | System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system |
US6377096B1 (en) * | 2000-10-24 | 2002-04-23 | Hewlett-Packard Company | Static to dynamic logic interface circuit |
US6792554B2 (en) * | 2000-12-11 | 2004-09-14 | International Business Machines Corporation | Method and system for synchronously transferring data between clock domains sourced by the same clock |
DE10121165B4 (en) | 2001-04-30 | 2011-02-03 | Qimonda Ag | Method and apparatus for initializing an asynchronous latch chain |
DE10122702C2 (en) | 2001-05-10 | 2003-08-21 | Infineon Technologies Ag | Method and device for generating a second signal with a clock based on a second clock from a first signal with a first clock |
US6766396B2 (en) * | 2001-06-07 | 2004-07-20 | Lucent Technologies Inc. | PC16550D UART line status register data ready bit filter and latch |
US7296174B2 (en) * | 2002-10-11 | 2007-11-13 | Broadcom Corporation | Apparatus and method to interface two different clock domains |
US7107393B1 (en) | 2003-03-28 | 2006-09-12 | Xilinx, Inc. | Systems and method for transferring data asynchronously between clock domains |
US7310396B1 (en) | 2003-03-28 | 2007-12-18 | Xilinx, Inc. | Asynchronous FIFO buffer for synchronizing data transfers between clock domains |
US6987404B2 (en) * | 2003-10-10 | 2006-01-17 | Via Technologies, Inc. | Synchronizer apparatus for synchronizing data from one clock domain to another clock domain |
US7515666B2 (en) * | 2005-07-29 | 2009-04-07 | International Business Machines Corporation | Method for dynamically changing the frequency of clock signals |
US7451338B2 (en) * | 2005-09-30 | 2008-11-11 | Intel Corporation | Clock domain crossing |
US7936789B2 (en) * | 2006-03-31 | 2011-05-03 | Intel Corporation | Disparate clock domain synchronization |
US8001409B2 (en) * | 2007-05-18 | 2011-08-16 | Globalfoundries Inc. | Synchronization device and methods thereof |
JP2009044489A (en) * | 2007-08-09 | 2009-02-26 | Panasonic Corp | Asynchronous absorption circuit with transfer performance optimizing function |
US7733130B2 (en) * | 2008-03-06 | 2010-06-08 | Oracle America, Inc. | Skew tolerant communication between ratioed synchronous clocks |
US8089378B1 (en) * | 2009-02-18 | 2012-01-03 | Marvell Israel (M.I.S.L) Ltd. | Synchronous multi-clock protocol converter |
US8498373B2 (en) * | 2011-09-20 | 2013-07-30 | Arm Limited | Generating a regularly synchronised count value |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5448715A (en) * | 1992-07-29 | 1995-09-05 | Hewlett-Packard Company | Dual clock domain interface between CPU and memory bus |
US5777942A (en) * | 1992-11-06 | 1998-07-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof |
Family Cites Families (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07114074B2 (en) * | 1985-12-18 | 1995-12-06 | 株式会社日立製作所 | Semiconductor memory device |
US4935894A (en) * | 1987-08-31 | 1990-06-19 | Motorola, Inc. | Multi-processor, multi-bus system with bus interface comprising FIFO register stocks for receiving and transmitting data and control information |
DE69125652T2 (en) * | 1990-06-05 | 1997-09-11 | Hitachi Maxell | Non-contact IC record carrier |
US5588152A (en) * | 1990-11-13 | 1996-12-24 | International Business Machines Corporation | Advanced parallel processor including advanced support hardware |
US5471587A (en) * | 1992-09-30 | 1995-11-28 | Intel Corporation | Fractional speed bus coupling |
US5535377A (en) * | 1994-01-31 | 1996-07-09 | Dell Usa, L.P. | Method and apparatus for low latency synchronization of signals having different clock speeds |
US5600824A (en) * | 1994-02-04 | 1997-02-04 | Hewlett-Packard Company | Clock generating means for generating bus clock and chip clock synchronously having frequency ratio of N-1/N responsive to synchronization signal for inhibiting data transfer |
US5654988A (en) * | 1995-09-29 | 1997-08-05 | Intel Corporation | Apparatus for generating a pulse clock signal for a multiple-stage synchronizer |
US5768550A (en) * | 1995-11-21 | 1998-06-16 | International Business Machines Corporation | Bus interface logic system |
US5905766A (en) * | 1996-03-29 | 1999-05-18 | Fore Systems, Inc. | Synchronizer, method and system for transferring data |
-
1997
- 1997-12-04 US US08/985,390 patent/US6049887A/en not_active Expired - Lifetime
-
1998
- 1998-11-09 WO PCT/US1998/023773 patent/WO1999028806A2/en active Application Filing
- 1998-11-09 AU AU13884/99A patent/AU1388499A/en not_active Abandoned
- 1998-11-09 DE DE19882870T patent/DE19882870C2/en not_active Expired - Fee Related
- 1998-12-04 TW TW087120196A patent/TW459172B/en not_active IP Right Cessation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5448715A (en) * | 1992-07-29 | 1995-09-05 | Hewlett-Packard Company | Dual clock domain interface between CPU and memory bus |
US5777942A (en) * | 1992-11-06 | 1998-07-07 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device including dynamic type memory and static type memory formed on the common chip and an operating method thereof |
Also Published As
Publication number | Publication date |
---|---|
DE19882870C2 (en) | 2003-09-25 |
WO1999028806A2 (en) | 1999-06-10 |
TW459172B (en) | 2001-10-11 |
AU1388499A (en) | 1999-06-16 |
DE19882870T1 (en) | 2001-06-21 |
US6049887A (en) | 2000-04-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO1999028806A3 (en) | Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio | |
EP0969350A3 (en) | Clock switching circuit | |
EP0822663A3 (en) | Separate set/reset paths for time critical signals | |
EP0763885A3 (en) | Modulator and frequency multiplier for use therein | |
MY113477A (en) | Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a p/q integer ratio relationship | |
AU1082099A (en) | Method and apparatus for coupling signals between two circuits operating in different clock domains | |
KR950009450A (en) | Data Synchronization System and Method | |
WO2002023715A3 (en) | Digital clock skew detection and phase alignment | |
DE3468568D1 (en) | Apparatus for recording and/or reproducing digital information signals | |
EP0898284A3 (en) | Semiconductor memory having a test circuit | |
WO2000065457A3 (en) | A method and apparatus for source synchronous transfers at frequencies including an odd fraction of a core frequency | |
EP0360691A3 (en) | Apparatus for receiving digital signal | |
WO1999022456A3 (en) | Arrangement and method relating to radio communication | |
ATE140349T1 (en) | DEMODULATOR FOR RADIO DATA SIGNALS | |
WO2001047122A3 (en) | Apparatus for selectively disabling clock distribution | |
AUPM587094A0 (en) | Microwave loop oscillators | |
WO2002069495A3 (en) | Circuit and method for generating a varying frequency clock signal | |
TW359823B (en) | Clocking scheme | |
JPS57203213A (en) | Clock signal reproducing circuit | |
TW362173B (en) | Meta-hardened flip-flop | |
ATE71785T1 (en) | COUPLING FIELD FOR DIGITAL AUDIO SIGNALS. | |
GB2366169A (en) | A method and an arrangement for preventing metastability | |
EP0610052A3 (en) | Method and apparatus for timing control. | |
EP0808022A3 (en) | Latch circuit operating in synchronization with clock signals | |
KR960043535A (en) | Method and apparatus for generating a multi-phase shift clock using a set of minimum-phase crosstalk signals |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AL AM AT AT AU AZ BA BB BG BR BY CA CH CN CU CZ CZ DE DE DK DK EE EE ES FI FI GB GD GE GH GM HR HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SK SL TJ TM TR TT UA UG US UZ VN YU ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): AL AM AT AT AU AZ BA BB BG BR BY CA CH CN CU CZ CZ DE DE DK DK EE EE ES FI FI GB GD GE GH GM HR HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SK SL TJ TM TR TT UA UG US UZ VN YU ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
NENP | Non-entry into the national phase |
Ref country code: KR |
|
122 | Ep: pct application non-entry in european phase | ||
NENP | Non-entry into the national phase |
Ref country code: CA |
|
RET | De translation (de og part 6b) |
Ref document number: 19882870 Country of ref document: DE Date of ref document: 20010621 |
|
WWE | Wipo information: entry into national phase |
Ref document number: 19882870 Country of ref document: DE |