WO1999024908A1

WO1999024908A1 - Electrical precharge of device drivers being connected to a data bus

Info

Publication number: WO1999024908A1
Application number: PCT/US1998/024075
Authority: WO
Inventors: Richard Uber
Original assignee: Quantum Corporation
Priority date: 1997-11-12
Filing date: 1998-11-12
Publication date: 1999-05-20

Abstract

An electrical precharge circuit precharges distributed capacitance of an integrated circuit device incident to being connected to a signal line of a data bus. A progressive connection array supplies power to the integrated circuit before connecting to the bus signal line. A logical control level from an on-board power supply monitor sources percharge current to the distributed capacitance appearing at an internal signal path. After the supply level monitored by the on-board power supply monitor has reached a predetermined level the precharge current source is switched off. The internal signal path of the integrated circuit device is then connected to the signal line. A reverse flow blocking diode prevents back flow from signal line of the data bus through the current source when power is removed from the integrated circuit while remaining connected to the bus. A precharge circuit for precharging dual differential signal lines is also described.

Description

ELECTRICAL PRECHARGE OF DEVICE DRIVERS BEING CONNECTED TO A DATA BUS

Field of the Invention

The present invention relates to the field of digital data transmission lines and related driver circuits. More particularly, the present invention is related to method and apparatus for electrically precharging devices being hot-connected to a digital data bus.

Background of the Invention

Buses are used to interconnect components and elements of digital computing systems. A bus is a collection of wires in a cable or conductive traces on a printed circuit board, or other signaling medium or paths, such as optical fiber paths, which transmit data, status, and control signals. A bus may also typically supply operating power and ground return paths via electrical conductors. A bus between physically separate computing systems is frequently referred to as a network.

Standard buses and bus structures have become widespread in digital computing. One family of bus structures is known as Small Computer System Interface, or "SCSI". The SCSI bus structure has become standardized, as specified by document S3.131-1986 published by the American National Standards Institute in June, 1986. This bus enabled e.g. eight computer CPUs and peripherals to be interconnected, and provided a defined physical interconnect and a signaling construct enabling exchange of data between interconnecting computing/storage subsystems, etc.

One recent improvement to SCSI has been the low voltage differential bus structure. This bus structure includes a pair of signal paths or wires for each logical signal, and each path has a signaling range of only approximately 400 millivolts, e.g. 1.1 volts to 1.5 volts. Two differential signal lines can hold two binary states. The voltages (1.5v, l.lv) represent one state while the voltages (l.lv, 1.5v) represent the opposite binary state. While the voltages in this example are not absolute, it is a characteristic of such systems that the voltage difference between the two lines (0.4v) is much smaller than the average voltage on the two lines (1.3v). This very narrow signaling range presents certain unique design requirements and challenges for interface circuits supporting connection to this bus structure. Most existing SCSI systems use a single bus path for signaling instead of differential pairs. In such a "single-ended" system, a voltage of greater than 1.9 volt represents one binary logic state while a voltage level of less than 1.1 volt represents the other binary logic state.

The SCSI interface has become particularly favored by designers of file servers (such as redundant array of inexpensive disks or "RAID"). Because file servers are typically required to be on-line at all times, it has become necessary to provide for live or "hot" connect and disconnect of individual storage devices, such as disk drives and tape drives to and from the bus structure. One prior approach has been to provide connector structures which enable progressive connection of ground, power and signal pins. One example of a known connector structure is SCA-2 which employs connector pins of graduated lengths, thereby assuring that the ground connection will precede the power supply connection, and that the power supply connections will precede connections to the signal conductors and paths.

Despite the progressive connection afforded by these connector structures, problems have remained in providing hot connect of devices to certain bus structures, such as the SCSI single-ended bus. and particularly, the low voltage differential SCSI bus. These problems lie in the fact that the driver circuits of the interface integrated circuit of the device being hot connected present a distributed capacitance at the signal pins. This capacitance is initially at zero volts. When an interface signal pin is connected to the bus, the distributed capacitance at the interface signal pin has the effect of applying a downward surge current spike to the bus.

Fig. 1A illustrates this problem schematically for a single-ended bus. A single- ended bus structure 10 includes a defined plurality of conductive lines, including e.g. a power line (VDD), a ground line and a signal line 12. The bus 10 interconnects a computer host interface 14 with a plurality of devices. Peripheral devices 16 and 18 are shown connected to the bus 10 in the Fig. 1 example. The peripheral devices 16 and 18 may be computer storage devices, such as magnetic or optical disk drives, and/or tape drives. The bus 10 may implement a standard bus specification, such as single-ended SCSI.

The signal line 12 is nominally maintained at a logical false level by virtue of a termination resistor R which leads to a termination power supply NT- A third peripheral device 20, includes an output inverter comprising CMOS FET transistors Ql (n-channel) and Q3 (p-channel) and an output pull down driver transistor Q2 (n-channel). An interconnect structure 24. comprising a pin array 24P and a matching receptacle array 24R, enables the device 20 to be interconnected to the bus 10. Specifically, the driver transistor Q2 connects to the signal line 12 via the interconnect structure 24.

At the moment of hot-interconnect of device 20 to signal line 12, a signal level on an incoming path 26 to inverter Q1-Q3 is logically low, and the pull down driver transistor Q2 is floating at a high impedance. Nevertheless, a distributed parasitic capacitance Cp (depicted in Fig. 1 in dashed outline as being in parallel with pull down transistor Q2) is charged to a zero voltage level. At this moment of hot-interconnect, the distributed capacitor Cp presents a low impedance to the bus signal line 12 and begins to charge toward the signal level (e.g. a level of 1.9 to 2.96 volts). A surge charging current flows into the capacitor Cp from line 12. This charging current is sourced at least by current flow from the termination power supply VT through the termination resistor RT and results in the presence of a momentary negative current spike on the line 12. The negative current spike can corrupt data at the moment of interconnect, as already noted above.

Fig. 2 presents a similar situation associated with a low voltage differential bus. A low voltage differential bus 10' includes a power line VDD, a ground, and two differential signal lines 12-1 and 12-2. The bus 10' interconnects a computer host interface 14' with a plurality of devices, such as peripherals 16' and 18' which may be computer storage devices (tape, or optical/magnetic disk drives). The bus 10' may implement a standard bus specification, such as low voltage differential SCSI.

In this differential bus arrangement 10', a termination resistor network comprises e.g. three termination resistors, RT-1, RT-2 and RT-3. Resistor RT-1 connects from signal line 12-1 to a first termination voltage supply VI. Resistor RT-2 connects from signal line 12-2 to a second termination voltage supply V2. Resistor RT-3 connects directly across signal lines 12-1 and 12-2. The consequence of this arrangement is to bias the differential lines 12-1 and 12-2 to a logical false state.

Peripheral device 20' supports differential signal lines 12-1 and 12-2 via an interconnect structure 24' similar to the interconnect 24 of Fig. 1. The positive supply line VDD supplies driving current to a current source 23, and a current sink 25 sinks current to the ground return path. A single-ended logical assert control path 26 controls two driver transistors Q4 and Q5. Q4 sources current from the current source 23 to differential line 12-2, while Q5 sinks current from line 12-1 through the current sink 25 to ground. A single-ended logical negate control path 28 controls two other driver transistors Q6 and Q7. When the negate line 28 is true, transistor Q6 sources current from the current source 23 to the differential line 12-1, and transistor Q7 sinks current from the line 12-2 through current sink 25 to ground.

As in the situation with the conventional single-ended bus 10 shown in Fig. 1 , the differential bus peripheral 20' presents distributed capacitance at both signal lines 12-1 and 12-2. Accordingly, when the peripheral 20' is hot-connected to the differential bus 10', surge charging currents flow via e.g. the termination resistor network RT-1, RT-2 and RT-3 and results in the presence of momentary current spikes on the differential lines 12- 1 and 12-2. If, for example, the bus path 12-1 or 12-2 with the higher voltage (e.g. 1.5v) were subjected to a downward surge current, the voltage on said bus path may briefly fall below that of the bus path which serves as its differential pair (e.g. l.lv). This brief signal reversal can be propagated along the bus 10' and be recognized by the other devices 16' and 18' on the bus 10', resulting in data corruption. This momentary surge current may have the unwanted effect of corrupting data being transferred over the bus 10' between other elements at the moment of hot connect.

While the desirability of eliminating transient disturbances to the signal line 12, such as the momentary surge current, would be understood and appreciated by those skilled in the art, heretofore there has been no satisfactory practical solution to remove this particular unwanted signal artifact.

Summary of the Invention

A general object of the present invention is to provide an electrical precharge circuit for precharging signal lines of an integrated circuit being connected to a signal bus in order to remove and minimize transient signal level disturbances in a manner overcoming limitations and drawbacks of prior approaches.

Another object of the present invention is to use a control level of an onboard power monitor circuit of an integrated circuit for controlling an electrical precharge circuit in a manner which provides effective electrical precharge of IC signal lines being connected to a bus with minimum circuitry and at minimal additional cost in IC circuit design or complexity.

In accordance with principles of the present invention, an electrical precharge circuit is provided for precharging distributed capacitance of an integrated circuit device being connected to a signal line of a data bus. In this arrangement the integrated circuit includes a connection array for supplying power to the integrated circuit before electrically connecting to the bus signal line. Accordingly, the precharge circuit uses a logical control level from an on-board power supply monitor to momentarily source precharge current to charge a distributed parasitic circuit capacitance appearing at an internal signal path to be connected to the bus signal line through a current source controlled by the logical control level. After the supply level monitored by the on-board power supply monitor has reached a predetermined level, such as 60% of the nominal operating supply level, the precharge current source is switched off. The internal signal path of the integrated circuit device then connects to the signal line. A reverse flow blocking diode prevents back flow from signal line of the data bus through the current source when power is removed from the integrated circuit and it remains connected to the bus. The diode element may be implemented within a diode-connected MOSFET.

Thus, in one embodiment the electrical precharge circuit includes an integrated circuit supply monitoring circuit for monitoring a power supply level of the integrated circuit and for putting out a control having a first logical condition below a predetermined power supply level and a second logical condition above the predetermined power supply level; a current source switched by the control for sourcing an electrical precharge current from a power source during an interval represented by the first logical condition, and for ceasing to source electrical precharge current from the power source during an interval represented by the second logical condition; and a reverse flow blocking diode connected in series between the current source and the signal line for blocking current flow from the signal line to the current source.

Preferably, the control of the integrated circuit supply monitoring circuit puts out a logical low or false as the first logical condition and puts out a logical high or true as the second logical condition.

Preferably, in one example, the current source comprises a P-channel FET having a source electrode connected to an internal voltage supply rail of the integrated circuit and a drain connected to the reverse flow blocking diode, and has its control electrode connected to the control of the supply monitoring circuitry.

An advantage of the current source circuitry described herein is that it will work well on either a single-ended bus or a differential bus. This advantage is important because the SCSI device may be hot-inserted into either class of bus, and the bus type cannot be known or ascertained prior to hot-insertion. The single-ended signal line may include a remote pull-up termination resistor and termination power supply for normally biasing the signal line at a false logic level as specified by the single-ended Small Computer System Interface (SCSI) JUS specification, for example. In this example the integrated circuit device is included within a computer peripheral data storage device which is hot-connected to the single-ended SCSI bus.

A progressive connector array is preferably provided for progressively making ground, power supply and signal connections between the computer peripheral data storage device and e.g. a low voltage differential SCSI bus. Alternately, the pair of differential signal lines may include remote termination circuitry which establishes a resistive connection between the pair of bus paths, and other circuitry to establish a negation state on the bus pair whenever the bus is permitted to float.

The integrated circuit device may preferably include a pull down NFET transistor output driver connected to the signal line, and a CMOS PFET and NFET pair in tandem and connected to form an inverter at an input of the pull down NFET transistor output driver. Alternately, the integrated circuit device may include MOSFET switches for coupling current sources and current sinks to the differential bus pair.

These and other objects, aspects, advantages and features of the present invention will become more completely understood and appreciated by considering the following detailed description of a preferred embodiment which is presented in conjunction with the accompanying drawings.

Brief Description of the Drawings

In the Drawings:

Fig. 1 is a schematic diagram of a conventional single-ended network bus including a host computer interface and a plurality of computer peripheral devices, with one of the devices being hot-connected to a signal line of the network bus and causing momentary signal disturbances on the bus signal line.

Fig. 2 is a schematic diagram of a conventional differential network bus including a host computer interface and a plurality of computer peripheral devices, with one of the devices being hot-connected to two differential signal lines of the network bus and causing momentary signal disturbances on the bus signal lines. Fig. 3 is a schematic diagram showing an electrical precharge circuit for precharging the signal line of a computer peripheral device to be hot-connected to a signal line of a single^:ended network of the Fig. 1 type, incorporating and illustrating principles of the present invention.

Fig. 4 is a schematic diagram showing an electrical precharge circuit for precharging differential signal lines of a computer peripheral device to be hot-connected to differential signal lines of a differential network of the Fig. 2 type, also incorporating and illustrating principles of the present invention.

Detailed Description of Preferred Embodiments

With reference to Fig. 3, in accordance with principles of the present invention a circuit 50 provides a momentary electrical precharge to the single-ended bus signal line 22 to overcome the drawbacks and limitations noted above in connection with the Fig. 1 example. Fig. 3 should be read in light of the disclosure and description of Fig. 1, with like elements bearing the same reference designators. Also, some of the elements shown to be present in Fig. 1 are omitted in Fig. 3 to save drawing room.

The precharge circuit 50 includes a power monitor circuit 52, a PFET Q8 and a blocking diode element Dl. The power monitor circuit 52 is conventionally provided within the peripheral interface IC 20 and functions to monitor the internal voltage level on the supply rail VQD- When power is first applied to the peripheral chip 20, the power monitor puts out a logical low signal on a control line 54. The logical low control signal remains low until a predetermined voltage level is reached on the supply rail VDD, such as e.g. 60% of the nominal voltage supply level. At that point the logical low control level switches to a logical high level, and the control on the line 54 remains high so long as the supply voltage remains above the switching level (e.g. 60% of the nominal supply voltage). Among other circuits within the interface 20, the control line 54 extends to a control element of PFET Q8. PFET Q8 is connected to the positive supply rail VDD and through diode blocking element Dl to the single-ended signal line 22.

When power is first applied to the peripheral chip 20, as by hot connect at the connector array 24, the control level on power monitor control line 54 is logical low, and this low condition biases PFET Q8 into conduction (following connection of the positive supply rail VDD which powers the chip 20 including monitor circuit 52. Current is accordingly sourced through PFET Q4 and blocking diode Dl to charge the parasitic capacitor CP toward the VDD level. The voltage level across this parasitic capacitance quickly rises to approach the VDD level (less junction voltage drops across PFET Q8 and diode Dl).

The power-first, progressive connection arrangement of connector array 24 means that the electrical precharge surge current flows into the parasitic capacitor CP before the signal line 22 comes into contact with a signal receptacle of the connector array 24. This progressive connection arrangement of array 24 is diagrammed in Fig. 3. During hot connection of the peripheral device 20 to the bus 10, a receptacle 24R receives pins of a mating connector pin header 24P. Ground pins 60 are longest and make contact with respective ground receptacles before any other pins become connected, thereby establishing an initial ground connection between the peripheral 20 and the bus structure 10. Next, the power supply pins 62 make contact with respective power supply receptacles. Lastly, signal pins 64 connected to chip signal lines 22 (which are shortest) make contact with receptacles of signal lines 12.

The diode blocking element Dl effectively isolates the precharge PFET Q8 from the signal bus 12, so that power is never drawn from the bus 10. Thus, when the chip power level rises above the power monitor switch point, and the PFET Q8 is biased off, the diode blocking element Dl prevents reverse bias flow through the drain-source elements of Q8. Other elements of peripheral 20 which are connected to a signal line 12, such as pull down FET Q2, include blocking elements, such as protection diodes, to preclude unwanted leakage current flows during chip power down conditions, when the chip remains connected to the bus structure 10.

Turning now to the differential embodiment of Fig. 4, a precharge circuit 50' is provided for the differential interface circuit 20' shown in Fig. 2 and already discussed above. The precharge circuit 50' includes a power monitor 52 and two PFETs Q9 and Q10 which connect through diodes D2 and D3, respectively, to differential signal lines 12-1 and 12-2. Operation of the PFETs Q9 and Q10 is the same as the operation of PFET Q8 discussed above in connection with the Fig. 3 embodiment. During hot-connect of the device including differential interface 20' to the bus 10', power is first supplied to the power monitor circuit 52. A logical low control level on path 54 causes PFETs Q9 and Q10 to conduct and source current through diodes D2 and D3 to internal differential signal lines 22-1 and 22-2 before they become progressively connected to bus differential signal lines 12-1 and 12-2 via progressive-connection connector 24'. The resultant precharge currents quickly precharge internal lines 22-1 and 22-2 toward the VDD level. Precharge continues until the internal supply voltage line reaches a predetermined fraction of nominal value, such as 60%. At this point, the control signal on line 54 becomes true, turning off the PFET transistors Q9 and Q10. The diodes D2 and D3 prevent discharge flow in the same manner as diode Dl of the Fig. 3 embodiment.

Having thus described embodiments of the invention, it will now be appreciated that the objects of the invention have been fully achieved, and it will be understood by those skilled in the art that many changes in construction and widely differing embodiments and applications of the invention will suggest themselves without departing from the spirit and scope of the invention. For example, while PFETs Q8, Q9 and Q10 are presently preferred as precharge current sources, other circuit elements and arrangements may be employed to precharge the parasitic capacitance CP. Accordingly, the disclosures and descriptions herein are purely illustrative and are not intended to be in any sense limiting.

Claims

What is claimed is:

1. An electrical precharge circuit for precharging at least one signal line manifesting distributed capacitance within an interface circuit being connected to a data bus, the interface circuit including connection means for supplying power from a power supply to circuit elements of the interface circuit before electrically connecting the signal line to a signal path of the data bus, the precharge circuit comprising:

power supply monitoring circuitry for monitoring a power supply level of the power being supplied to the interface circuit and for putting out a control having a first logical condition when level of the power is below a predetermined power level and having a second logical condition when level of the power is above the predetermined power level,

at least one current source switched by the control for sourcing an electrical precharge current from the power supply during an interval represented by the first logical condition, and for ceasing to source electrical precharge current from the power source during an interval represented by the second logical condition, and

at least one reverse flow blocking means connected in series between the current source and the signal line for blocking current flow from the signal line to the current source.

2. The electrical precharge circuit set forth in claim 1 wherein the interface circuit comprises an integrated circuit chip and a progressive connector for progressively connecting power and then the signal path of the data bus to the integrated circuit chip during a hot-connect operation.

3. The electrical precharge circuit set forth in claim 2 wherein the data bus is a single-ended data bus.

4. The electrical precharge circuit set forth in claim 1 wherein the control of the power supply monitoring circuitry puts out a logical false condition as the first logical condition and puts out a logical true condition as the second logical condition.

5. The electrical precharge circuit set forth in claim 3 wherein said current source comprises a P-channel FET having a source electrode connected to an internal voltage supply rail of the integrated circuit and a drain and having a control electrode connected to the control of the supply monitoring circuitry, and wherein said reverse flow blocking means comprises a diode connected between the drain and the signal line.

6. The electrical precharge circuit set forth in claim 3 wherein the signal path includes a remote pull-up termination resistor and termination power supply for normally biasing the signal path at a false logic level.

7. The electrical precharge circuit set forth in claim 6 wherein the data bus comprises a single-ended Small Computer System Interface (SCSI) bus.

8. The electrical precharge circuit set forth in claim 7 wherein the integrated circuit device is included within a computer peripheral data storage device which is hot- connected to the single-ended SCSI bus.

9. The electrical precharge circuit set forth in claim 1 wherein the connection means comprises a progressive connector array for progressively making ground and power supply connections to the circuit before making signal connections between the signal path and the signal line.

10. The electrical precharge circuit set forth in claim 3 wherein the integrated circuit device includes a pull down NFET transistor output driver connected to the signal line, and a CMOS PFET and NFET connected as an inverter at an input of the pull down NFET transistor output driver.

11. The electrical precharge circuit set forth in claim 1 wherein the data bus comprises a differential bus having two differential signal paths and having remote pull- up termination resistors and termination power supplies for normally biasing the two differential signal paths to a false logic condition, wherein the interface circuit includes two differential signal lines manifesting distributed capacitance within an interface circuit, two current sources controlled by the power supply monitoring circuitry, and two reverse flow blocking means connected between the two current sources and the two differential signal lines.

12. The electrical precharge circuit set forth in claim 11 wherein the interface circuit comprises an integrated circuit chip and a progressive connector for progressively connecting power and then the differential signal paths of the data bus to the integrated circuit chip during a hot-connect operation.

13. The electrical precharge circuit set forth in claim 12 wherein each said current source comprises a P-channel FET having a source electrode connected to an internal voltage supply ^"rail of the integrated circuit and a drain and having a control electrode connected to the control of the supply monitoring circuitry, and wherein each said reverse flow blocking means comprises a diode connected between the drain of a said P-channel FET and a said signal line.

14. The electrical precharge circuit set forth in claim 11 wherein the differential signal paths include a remote pull-up termination resistor network and termination power supplies for normally biasing the differential signal paths at a false logic level.

15. The electrical precharge circuit set forth in claim 13 wherein the data bus comprises a low voltage differential Small Computer System Interface (SCSI) bus.

16. The electrical precharge circuit set forth in claim 15 wherein the integrated circuit device is included within a computer peripheral data storage device which is hot- connected to the low voltage differential SCSI bus.

17. The electrical precharge circuit set forth in claim 11 wherein the connection means comprises a progressive connector array for progressively making ground and power supply connections to the circuit before making signal connections between the differential signal paths and the differential signal lines.

18. The electrical precharge circuit set forth in claim 13 wherein the integrated circuit device includes a pair of pull down NFET transistor output drivers connected between the differential signal lines and a current sink, and a pair of pull up NFET transistor output drivers connected between a current source and the differential signal lines.

19. An electrical precharge circuit for precharging at least one signal line manifesting distributed capacitance within an interface circuit being connected to a data bus, the interface circuit including connection means for supplying power from a power supply to circuit elements of the interface circuit before electrically connection the signal line to a signal path of the data bus, the precharge circuit comprising:

a plurality of current sources switched by the control, at least one of the plurality of current sources for sourcing an electrical precharge current from the power supply during an interval represented by the first logical condition, and for ceasing to source electrical precharge current from the power source during an interval represented by the second logical condition, and

a plurality of reverse flow blocking means connected in series with the plurality of current sources, at least one of the plurality of reverse flow blocking means being in series with the signal line for blocking current flow from the signal line to the current source.

20. The electrical precharge circuit set forth in claim 19 wherein the electrical precharge circuit precharges a plurality of signal lines, wherein each one of the plurality of current sources and an associated one of the reverse flow blocking means is connected to one of the plurality of signal lines.