WO1999021326A2

WO1999021326A2 - Resource optimization in a multiprocessor system for a packet network

Info

Publication number: WO1999021326A2
Application number: PCT/FI1998/000816
Authority: WO
Inventors: Jari Korhonen; Jyri Suvanen; Matti LEHTIMÄKI
Original assignee: Nokia Networks Oy
Priority date: 1997-10-21
Filing date: 1998-10-20
Publication date: 1999-04-29
Also published as: WO1999021326A3; AU9543998A; FI974020A0

Abstract

A method, an arrangement and an SAR circuit for serving several packet switched telecommunication connections (CA to CE) by several processors (PROC1 to PROCn). One processor is selected from among several processors (PROC1 to PROCn) for each telecommunication connection (CA to CE) to be served. On each telecommunication connection (CA to CE) information is transmitted in packets from which are formed elements (A to E) of at least one queue (Q1 to Qn). A separate queue (Q1 to Qn) is formed for each telecommunication connection (CA to CE) to be served. The SAR circuit conveys only queue elements (A to E) formed from the packets of the respective telecommunication connection (CA to CE) via each queue to a corresponding processor (PROC1 to PROCn).

Description

RESOURCE OPTIMIZATION IN A MULTIPROCESSOR SYSTEM FOR A PACKET

NETWORK

BACKGROUND OF THE INVENTION

The invention relates to serving packet switched connections, pref- erably ATM connections, in a multiprocessor system, and particularly to optimizing resource allocation in such a system. The invention further relates to an SAR circuit employed in such a system.

With reference to Figure 1 , in a packet switched network information is transmitted in packets comprising at least a header part and a payload part. In an ATM network, for example, the length of the packets is 53 bytes. A five- byte header indicates with which connection the packet in question is associated. For the sake of simplicity, Figure 1 shows five connections C_A to C_E. A terminal using ATM connections is typically a workstation, a personal computer or the like wherein one efficient processor PROC1 processes the ATM connections. The ATM terminal equipment comprises an SAR circuit (Segmentation And Re-assembly) SAR which receives ATM packets and writes them to a queue Q1 located in a memory, from which queue the processor retrieves them on a first in, first out principle (FIFO).

If more than one processor are needed in the terminal equipment, the allocation of resources between the different processors presents a problem. In accordance with a potential solution, one common SAR circuit shared by all processors serves all processors sharing a common queue. In this solution the elements of the queue are formed in an unarranged manner from packets which belong to all C_A to C_E. The processors spend much time searching the queue Q1 only for elements which belong to them. Furthermore, to write to a shared queue would be difficult for the processors. If, on the other hand, there are as many queues as there are processors but the SAR circuit is still a shared one, the processors still waste their time searching the unarranged queues only for elements which belong to them. If a specific SAR cir- cuit is reserved for each processor, the queues could be arranged in such a manner that only elements which belong to the respective processor are written to the queue of each processor. The problem in this solution is, however, that it requires a great number of SAR circuits, and it is still unclear how the system should be configured in case some processors serve more than one connection at a time. This is not extremely harmful in terminal equipment with a light processing load associated with a single connection, since the processors can perform the required arranging (for example by simply selecting only packets which belong to the connection to be served and discarding others). In net- work elements performing complex signal processing, such as speech encoding devices, echo cancellers, compression or decompression devices, etc. the situation is different. One processor (typically a digital signal processor DSP) can usually serve a few connections at the most and often only one connection at a time. The processors spend much time arranging the queues ac- cording to which connection they serve at a given time.

BRIEF DESCRIPTION OF THE INVENTION

An object of the invention is thus to provide a method and equipment implementing the method so as to solve the above problems. More specifically, the object of the invention is to enable resources to be more efficiently utilized in a multiprocessor system which serves several connections. The objects of the invention can be achieved by a method, an arrangement and an SAR circuit characterized by what is said in the independent claims. The preferred embodiments of the invention are disclosed in the dependent claims.

The invention is based on the idea of forming a separate queue for each telecommunication connection to be served in a memory space of an SAR circuit, and conveying to each queue substantially only queue elements formed from packets which belong to the respective telecommunication connection. In this connection, "substantially only" means that only queue elements formed from packets of a corresponding telecommunication connection (but not of other connections) are transmitted via each queue. Furthermore, processor configuration instructions and status information may be transmitted via the queue. In the present invention, this configuring means that the processor is informed at which memory address the queues associated with the connections and served by it can be found. Most preferably, all queues and processors share a common SAR circuit. Each queue can in practice be implemented as a ring buffer pair or a linked list. The SAR circuit places in each queue only packets which belong to the connection corresponding to it. If a processor serves several connections, the processor also processes several queues. An advantage of the method and the system of the invention is that the processors do not have to spend much time arranging the queues, and the equipment becomes readily scalable for large numbers of connections and processors. Avoiding redundant processing also reduces power consumption. The memory capacity required by the queues is reduced since no need exists to store in any queue packets which will not be processed. In accordance with a preferred embodiment, a shared SAR circuit is fitted for several processors, which reduces the number of components and the price of the system. The invention thus enables several processors to be connected behind a shared SAR circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention is now described in closer detail in connection with the preferred embodiments with reference to the accompanying drawings, in which Figure 1 shows how several connections are served by one processor in accordance with prior art, and

Figure 2 shows how several connections are served by several processors in accordance with the invention.

DETAILED DESCRIPTION OF THE INVENTION Let us first take a simple case in which packets A to E which belong to connections C_A to C_E can be processed as such. An example of such a situation is a speech frame of the GSM system, whose length is about 85% of the length of the payload of an ATM cell.

With reference to Figure 2, a shared SAR circuit arranges packets which belong to all connections C_A to C_E into queues Q1 to Q2 on the basis of their header in such a manner that a separate queue is formed in the memory space of the SAR circuit for each connection C_A to C_E. The SAR circuit places in each queue Q1 to Qn only packets which belong to a corresponding connection C_A to C_E. The queues Q1 to Qn can be provided in a shared physical memory. A problem is then presented, however, by collisions caused by several processors simultaneously writing in the same memory. Even if the queue of each processor was located in a separate storage area, the processor would be compelled to use the same data and/or address bus simultaneously. It is thus more preferable to implement a separate physical queue for each processor. In accordance with a preferred embodiment, in order to save mem- ory only the payload parts of the packets are stored in the queues Q1 to Qn and the packet header parts are reformed when the packet is transmitted to the network after processing. Since the length of the packet is a fixed one in this example, the queues Q1 to Qn can be simple ring buffer pairs in which the writing element (the SAR circuit or the processor) maintains the write address of a next location, rewrites the packet to this address and increments the write address. The reading element (the processor or the SAR circuit, correspondingly) reads the packet from the read address of the location to be read next and increments this address. When the write or the read address is incre- mented beyond the maximum address of the ring buffer, it is returned to the minimum address.

A situation in which the same processor serves several connections (in this case C_B and C_c) is shown in connection with a second processor of Figure 2. The processor PROC2 reads from and writes to two queues Q2τ and Q2₂. A separate queue is provided for each connection C_A to C_E, however.

Let us next discuss a more complex case in which the packets A to E which belong to the connections C_Ato C_E do not as such constitute appropriate packets to be processed. Such a situation is, for example, a half-speed speech frame of the GSM system, two of which fit in one ATM cell. On such a connection, the SAR circuit can be configured to divide the payload of one ATM cell into two packets to a corresponding queue Q1 to Qn. Similarly, if the length of the packet to be processed is a fixed multiple of the payload of the ATM cell, the SAR circuit can be configured to form each packet of the queue from the payload part of several ATM cells. In all the cases described above the queues Q1 to Qn can be implemented as ring buffers, for example.

However, if variable length packets produced by many video codecs, for example, are transmitted via the ATM network, a simple ring buffer is not sufficient but the queues can be formed as linked lists, for example, in which each element refers to the beginning of a next element. It is obvious to those skilled in the art that with progress in technology the basic ideas of the invention can be implemented in various ways. The invention and its embodiments are thus not restricted to the examples described above, but they can vary within the scope of the claims.

Claims

1. A method of serving several packet switched telecommunication connections (C_A to C_E) by several processors (PROC1 to PROCn), in which method one of several processors (PROC1 to PROCn) is selected to serve each connection (C_A to C_E) to be served, on each telecommunication connection (C_A to C_E) information is transmitted in packets from which are formed elements (A to E) of at least one queue (Q1 to Qn) and which elements are conveyed via said queue to said selected processor (PROC1 to PROCn), characterized in that a separate queue (Q1 to Qn) is formed for each telecommunication connection (C_A to C_E) to be served, and to each queue substantially only queue elements (A to E) formed from packets of the respective telecommuni- cation connection (C_A to C_E) are conveyed.

2. A method as claimed in claim 1, characterized in that said telecommunication connection packets comprise a header part and a payload part and the elements (A to E) of said queues (Q1 to Qn) are formed from a fixed number of payload parts of the packets.

3. A method as claimed in claim 2, characterized in that the queues (Q1 to Qn) are formed as pairs of ring buffers, one ring buffer comprising elements (A to E) applied to the processor and the other ring buffer comprising elements (A to E) supplied from the processor.

4. A method as claimed in claim 1, characterized in that said telecommunication connection packets comprise a header part and a payload part, and the elements (A to E) of said queues (Q1 to Qn) are formed from a variable number of payload parts of the packets.

5. A method as claimed in claim 4, characterized in that the queues (Q1 to Qn) are formed as pairs of linked lists, one list comprising packets (A to E) or their payload parts applied to the processor, and the other list comprising packets (A to E) or their payload parts supplied from the processor.

6. An arrangement for serving several telecommunication connections (C_A to C_E) by several processors (PROC1 to PROCn), which arrange- ment comprises connection means (I/O) for connecting to a telecommunications network (ATM) in which information is transmitted in packets, means for selecting one processor from among several processors (PROC1 to PROCn) to serve each said telecommunication connection (C_A to C_E), and at least one queue (Q1 to Qn), segmentation means (SAR) operationally connected to said connection means (I/O) for forming queue elements (A to E) from said packets and conveying the elements (A to E) via said queue (Q1 to Qn) to the processor (PROC1 to PROC2) selected to serve the respective communication con- nection (C_A to C_E) and vice versa, c h a r a c t e r i z e d in that the arrangement is arranged to form a separate queue (Q1 to Qn) for each telecommunication connection (C_A to C_E) to be served and to convey to each queue (Q1 to Qn) substantially only queue elements (A to E) formed from the packets of the respective telecommunica- tion connection (C_A to C_E),

7. An arrangement as claimed in claim 6, c h a r a c t e r i z e d in that said packets are ATM frames and said segmentation means comprise a common SAR circuit (SAR) shared by all queues and processors.

8. A segmentation circuit and a re-assembly circuit, i.e. an SAR cir- cuit, of a packet switched telecommunications network, particularly of an ATM network, which circuit is arranged to read packets which belong to the different connections (C_A to C_E) of said telecommunications network, and to form from the packets elements (A to E) of at least one queue (Q1 ), c h a r a c t e r i z e d in that the SAR circuit is arranged to connect to several queues (Q1 to Qn) of which one is provided for each telecommunication connection (C_A to C_E) to be served, and to place in each queue (Q1 to Qn) substantially only queue elements (A to E) formed from the packets of the respective telecommunication connection (C_A to C_E).