WO1999012111A1 - A method of designing fpgas for dynamically reconfigurable computing - Google Patents
A method of designing fpgas for dynamically reconfigurable computing Download PDFInfo
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- WO1999012111A1 WO1999012111A1 PCT/US1998/016436 US9816436W WO9912111A1 WO 1999012111 A1 WO1999012111 A1 WO 1999012111A1 US 9816436 W US9816436 W US 9816436W WO 9912111 A1 WO9912111 A1 WO 9912111A1
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- fpga
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
Definitions
- the present invention relates generally to the field of field programmable gate arrays (FPGAs) and more particularly to a method of configuring an FPGA using a host processor and a high level language compiler.
- FPGAs field programmable gate arrays
- the second major approach is compilation of standard programming languages to reconfigurable logic coprocessors. These approaches typically attempt to detect computationally intensive portions of code and map them to the coprocessor. These compilation tools, however, are usually tied to traditional placement and routing back-ends and have relatively slow compilation times. They also provide little or no run-time support for dynamic reconfiguration. In general, today's tools are based on static circuit design tools originally developed for use in circuit board and integrated circuit design. The full potential of dynamic logic is not supported by such static design tools.
- the method of design for reconfigurable computing (MDRC) of the invention represents a novel approach to hardware/software co-design for reconfigurable logic based coprocessors .
- a system and method are provided for configuring an FPGA directly from a host processor. It is not necessary to store the configuration data in a file, although it can be so stored if desired. Therefore, this method is particularly suited for use with FPGAs such as reconfigurable coprocessors, which are often reconfigured "on the fly", i.e., without repowering the FPGA and sometimes while reconfiguring only a portion of the FPGA.
- a description of the desired functionality for the FPGA is entered using the MDRC libraries and a standard high level language such as JavaTM (Java is a trademark of Sun Microsystems, Inc.). Configuration, reconfiguration and host interface software for reconfigurable coprocessors is supported in a single piece of code. Since MDRC does not make use of the traditional placement and routing approach to circuit synthesis, compilation times are significantly shorter than with prior art methods, being on the order of seconds. This high-speed compilation provides a development environment which closely resembles those used for modern software development. The MDRC provides a simple alternative to traditional Computer Aided Design (CAD) tool based design. In the preferred embodiment, Java libraries are used to program an FPGA device. This method has the following benefits: Very fast compilation times .
- This feature has uses in areas such as adaptive filtering.
- Object Oriented Hardware Design Because Java is an object oriented language (i.e., a structured language in which elements are described in terms of objects and the connections between these objects) , hardware designed in this language can make use of object-oriented support. Libraries constructed with MDRC may be packaged as objects and manipulated and reused like any standard software component. Support for dynamic reconfiguration. The ability to dynamically configure a circuit automatically brings with it the ability to do dynamic reconfiguration. Uses for this capability are beginning to appear. For example, a portion of a dynamically reconfigurable FPGA could be configured as a multiplier that multiplies an input value by a constant, the constant being a scaling factor in a signal processing application.
- MDRC requires a host processor to be available for executing the Java code and supplying configuration data to the FPGA. This processor/FPGA combination is a powerful coprocessing environment currently being investigated by researchers . One barrier to use of these systems is the need to interface the FPGA hardware design with the host software design. MDRC merges the software and hardware design activities into a single activity, eliminating these interfacing issues. Flexibility. Because MDRC comprises a library used by a standard programming language, it may be extended, even by users . This capability provides a level of flexibility unavailable in a static design tool. Users are free to provide new libraries and library elements, or even accessories such as custom graphical user interfaces . Standard device interface .
- MDRC One way to think of MDRC is not so much as a tool in itself, but as a standard interface to the FPGA device. This interface may be used for FPGA configuration, or it may be used to build other tools. MDRC may even be used as the basis for traditional CAD software such as placement and routing tools. Another way to think of MDRC is as the "assembly language" of the FPGA. Guaranteed "safe" circuits. MDRC provides an abstraction (a software construct that provides a representation, often simplified, of the hardware) which makes it impossible to produce circuits with contention problems. This makes it impossible when using MDRC to accidentally damage or destroy the device due to a bad configuration. Such protection is highly desirable in a dynamic programming environment like MDRC, where a programming error could otherwise result in permanently damaged hardware. (An incorrectly configured FPGA may inadvertently short power and ground together, destroying the device.) A side effect of this feature is that the MDRC may be used as an implementation vehicle for the emerging field of genetic algorithms.
- Figure 1 is a block diagram illustrating the prior art design flow for design of a circuit implemented in an FPGA using a reconfigurable logic coprocessor.
- Figure 2 is a block diagram illustrating the design flow in the present invention.
- Figure 3 is a diagram of a level 1 logic cell abstraction of the present invention.
- Figure 3A is a diagram of an XC6200 logic cell represented by the abstraction of Figure 3.
- Figure 4 is a diagram of a multi-bit counter according to one embodiment of the invention.
- Figure 5 is an element definition code listing for the basic elements of the embodiment of Figure 4.
- Figure 6A is a diagram of a toggle flip-flop cell of the embodiment of Figure 4.
- Figure 6B is a diagram of a carry logic cell of the embodiment of Figure 4.
- Figure 7 is a configuration code listing for the counter of Figure 4.
- Figure 8A is a run time code for the counter of Figure 4.
- Figure 8B is an execution trace for the counter of Figure 4.
- DETAILED DESCRIPTION OF THE DRAWINGS Design of a circuit implemented in an FPGA using a reconfigurable logic coprocessor currently requires a combination of two distinct design paths, as shown in prior art Figure 1. The first and perhaps most significant portion of the effort involves circuit design using traditional CAD tools.
- the design path for these CAD tools typically comprises entering a design 101 using a schematic editor or hardware description language (HDL) , using a netlister 102 to generate a netlist 103 for the design, importing this netlist into an FPGA placement and routing tool 104, which finally generates a bitstream file 105 of configuration data which is used to configure FPGA 106.
- the next task is to provide software to interface the host processor to the FPGA.
- the user enters user code 107 describing the user interface instructions, which is then compiled using compiler 108 to produce executable code 109.
- the instructions in executable code 109 are then used by the processor to communicate with the configured FPGA 106.
- the MDRC environment comprises a library of elements which permit logic and routing to be specified and configured in a reconfigurable logic device. By making calls to these library elements, circuits may be configured and reconfigured. Additionally, host code may be written to interact with the reconfigurable hardware. This permits all design data to reside in a single system, often in a single Java source code file.
- the MDRC approach also tightly couples the hardware and software design processes. Design parameters for both the reconfigurable hardware and the host software are shared. This coupling provides better support for the task of interfacing the logic circuits to the software. As shown in Figure 2, entering and compiling an FPGA circuit using the MDRC method requires many fewer steps than in the prior art method of Figure 1.
- User code 201 in this embodiment Java code, is entered.
- This code includes not just instructions describing the user interface and the configuration process, but also a high-level description of the desired FPGA circuit.
- This circuit description comprises calls to library elements (function calls) in MDRC libraries 202. In one embodiment, these cells can be parameterized.
- Java compiler 203 combines the circuit descriptions from MDRC libraries 202 with the instructions from user code 201 to generate executable code 204.
- Executable code 204 includes not only user interface instructions, as in executable code 109 of Figure 1, but also configuration instructions.
- the bitstream need not be stored as a file; if desired the configuration data can be directly downloaded to FPGA 106 by executable code 204. This technique is particularly useful in reconfigurable computing, i.e., when using a reconfigurable FPGA as a coprocessor to perform a series of different computations for a microprocessor.
- the MDRC Abstraction MDRC takes a layered approach to representing the reconfigurable logic. At the lowest (most detailed) layer, called Level 0, MDRC supports all accessible hardware resources in the reconfigurable logic. Extensive use of constants and other symbolic data makes Level 0 usable, in spite of the necessarily low level of abstraction.
- the current platform for the MDRC environment is the XC6200DS Development System manufactured by Xilinx, Inc. the assignee of the present invention.
- the XC6200DS Development System comprises a PCI board containing a Xilinx XC6216 FPGA.
- Level 0 support comprises abstractions for the reconfigurable logic cells and all routing switches, including the clock routing.
- Level 0 is essentially the bit-level information in the XC6200 Data Sheet coded into Java.
- the "XC6200 Data Sheet” as referenced herein comprises pages 4-251 to 4-286 of the Xilinx 1996 Data Book entitled “The Programmable Logic Data Book", published September 1996, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) While Level 0 provides complete support for configuring all aspects of the device, it is very low level and may be too tedious and require too much specialized knowledge of the architecture for most users.
- Level 0 is the "assembly language" of the MDRC system.
- Level 1 abstraction is the Level 1 abstraction. This level of abstraction permits simpler access to logic definition, clock and clear routing, and the host interface.
- the most significant portion of the Level 1 abstraction is the logic cell definition. Using the logic cell definition, one logic cell in the XC6200 device can be configured as a standard logic operator. In one embodiment, AND, NAND, OR, NOR, XOR, XNOR, BUFFER and INVERTER combinational logic elements are supported. These elements may take an optional registered output.
- FIG. 3 is a diagram of the Level 1 logic cell abstraction. Outputs Nout, Eout, Sout, Wout correspond to the outputs of the same names in the XC6200 logic cell, as pictured on page 4-256 of the XC6200 data sheet. The XC6200 logic cell is also shown in Figure 3A herein. Input Sin of Figure 3 corresponds to input S of the logic cell of Figure 3A, input Win corresponds to input W, Nin to N, and Ein to E.
- the Level 1 abstraction shown in Figure 3 is a simplified representation of the XC6200 logic block.
- inputs S4, W4, N4, and E4 are not supported in the Level 1 abstraction, although they are supported in the Level 0 abstraction.
- the Logic block and flip-flop shown in Figure 3 signify the circuits available in one XC6200 logic cell.
- Inputs A, B, and SEL in Figure 3 are the inputs to the Logic block; they can be mapped to any of logic cell inputs Sin, Win, Nin, and Ein.
- the circuits available in one logic cell differ in other FPGA devices.
- the clock routing is abstracted.
- Various global and local clock signals may be defined and associated with a given logic cell.
- a third portion of the MDRC Level 1 abstraction is the register interface. In the XC6200 device, columns of cells may be read or written via the bus interface, the columns of cells thus forming read/write registers.
- the Register interface allows registers to be constructed and accessed symbolically.
- An Example Figure 4 shows a simple counter designed for an XC6200 device, based on toggle flip-flops 402 and carry logic 401 using the Level 1 abstraction.
- the circuit is described and configured, and clocking and reading of the counter value is performed.
- the structure of this circuit permits it to be easily packaged as a parameterized object, with the number of bits in the counter being set via a user-defined parameter. Such an object-based approach would permit counters of any size to be specified and placed at any location in the XC6200 device.
- the counter of Figure 4 could also be placed in a library of parameterized macrocells.
- the implementation process is fairly simple. First, the logic elements required by the circuit are defined.
- circuit element definitions are abstractions and are not associated with any particular hardware implementation. Once these logic elements are defined, they may be written to the hardware, configuring the circuit. Once the circuit is configured, run time interfacing of the circuit, usually in the form of reading and writing registers and clocking the circuit, is performed. If the application demands it, the process may be repeated, with the hardware being reconfigured as necessary.
- the counter example contains nine basic elements. Five basic elements provide all necessary support circuitry to read, write, clock and clear the hardware. The remaining basic elements are used to define the counter circuit itself. These elements are best seen by looking at Figure 5 in conjunction with Figure 4. Figure 5 gives the MDRC code for describing the basic elements.
- the pci6200 object passed to each of the two register definitions is the hardware interface to the XC6200DS PCI board.
- the support circuitry includes two registers which simply interface the circuit to the host software. These two registers are used to read the value of the counter ("Register counterReg” in Figure 5) and to toggle a single flip-flop 404, producing the local clock (“Register clockReg” in Figure 5) . To support the flip-flops in the XC6200 device, clock and clear (reset) inputs must also be defined.
- the global clock (“ClockMux globalClock” in Figure 5) is the system clock for the device and must be used as the clock input to any writable register.
- the flip-flop which provides the software-controlled local clock must use the global clock.
- the local clock (“ClockMux localClock” in Figure 5) is the output of the software controlled clock, and must be routed to the toggle flip- flops which make up the counter.
- all flip-flops in the XC6200 device need a clear input (“ClearMux clear” in Figure 5) .
- the clear input to all flip- flops is simply set to logic zero (GND) .
- the first logic element in the counter circuit is the clock ("Logic clock” in Figure 5) . This element is just a single bit register 404 ( Figure 4) which is writable by the software. Toggling register 404 via software control produces clock Local_clock for the counter circuit.
- the next counter circuit element is a toggle flip-flop such as flip-flop 402, ("Logic tff" in Figure 5).
- This flip-flop is defined as having an input coming from the west.
- the names Logic. EAST and Ein denote an east-bound signal, i.e., a signal coming from the west.
- the toggle flip-flop element provides the state storage for the counter.
- the carry logic element 401 for the counter (“Logic carry” in Figure 5) is simply an AND-gate with inputs from the previous stage carry logic and the output of the current stage toggle flip- flop. The carry element generates the "toggle" signal for the next stage of the counter.
- Figures 6A and 6B are graphical representations of the flip-flop and carry logic cells, respectively, in an XC6200 device.
- a logical "one" or VCC cell (“Logic one” in Figure 5, block 403 in Figure 4) is implemented for the carry input to the first stage of the counter.
- Figure 7 An example of this instantiation is shown in Figure 7, which instantiates the elements for the counter of Figure 4.
- the code in Figure 7 performs all necessary configuration.
- the carry cells (401 in Figure 4) are in one column with the toggle flip-flops tff (402 in Figure 4) in the next column.
- a local clock and a clear are attached to each toggle flip-flop tff.
- the relative location of these cells is shown in Figure 4.
- a constant "1" is set as the input to the carry chain (403 in Figure 4) .
- the software-controlled clock (Local_clock in Figure 4) is configured. This is the clock object, with its localClock routing attached to the toggle flip-flops tff of the counter.
- the global clock is used to clock the software-controlled local clock.
- the clock and clear basic elements are not required; in this embodiment their presence is necessary to support the XC6200 architecture.
- the clock is toggled by alternately writing "0" and "1" to the clock register (404 in Figure 4) .
- the counter register (not shown) is used to read the value of the counter (outputs COUN [0], COUNT [1], COUNT [2], etc.).
- Figure 8B shows an actual trace of the execution of this code running on the XC6200DS development system.
- MDRC provides a simple, fast, integrated tool for reconfigurable logic based processing.
- MDRC is currently a manual tool, since it is desirable for the programmer to exercise tight control over the placement and routing of circuits for reconfigurable computing.
- MDRC provides very fast compilation times in exchange for the manual design style.
- the compile times necessary to produce these circuits and run-time support code is on the order of seconds, many orders of magnitude faster than the design cycle time of traditional CAD tools. This unusual speed permits development in an environment that is similar to a modern integrated software development environment. Additionally, the object-oriented nature of Java permits libraries of parameterized cells to be built. This feature could significantly increase the productivity of MDRC users. MDRC may be used as a basis for a traditional graphical CAD tool. This approach would be useful for producing static circuits.
- the above text describes the MDRC in the context of FPGAs used for dynamically reconfigurable computing, such as the Xilinx XC6200 family of FPGAs.
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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DE69805811T DE69805811T2 (en) | 1997-08-28 | 1998-08-07 | METHOD FOR DESIGNING FPGAS FOR DYNAMIC RECONFIGURABLE INVOICE |
EP98939275A EP1008069B1 (en) | 1997-08-28 | 1998-08-07 | A method of designing fpgas for dynamically reconfigurable computing |
JP2000509047A JP4481487B2 (en) | 1997-08-28 | 1998-08-07 | FPGA design method for dynamically reconfigurable computation |
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US08/919,531 US6078736A (en) | 1997-08-28 | 1997-08-28 | Method of designing FPGAs for dynamically reconfigurable computing |
US08/919,531 | 1997-08-28 |
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WO1999012111A1 true WO1999012111A1 (en) | 1999-03-11 |
WO1999012111B1 WO1999012111B1 (en) | 1999-04-15 |
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EP (2) | EP1008069B1 (en) |
JP (1) | JP4481487B2 (en) |
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WO (1) | WO1999012111A1 (en) |
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US6078736A (en) | 2000-06-20 |
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