WO1999012102A8 - A multiprocessing system including cluster optimization mechanisms - Google Patents

A multiprocessing system including cluster optimization mechanisms

Info

Publication number
WO1999012102A8
WO1999012102A8 PCT/US1998/018466 US9818466W WO9912102A8 WO 1999012102 A8 WO1999012102 A8 WO 1999012102A8 US 9818466 W US9818466 W US 9818466W WO 9912102 A8 WO9912102 A8 WO 9912102A8
Authority
WO
WIPO (PCT)
Prior art keywords
system interface
memory
global
entry
nodes
Prior art date
Application number
PCT/US1998/018466
Other languages
French (fr)
Other versions
WO1999012102A1 (en
Inventor
Erik Hagersten
Christopher J Jackson
William A Nesheim
Aleksandr Guzovskiy
Hien Nguyen
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Priority to AT98946854T priority Critical patent/ATE247299T1/en
Priority to JP2000509038A priority patent/JP2001515243A/en
Priority to DE69817192T priority patent/DE69817192D1/en
Priority to EP98946854A priority patent/EP1010090B1/en
Publication of WO1999012102A1 publication Critical patent/WO1999012102A1/en
Publication of WO1999012102A8 publication Critical patent/WO1999012102A8/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0712—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a virtual computing platform, e.g. logically partitioned systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G06F12/1018—Address translation using page tables, e.g. page table structures involving hashing techniques, e.g. inverted page tables
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0766—Error or fault reporting or storing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0864—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using pseudo-associative means, e.g. set-associative or hashing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/254—Distributed memory
    • G06F2212/2542—Non-uniform memory access [NUMA] architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/27—Using a specific cache architecture
    • G06F2212/272—Cache only memory architecture [COMA]

Abstract

A multiprocessing system includes a plurality of nodes interconnected through a global interconnect network which supports cluster communications. An initiating node may launch a request to a remote nodes memory. A cluster protection mechanism is advantageously employed within a system interface of the remote node. The system interface, which is coupled between the global interconnect network and a local bus of the remote node, includes a memory management unit, referred to as a cluster MMU, including a plurality of entries which are selectable on a page basis. Depending upon the particular address of a received global transaction, an entry within the memory management unit is retrieved. The entry includes various fields which may be used to protect against accesses by unauthorized nodes, and to specify the local physical address to be conveyed upon the local bus. A field of the entry is further provided to control the type operation performed upon the local bus by the system interface in response to the global interface. In one specific implementation, several different command types may be specified by the particular entry of the memory management unit, including normal memory operations, atomic test and set operations, I/O operations and interrupt operations, among others. Additional control registers may further be provided within the system interface to specify further protection parameters and/or functionality. For example, in one embodiment, a control register is provided within the system interface to store values indicative of the other nodes of the system which are allowed access to this node's local memory, a second control register which indicates on a per-address region basis whether a global transaction is a pass-through transaction, and a third control register indicating on a per-address region basis whether a global transaction is directed to a local memory region. A plurality of error status registers may further be provided.
PCT/US1998/018466 1997-09-05 1998-09-04 A multiprocessing system including cluster optimization mechanisms WO1999012102A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AT98946854T ATE247299T1 (en) 1997-09-05 1998-09-04 MULTI-PROCESSOR COMPUTER SYSTEM USING A GROUP PROTECTION MECHANISM
JP2000509038A JP2001515243A (en) 1997-09-05 1998-09-04 A multiprocessing computer system using a cluster protection mechanism.
DE69817192T DE69817192D1 (en) 1997-09-05 1998-09-04 MORE PROCESSOR COMPUTER SYSTEM USING A GROUP PROTECTION MECHANISM
EP98946854A EP1010090B1 (en) 1997-09-05 1998-09-04 Multiprocessing computer system employing a cluster protection mechanism

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US92438597A 1997-09-05 1997-09-05
US08/924,385 1997-09-05

Publications (2)

Publication Number Publication Date
WO1999012102A1 WO1999012102A1 (en) 1999-03-11
WO1999012102A8 true WO1999012102A8 (en) 1999-05-06

Family

ID=25450157

Family Applications (2)

Application Number Title Priority Date Filing Date
PCT/US1998/018469 WO1999012103A2 (en) 1997-09-05 1998-09-04 Scalable shared memory multiprocessor system
PCT/US1998/018466 WO1999012102A1 (en) 1997-09-05 1998-09-04 A multiprocessing system including cluster optimization mechanisms

Family Applications Before (1)

Application Number Title Priority Date Filing Date
PCT/US1998/018469 WO1999012103A2 (en) 1997-09-05 1998-09-04 Scalable shared memory multiprocessor system

Country Status (6)

Country Link
US (11) US6351795B1 (en)
EP (2) EP1010090B1 (en)
JP (2) JP2001515243A (en)
AT (2) ATE247299T1 (en)
DE (2) DE69817192D1 (en)
WO (2) WO1999012103A2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
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CN105765546A (en) * 2013-12-19 2016-07-13 英特尔公司 Elastic virtual multipath resource access using sequestered partitions

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