WO1999007014A1

WO1999007014A1 - Interposer/adhesive composite

Info

Publication number: WO1999007014A1
Application number: PCT/US1998/013554
Authority: WO
Inventors: Rolf W. Biernath; Eric M. Schwartz; Donelly M. Jahnke; William A. Farmer; George E. Page; James S. Mchattie
Original assignee: Minnesota Mining And Manufacturing Company
Priority date: 1997-08-01
Filing date: 1998-06-29
Publication date: 1999-02-11
Also published as: AU8657598A

Abstract

This invention concerns a composite (100) useful as a pad for integrated circuits, comprising an elastomer layer (110) having a first side and a second side, a first adhesive layer (120) attached to the first side; a second adhesive layer (130) attached to the second side; wherein the first and second adhesive layers (120, 130) are made of a different material than the elastomer layer (110).

Description

INTERPOSER/ADHESIVE COMPOSITE

Background of Invention

This invention relates generally to integrated circuit packaging, and more specifically to elastomeric pads for use in chip scale packages as spring members and planarity compensators.

The demand for a reduction in size and an increase in sophistication of electronic components has driven the industry to produce smaller and more complex integrated circuits (ICs). These same trends have forced IC packages to have smaller footprints, higher lead counts, and better electrical and thermal performance. At the same time, these IC packages are required to meet accepted reliability standards.

Ball grid array (BGA) packages were developed to meet the demand for integrated circuit packages having higher lead counts and smaller footprints. A BGA package is typically a square package with terminals, normally in the form of an array of solder balls, protruding from the bottom of the package. These terminals are designed to be mounted onto a plurality of bonding pads located on the surface of a printed circuit board (PCB) or other suitable substrate.

Recently, BGA packages have been fabricated using a tape automated bonding

(TAB) process and flexible circuitry (sometimes referred to as TAB tape or flex circuit) which typically consists of copper traces on a thin polyimide substrate. Electrically conductive leads may be laminated on one or both sides of the TAB tape.

This BGA design is commonly referred to as a Tape BGA (TBGA). In a TBGA design, the circuitry on the tape has leads which are connected to a semiconductor die through any of the conventional methods such as wire bonding, thermocompression bonding, or flip chips. If the circuitry is present on both sides of the tape, electrically conducting vias may extend through the tape from one layer of circuitry to another.

For some applications such as portable electronic components (cellular phones, disk drives, pagers, etc.) even BGA packages are sometimes too large.

Consequently, solder bumps are sometimes deposited directly onto the surface of an

IC itself and used for attachment to the PCB (commonly referred to as direct chip attach or flip chip). However, there are a number of problems associated with this approach. First, the deposition of solder balls requires a number of costly process steps. In addition, it is typically necessary to deposit a polymer underfill beneath a die to achieve acceptable reliability with flip chip attach to a PCB. This underfill is required to reduce thermal stress which is caused by the low thermal expansion of the IC die relative to the typically much higher expansion of a PCB ("thermal mismatch stress"). Deposition of this underfill is a costly process which eliminates the ability to rework the component. Consequently, if any defects are found after the underfill step, a valuable PCB must be thrown out or undergo a very costly and delicate rework procedure.

To address concerns associated with flip chip processing, another class of BGA packages have been developed. This class of BGA package may be referred to as a chip scale ball grid array or a chip scale package (CSP). Chip scale packages are so called because the total package size is similar or not much larger than the size of the IC itself. In a chip scale package, the solder ball terminals are typically disposed underneath a semiconductor die in order to reduce package size. One sample of a CSP is a product developed by TESSERA called "MICRO BGA". This product consists of a flexible circuit with a soft compliant elastomer layer (or elastomer pad) between the die and the circuit. This elastomeric member consists of polymer materials such as silicone and is typically 125 μm-175 μm (5-7 mils thick). One purpose of the elastomer is to obtain suitable reliability by minimizing thermal mismatch stress between the die and the PCB without the need for expensive underfill material. The elastomers may also serve as spring members, force spreaders, and chip attach to a flex circuit. In CSP test fixtures, the elastomers serve as spring members and planarity compensators, where initial force detention, local compliance, minimal outgassing, and proper uniformity over a wide temperature range are all important. One challenge with chip scale package designs, however, is the process for attaching the elastomer to the flex tape. One method commonly employed is screen printing a fluid polymer followed by a cure. In either case, it is difficult to meet the tight tolerances required for a CSP application. Yet another concern is package flatness. In a typical CSP design, it is critical that the package flatness (coplanarity) be less than 25 μm to ensure that all solder balls contact the PCB upon reflow. This level of flatness or coplanarity may be difficult to achieve with soft polymer and elastomer materials commonly used. Finally, if a die is not adequately isolated from other parts of a package, premature failure of solder ball joints may occur due to thermal stress generated between an assembled die and a substrate, such as a circuit board. In other CSP designs, elastomer pads have been directly laminated to a circuitry and semiconductor dies without using layers of adhesive in an effort to eliminate void formation in adhesive layers. However, these designs still may suffer from thermal stress problems and do not process sufficient rigidity for strip format processing. In particular, existing elastomer application methods require a liquid pre- polymer to be screen-printed or stenciled onto the appropriate area of the flex circuit and then cured. The resulting elastomer is not tacky or conformable to the topography of the circuit. This problem has been previously solved by screen printing a second thin coat of prepolymer over the cured coat (b-staged), resulting in a compliant, adherable surface. Subsequently, the chip is applied with heat, contact leads bonded, and encapsulant edge-coat applied and cured.

The inventors herein have observed that a number of problems plague current approaches. For instance, a large number of process steps are required, which result in associated control, yield, and cost issues. More specifically, the existing liquid stenciling process has a low yield, and is late in the fabrication process, thereby resulting in significant losses of high- value intermediate products. The low yield frequently does not manifest itself until the integrated circuit bonding stage, at which time the value of the micro-flex circuit and the integrated circuit chips are at risk. Also, the stenciled elastomer construction is not readily reworkable, thereby deeming the valuable integrated circuit and flex circuit to the scrap heap. Furthermore, there is a great likelihood that the stencil will get contaminated by residual prepolymer, which contaminates subsequently stenciled circuits. Moreover, even when the stenciling process is done perfectly (e.g., with no prepolymer transfer), there is still a substantial likelihood that low molecular weight silicones and adhesion promoters will diffuse out along the contact lead surfaces, thereby poisoning them and hindering their ability to bond well to the aluminum integrated circuit pads. Consequently, the inventors herein have recognized that a need exists for integrated circuit pads which do not suffer from the disadvantages and deficiencies discussed above.

Summary of Invention This invention in one broad respect is a composite useful as a pad for integrated circuits, comprising: an elastomer layer having a first side and a second side; a first adhesive layer attached to the first side; a second adhesive layer attached to the second side; wherein the first and second adhesive layers are made of a different material than the elastomer layer. In another broad respect, this invention is a process useful for the manufacture of an adhesive composite, comprising: laminating an elastomer pre-polymer layer between first and second adhesive layers; curing the elastomer pre-polymer to form the adhesive composite.

In yet another broad respect, this invention is a package useful in ball grid array applications, comprising: a conductive circuitry layer; a composite pad of adhesive and elastomer bonded to the circuitry layer; wherein the adhesive and elastomer are made of different materials, and wherein the composite pad has a pattern corresponding to the circuit board.

In another broad respect, this invention is a composite useful as a pad for integrated circuits, comprising: an elastomer layer having a first surface; a first adhesive layer attached to the first surface; wherein the first adhesive layer is made from a different material than the elastomer layer.

This invention possesses one or more of the following advantages or solutions to the problems and deficiencies of the prior art. For example, this invention needs the same or preferably fewer process steps than previously required. This invention provides a high yield, owing to a large process window. Also, the adhesive pad construction may be manufactured independently of the flex circuit and integrated circuit, which allows quality control of the pad prior to attachment to the flex circuit. Hence, any yield losses apply only to the pad, sparing both the integrated circuit and the flex circuit. In addition, the adhesive pad construction is easily reworkable, enabling both the valuable integrated circuit and flex circuit to be reclaimed. Advantageously, there is no stencil involved that might lead to contamination. Furthermore, the elastomer is cured, e.g., crosslinked prior to attachment to the flex circuit and the IC, thereby sparing the IC from any volatiles released during cure. The composite exhibits better adhesion and wetting than would be exhibited by an equally thick layer of monolithic elastomer alone. Likewise, the composite has substantially better die cuttability and handleability than an equally thick layer of adhesive alone. The composite construction allows the circuit adhesion and wetting to be optimized independently of the elastomer for a given system. Similarly, the compression set and spring force characteristics of the elastomer can be optimized independently of the adhesive for a given composite. Furthermore, the process disclosed herein by which the composite is made allows for very tight tolerance control, especially when compared to laminating together three independently formed layers (e.g., tolerance determine by gap in the nip region, rather than the sum of the layer tolerance).

Additionally, the adhesive pad can be pre-mounted to the flex circuit, so that a manufacturer need only attach the IC, seal with encapsulant, and cure to produce the electronic part. The invention allows for faster throughput and ease of customizability to different die sizes and positions. Also, one or more of the adhesive layers may offer vibration damping characteristics to the part. Beneficially, this invention allows the conventional multiple step additive process to be replaced by a parallel process in which quality control can be performed on the pad before it is adhered to the more costly circuit.

In summary, the composite of this invention may result in substantial cost savings and in a simple, reliable processing.

As used herein, these terms have the following meaning. The term "substantially crosslinked" means that more than 50% of the possible sites have been crosslinked.

Brief Description of the Drawings FIG. 1 shows a cross-sectional view of a three layer composite of this invention. FIG. 2 shows a representative scheme of a composite manufacturing process. FIG. 3 shows a representative scheme for the manufacture of a three layer composite of this invention.

FIG. 4 are expanded cross-sectional representations of a TBGA package utilizing conductive plugs according to the present invention. FIG. 5 shows a cross-sectional view of a CSP-type package including a two- layer flex circuit, circuits-in, and a three layer pad.

FIG. 6 shows a cross-sectional view of a CSP-type package including a two- layer flex circuit, circuits-in, and a four layer pad.

FIG. 7 shows a cross-sectional view of a CSP-type package including a two- layer flex circuit, circuits-out, and a three layer pad.

FIG. 8 shows a cross-sectional view of a CSP-type package including a two- layer flex circuit, circuits-out, and a four layer pad.

FIG. 9 shows a cross-sectional view of a CSP-type package including a three- layer flex circuit, circuits-out, and a three layer pad. FIG. 10 shows a cross-sectional view of a CSP-type package including a three- layer flex circuit, circuits-out, and a four layer pad.

FIG. 11 shows a cross-sectional view of a CSP-type package including a three-layer flex circuit, circuits-in, and a three layer pad.

FIG. 12 shows a cross-sectional view of a CSP-type package including a three- layer flex circuit, circuits-in, and a four layer pad.

FIG. 13 shows a cross-sectional view of a CSP-type package including a two- layer flex circuit, circuits-in, and a three layer segmented pad.

FIG. 14 shows a representative pattern of composite pads in the form of circular dots which may be attached to a semiconductor die and to a flex circuit. FIG. 15 shows another representative pattern of composite pads in the form of circular dots which may be attached to a semiconductor die and to a flex circuit.

Detailed Description of the Invention As discussed generally above, this invention includes a multi-layer composite comprising an interposer or elastomer layer and one or more adhesive layers. FIG. 1 shows a representative example of a three layer composite of this invention. In FIG. 1, the composite 100 includes an interposer or elastomer layer 110 sandwiched between first adhesive layer 120 and second adhesive layer 130. Interposer layer 110, a core layer, may be made from a variety of polymers that are curable by heat, pressure, or ultraviolet light. Desirable physical properties of the cured polymer include compression set resistance and sufficient unitary strength so that the composite may be cut or otherwise patterned as needed for a given application. Alternatively, the interposer layer may be a metal layer, such as a copper layer. When gold or solder bumps on the circuit are to bear an externally applied force during test and burn-in, a compression set resistant elastomer is typically needed so that the bumps do not get damaged. In the practice of this invention, it is desirable to match interposer layer materials to adhesives which adhere to the interposer layer, especially when the interposer layer is a cured elastomer. So long as the interposer exhibits adequate compression set resistance for support of gold or solder bumps of a CSP and die-cutting characteristics, the interposer would be expected to be useful in the practice of this invention.

The interposers used in the practice of this invention are generally curable elastomers. Representative examples of such curable elastomers include, but are not limited to, curable silicones, epoxy, urethane, and the like. Representative examples of commercially available epoxies include, but are not limited to, MA- 130 (approximately 47 Shore A) and MT-130 (thermally conductive) which are both available from Thermoset. Representative examples of commercially available curable silicones include, but are not limited to platinum cured vinyl silicone such as 3M 7302 Elastomer, Dow Corning #577, Dow Corning Q5 8704 and Q5 8708, 3M Press-in-Place silicone. The silicon elastomers curable at room temperature often exhibit superior performance when subjected to the environmental requirements of high performance electronic connectors. Certain silicone elastomers may exhibit good stress relaxation performance at 125°C and may remain flexible at -55°C, withstand humidity aging at 85°C and 85% relative humidity, and show minimal outgassing during a 245°C solder reflow in air. In one embodiment of this invention, the cured elastomer may have a shore A hardness of 60. Alternatively, the interposer layer may be made of metal such as a copper layer; polybutadiene such as Dolph 1109 poly butadiene; or of polyimide such as Du Pont KAPTON E polyimide.

The interposer layer, including a cured elastomer, useful in this invention may provide composites which can be die-cut, thus enabling pads to be excised and handled either individually or on a release liner. It has been found that without an interposer core, such as an elastomer core, the adhesive alone generally die-cuts poorly. The interposer layer may contain one or more fillers such as silica, metals, and thermal conductors. Likewise, the composite pad may include two or more interposer layers, each interposer layer of which may be made of the same or different material from the other layer or layers.

Adhesive layer 120 and adhesive layer 130 may be the same or different. The adhesive may be any adhesive which adheres (bonds) to a given elastomer after cure, and which adheres to an integrated circuit during normal use. While not wishing to be bound by theory, it is believed that the elastomer may form an inter-penetrating network in the adhesive. It is also believed that the elastomer may form covalent bonds to the adhesive upon cure. The adhesive may be selected from a wide variety of types. Selection of any particular adhesive is not critical to the practice of this invention. It is contemplated that, when the pad is bonded to an IC, the adhesive should be of a type which is compatible with the integrated circuit, thus being made of suitable electronics grade materials. Representative classes of adhesives which may be used in the practice of this invention include pressure sensitive adhesive (PSA), crosslinking or chemically reactive adhesive, (including UV curable, heat curable, and dual cure (UV/heat) adhesives), hot melt adhesive, B-staged thermoset adhesives, and the like. Representative examples of such adhesives include silicones such as 3M RExSi 50K/50MQ; acrylates such as isobornyl acrylate (such as viscoelastic damping isobornyl acrylate adhesives), isoctyl acrylate, and acrylates sold as 3M 300LSE, 3M 467, 3M 468, 3M 468MP, 3M 966, 3M 9460, 3M 946 IP, 3M 9482PC, and microreplicated acrylates such as 3M 413, 3M 414, and 3M A515; epoxy such as sold under the name Ablestik RP-272; fluorosilicone; fluorocarbon such as Dow 6573 and 7938; polyolefins and polyolefin blends such as Shell 9731 , a polystyrene/polyisoprene blend; phenolic butyral such as Rogers 1000; Sumitomo-3M 1572; thermoplastic polyimide such as Du Pont KJ polyimide; and Du Pont Pyralux™ butyl acrylate hotmelt adhesive. PSAs of this invention generally have low cross-link density and low hardness such as a shore A hardness of 10. The peel force for PSA has been found to tend to initially increase over time possibly due to better wetting of the adhered surface. However, even with high filler loading, PSAs generally have poor compression set characteristics, and tend to lose adhesion with increased filler loading. The adhesive may optionally include one or more fillers such as silica, metals, and thermal conductors.

The composite pad of this invention may be made of varying thickness, with the layers also varying in thickness. In practice, the type of end use for the pad will drive selection of the pad's thickness. In general, the pad may vary in thickness from 1 inch (2.54 cm) to 4/1000 inch (100 μm or 4 mils), but in some cases, may be as thin as 25-50 μm. More typically, the pad may have a thickness of from 400 μm (16 mils) down to 100 μm (4 mils) for applications where the pad is used to make a chip scale package. Likewise, the composite pad may be of a variety of sizes and shapes. In certain embodiments, the composite pad may be cut to the size of the IC. Alternatively, the composite pad may be cut into circles or other shapes and applied to the IC as two or more pads; thereafter, an encapsulant may be applied which infiltrates the voids and is subsequently allowed to cure. In addition, it is contemplated that the composite pad may be cut into a variety of other shapes, such as for example ovals, rectangles, H-shapes, and so forth, with one, two, or more of such shaped pads being applied to the circuit tape and/or integrated circuit. This alternative embodiment may be referred to as segmented pads.

FIG. 2 shows a representative process for manufacture of an elastomer/adhesive composite. In FIG. 2, rolls of adhesive 210 and 212 are unwound (with braking). The adhesive faces are pointing toward each other and are fed to nip roller 224 after passing over idler rollers 220 and 222. The elastomer pre-polymer is mixed and metered out onto adhesive layer 210. The elastomer pre-polymer collects at the nip of nip roller 224, causing a recirculating flow pattern to develop which drives out any air bubbles. As adhesive layers 210 and 212 are pulled through nip roller 224, a measured amount of elastomer pre-polymer is drawn through the nip roller 224. The gap height between the laminator rolls is used to set and control the thickness of the final product. The feed rate will vary with type of equipment and materials being used, and may be in the range from 1.5 to 2.5 meters per minute. The adhesive/elastomer pre-polymer/adhesive composite is then drawn through a heating zone for heat curable elastomers. In the embodiment depicted in FIG. 2, two heating zones 230 and 232 are utilized, for example, at 55°C and 105°C respectively and a residence time in each zone of from about 1 to 2 minutes. The multiple heating zone arrangement is optional, but may be more effective for certain elastomers, with the second heating zone being at a higher temperature to force cure toward completion, and to help drive off any volatiles from the adhesive layers. After cure, the adhesive/elastomer/adhesive composite may be slit to a desired width by slitter 240. The release liner of the adhesive may optionally be peeled off at peeler 242, with the final product being wound up to roll 246.

In FIG. 3, there is shown a process for formation of a three layer composite by knife coating. Rolls of adhesive (for example, 3M VHB 9460 adhesive) are unwound in tram with one another, adhesive faces pointing toward each other. The adhesive film layers 310 and 312 are fed through knife coater 320 having a gap set by metal shims to 400 μm for example. The two liners on the adhesive may be 100 μm (4 mils) each, to result in a final composite thickness of 200 μm (8 mils). Composite thickness is variable depending on application. The knife of the knife coater 320 was held in place using clamps to maintain gap height on rigid support 322. An elastomer pre-polymer 330 (e.g., 3M 7302H silicone) is mixed and dispensed into the gap between the adhesive film layers 310 and 312. The liners of adhesive film layers 310 and 312 may be drawn through knife coater 320, thereby drawing elastomer pre- polymer 330 there along. The resulting laminate (composite) 330 may then be allowed to cure, and optionally put on a roll.

An expanded view of the TBGA package 400 showing the vias after formation is shown in FIG. 4. As shown in FIG. 4. the TAB tape 420 has conductor layers 420b and a dielectric layer 420a adhered to the stiffener 410 through an adhesive 425. The via 460 extends through the TAB tape 420 and the adhesive layer 425. A bonding site 440a is provided, at which point a solder ball 440 may be placed. To complete the electrical connection from the solder ball 440 to the stiffener 410, a conductive plug 450 is provided in the via region 460.

FIG. 5 shows a cross-sectional view of a CSP-type package including a two- layer flex circuit made up of metal leads 501, dielectric 502, and metal traces 504. In this configuration the flex circuit may be referred to as having circuits-in (metal traces 504 directed in toward the die 509). FIG. 5 also shows solder balls 503, which have been deposited in vias 516 in the dielectric 502. The package includes a first adhesive layer 505, an interposer layer 506, and a second adhesive layer 507 which make up a three layer pad. The composite pad is bonded to the metal traces 504 of the flex circuit and the die 509 using first adhesive layer 505 and second adhesive layer 507. An encapsulant 508 (which can be made of the same material as the interposer layer 506) is also depicted in FIG. 6. The encapsulant 508 encompasses the metal leads 501 and partially surrounds the die 509.

FIG. 6 shows a cross-sectional view of a CSP-type package including a two- layer flex circuit made up of metal leads 601. dielectric 602, and metal traces 604. Solder balls 603 are deposited in vias, 616, in the dielectric 602. The package includes a first adhesive layer 605, two interposer layers 606, and 610, and a second adhesive layer 607 which together make up a four layer composite pad. The four layer composite pad is bonded to the metal traces 604 of the flex circuit and the die 609 using adhesive layers 605 and 607. In this configuration, the circuits are in toward the die 609, with the dielectric 602 being bonded to the metal traces and directed away from the die 609. An encapsulant 608 encompasses the metal leads 601 and partially surrounds the die 609.

FIG. 7 shows a cross-sectional view of a CSP-type package including a two- layer flex circuit made of metal leads 701, dielectric 702, and metal traces 704. This type of two-layer flex circuit is referred to as being circuits-out since the dielectric is closer to the die 709 than the metal traces 704. The dielectric layer 702 is bonded to an adhesive layer 705. The three layer pad depicted in FIG. 7 is made up of adhesive layer 705, interposer layer 706, and second adhesive layer 707. The second adhesive layer 707 is bonded to die 709. FIG. 7 also illustrates a solder mask 711 placed on top of the metal traces, with the solder balls 703 being deposited in vias 716 in the solder mask 711. An encapsulant 708 surrounds and seals the metal traces 704 and die 709. FIG. 8 shows a cross-sectional view of a CSP-type package including a two- layer flex circuit, circuits-out, which is composed of metal leads 801, dielectric 802, metal traces 804, and solder mask 811, with solder balls 803 being deposited in vias 816 in the solder mask 811. FIG. 8 illustrates use of a four layer pad, which comprises a first interposer layer 806 and a second interposer layer 810 between first adhesive layer 805 and second adhesive layer 807. The first and second interposer layers 806 and 810 may be the same or different. An encapsulant 808 surrounds metal leads 801 and at least partially surrounds semiconductor die 809.

FIG. 9 shows a cross-sectional view of a CSP-type package including a three- layer flex circuit, circuits-out, which is comprised of metal traces 904 which are adhesively bonded to dielectric 902 by adhesive layer 912. The solder mask 911 includes vias 916 to receive solder balls 903. The flex also includes metal leads 901 which extend from the metal traces 904 and connect to the die 909. FIG. 9 also illustrates a three-layer pad that is comprised of an interposer layer 906 that is bonded to and between first and second adhesive layers 905 and 907. The first adhesive layer 905 serves to bond the pad to dielectric 902, and the second adhesive layer 907 bonds the composite pad to the die 909. An encapsulant 908 surrounds metal leads 908 and at least partially encompasses integrated circuit 909.

FIG. 10 shows a cross-sectional view of a CSP-type package including a three- layer flex circuit, circuits-out, which is composed of dielectric layer 1002 which is bonded to metal traces 1004 by adhesive layer 1012, and solder mask 101 1. Solder mask 1011 may also be referred to as a nonconductive cover coat. Metal leads 1001 lead from the metal traces 1004 to semiconductor die 1009. FIG. 10 illustrates a four- layer pad that is composed of first and second interposer layers 1006 and 1010 that are sandwiched between first and second adhesive layers 1005 and 1007. An encapsulant 1008 surrounds and protects metal leads 1001, and at least partially encompasses semiconductor die 1009. The terms "semiconductor die," "die," and "integrated circuit" are used synonymously herein. FIG. 11 shows a cross-sectional view of a CSP-type package including a three- layer flex circuit, circuits-in, that is composed of metal traces 1104 bonded to a dielectric layer 1102 using an adhesive layer 1112. Metal leads 1101 connect the metal traces 1104 to the semiconductor die 1109. Solder balls 1103 are formed in vias 1116 of the dielectric layer 1102 and adhesive layer 1112 such that the solder balls 1103 make contact with portions of metal traces 1104. FIG. 11 also illustrates a three layer pad that is composed of an interposer layer 1 106 between first and second adhesive layers 1105 and 1107. An encapsulant seals the metal leads 1101 from the atmosphere, and partially surrounds the semiconductor die 1 109. FIG. 12 shows a cross-sectional view of a CSP-type package including a three- layer flex circuit, circuits-in, which is composed of metal traces 1204 connected to a dielectric layer 1202 using an adhesive layer 1212. Metal leads 1201 connect the metal traces 1204 to the semiconductor die 1209. Solder balls 1203 have been deposited in vias 1216 of the dielectric layer 1202 and adhesive layer 1212 such that the solder balls 1203 contact portions of metal traces 1204. FIG. 12 also depicts a four layer composite pad which is comprised of first and second interposer layers

1206 and 1210 that lay between adhesive layers 1205 and 1207. Adhesive layer 1205 serves to bond the pad to the metal traces 1204 of the flex circuit, with adhesive layer

1207 serving to join the pad to the semiconductor die 1209. An encapsulant 1208 covers the metal leads 1201, and at least partially cover the die 1209.

FIG. 13 shows a cross-sectional view of a CSP-type package including a two- layer flex circuit, circuits-in, and a three layer segmented pad. The flex circuit is composed of metal traces 1304 bonded to a dielectric layer 1302, the latter having vias 1316 which hold solder balls 1303 that contact the metal traces 1304. The flex circuit also includes metal leads 1301 which connect the metal traces 1304 to the die 1309. In the embodiment of invention illustrated in FIG. 13, multiple composite pads are employed including first and second adhesive layers 1305 and 1307, with an interposer layer 1306 being sandwiched therebetween. In the configuration depicted in FIG. 13, encapsulant 1318 has been used to fill the void spaces created by die 1309, adhesive layers 1305 and 1307 and interposer layer 1306, and metal traces 1304. The encapsulant 1318 which fills such void spaces may be the same material as the interposer layer 1306, or may be different. Encapsulant 1308 also covers metal leads 1301. Encapsulant 1308 may or may not be the same material as encapsulant 1318. While the embodiment illustrated in FIG. 13 employs a two-layer flex, circuit-in, three layer segmented pad, it should be appreciated that the pad in any of the embodiments shown in FIGS. 5-12, or as otherwise disclosed herein and equivalents thereto, may be segmented form, such as represented in FIG. 13.

It has been found that patterned pads may be less susceptible to delamination than pads which fully cover a given circuit. For example, it has been found that 750 μm to 1500 μm circular dots, underfilled with encapsulant which may be the same material as the interposer, are less prone to moisture-induced delamination. While not wishing to be bound by theory, it is believed that the interface between the adhesive and the polyimide flex tape is the most susceptible to moisture induced delamination. It is believed that patterning the composite pad effectively reduces the total amount and surface area of the adhesive. As a result, less area is available for moisture induced delamination. When patterned pads are employed, the open structure created by the patterning is filled with encapsulant by an underfill process after die attach and lead bonding.

FIG. 14 illustrates a pattern of composite pad dots (or "nubbins") 1401. In FIG. 14, the "a" depicts the distance between the center points of the circular dots 1401. The "b" refers to the diameter of the dots 1401. The "c" illustrates the distance between center points of the circular dots 1401 as measured in a direction normal to "a". The "d" refers to the end-to-end distance in one direction for a given pattern of dots, with the "e" referring to the end-to-end distance in a direction perpendicular to the "d" direction. The pattern represented in FIG. 14 may be referred to as a 3x5 arrangement (3 horizontal dots, 5 vertical dots). By way of example, the dots may have a diameter "b" of 0.75cm, an "a" value of 0.022 cm, a "c" value of 0.14 cm, a "d" value of 0.65 cm, and an "e" value of 0.35. The "d" and "e" values may correlate with the size of the integrated circuit (the semiconductor die). Each of these values may vary widely, as is discussed herein. Likewise, the arrangement of dots may vary, such as being of the following non-limiting examples: 3x4, 2x3, 2x4, and so on. In one alternative arrangement, the dots may be arranged as shown in FIG. 15 wherein the dots 1501 have a 2-1-2 pattern. This pattern can be used, for example, on circuits having a size of 0.831 cm by 0.871 cm, with the dots having a diameter of 0.152 cm. A CSP of this invention may include a composite pad of this invention placed between a semiconductor die and two piece flexible circuit tape. The circuit tape may include a patterned dielectric layer (e.g., polyimide such as DU PONT KAPTON or UBE UPILEX) and a patterned conductive layer. The conductive layer may be formed by sputtering conductive metal directly on the dielectric layer, and may be patterned with openings (or "vias") for accepting solder bumps so that the solder bumps may make electrical contact with patterned conductive layer. The vias may be any shape or size which provides sufficient electrical contact during use. The vias are typically tapered with the diameter of vias varying from 100 μm to 750 μm. However, the vias are not always tapered in shape. For example, the vias may be circular in shape, or rectangular with straight walls. The diameter of the conductive layer via may be from 50 μm to 300 μm smaller than the opening in the dielectric layer. The conductive layer typically has a thickness of between 5 μm to 50 μm, more typically from 15μm to 35μm. Conductive plugs which fill vias may be formed from a wide variety of materials, such as solder paste, conductive adhesives, conductive epoxies, and copper pastes. The dielectric layer typically has a thickness of between 25 μm to 100 μm, with from 50 μm to 75 μm being more typical. The patterned conductive layer typically has a plurality of bonding leads for making electrical connection to an integrated circuit (also commonly referred to as the "semiconductor die"). Also, leads may be formed by wire bonding to the IC. The conductive circuit layers which may be employed in the practice of this invention may vary widely, and may include flex tapes having single, double or multilayer conductive layers, single, double or multilayer dielectric layers, cover coats, wire bonds, interlead bonds, conductive layer facing the die or the ball grids, and so forth.

In the practice of this invention, a plurality of composite pads may be positioned as appropriate on a flex circuit tape (e.g., in areas defined by contact leads). A tape containing numerous pads may thus be made. Similarly, the tape may be supplied as a roll of tape. Likewise, a release liner may be employed to cover the adhesive during shipping, which is removed prior to an IC being placed on the composite pad. Such a release liner, well known in the art, functions to protect the adhesive prior to IC installation.

In general, to form a ball grid array, conductive solder balls or bumps are typically attached to flexible tape and, to make electrical contact with individual pads through vias, are patterned in the dielectric layer. Vias may be patterned in a manner complimentary with the conductive pads so that each via overlays a respective conductive pad. In general, conventional techniques and materials may be used to fabricate arrays of this invention, with the proviso that the composite of this invention is employed. For example, a carrier web may be employed such as disclosed in U.S. Patents 5,344,681 and 5,462,765.

For composite pads made from materials which are hydroscopic, it has been found that the resistance to delamination can be improved markedly by exposing the pads to a baking process prior to reflow. The baking process enables a package employing the composite pad to survive solder reflow without moisture induced delamination. In general, water is removed from the package during the bake step, which thereby reduces the amount of water available to produce the "popcorn" effect (i.e., delamination). In general, a package assembly process incorporating the bake step would include the following sequential steps: die attach; lead bonding; cover- tape application; encapsulation; cover-tape removal; solder mask application (for circuits-out designs); flux application; solder ball attach; bake step; solder reflow. A typical board-mount process would include the following sequential steps: flux application to board; bake step; solder reflow. The temperature employed during the bake step will vary on type of pad, pressure, bake time, and so forth. For instance, bake time will increase for lower temperatures and temperature will decrease under reduced pressure. When baking at standard pressure, it is desirable to employ a temperature from 125°C to l60°C.

For the 175 μm pads used in Table III below, a bake time of at least 30 minutes is desirable at a temperature of 125°C. When reduced pressure is used, the temperature may be reduced, bake time may be reduced, or both. The bake time is inversely proportional to temperature. Determining appropriate and preferable temperature, pressure, and bake time requires routine experimentation for a given pad.

The following examples are illustrative of the invention and should not be construed as limiting to the scope of the invention or claims hereto. Unless otherwise denoted, all percentages are by weight.

Example 1 - Formation of a Three Layer Composite by Knife Coating Two rolls of transfer adhesive (3M, VHB 9460) were unwound in tram with each other. The two adhesives were fed through a knife coater having a gap set by metal shims to 400 μm (two liners at 100 μm each, resulting in a final laminate thickness of 200 μm). The knife is held in place using clamps so that the gap height did not change. Elastomer pre-polymer (3M Dental Products Division 7302H silicone, 30 grams) was mixed and dispensed into the gap between the two adhesives. The liners were then pulled through the knife coater, drawing the elastomer prepolymer along with it. The resulting laminate was allowed to cure. After curing, the liner was pulled from one face of the laminate. The adhesive adhered readily to the cured silicone elastomer.

When the adhesive was placed in contact with a precured sample of the silicone elastomer, poor adhesion was observed between the silicone and adhesive. However, in accordance with this invention, when the silicone was cured with adhesive thereon, the adhesive did adhere to the silicone. While not wishing to be bound by theory, it is believed that the adhesive and silicone undergo chemical reaction during the curing step, probably by crosslinking in the case of an acrylate adhesive.

Example 2 - Formation of a Three Layer Composite by Knife Coating and of Two Layer Composite with High Glass Finish

The procedure of Example 1 was repeated, except that a clear roll of polyester film was substituted for the top roll of adhesive. After cure had taken place, the polyester film was removed, revealing a high gloss finish on the adhesive/elastomer composite. The adhesive adhered tenaciously to the silicone elastomer. Example 3 - Formation of Two Layer Composite Using Additional Pressure Sensitive Adhesive Adhesion of the silicone elastomer to other pressure sensitive adhesives was tested. Silicone pre-polymer (about 3 grams, 3M 7302H silicone) was dispersed onto the surface of adhesive. The pre-polymer was allowed to cure for approximately 15 minutes. Adhesion was then tested by attempting to remove the elastomer from the surface of the adhesive. Good adhesion corresponded to the cured silicone not being easily removed from the adhesive. The following pressure sensitive adhesives were tested: isooctyl acrylate/acrylic acid (IOA AA) adhesive; isobornyl acrylate/acrylic acid (IBA/AA) adhesive; silicone pressure sensitive adhesive on 3M #92 tape; and 3M 467, 468, and 966 pressure sensitive adhesives from 3M's ICSD division.

Example 4 - Formation of Three Layer Composite Approximately 700 feet of 75 μm 3M 7302H silicone elastomer prepolymer was coated between two layers of 50 μm each VHB 9460 adhesive using an Hirano M200L Coater to which an accessory unwind stand was mounted. A pneumatic dual cartridge gun was used to dispense the silicone elastomer prepolymer through a static mixer onto the web about 20.32 to 31.5 cm from the nip roller.

Direct coating into a nip (400 μm gap) appeared to produce the best results. Neither coating with a slot die nor with a notched bar set up appeared to produce acceptable results for the system tested due to cure of the elastomer. However, it is contemplated that these approaches may prove viable upon optimization of the pumping/mixing. Due to manual feed, the coater was run at a rate of one meter per minute. A line speed of approximately 0.6 meter per minute is expected in a commercial line. The operating parameters of the M200L apparatus was as follows: air volume, 20 and 20; nips, both open; speed, 1.68 meters per minute; meter gap, 375 μm; cure to 100,000 centipoise; made on 15.24 cm cores; unwind tension, 1.3; winder tension, 4.5; doctor blades on rolls M and C; winder and unwinder set to forward; solution hand fed; M-roll, 9 cm; and C-roll, 12 cm. Example 5 - Slitting Liner Removal of Three Layer Composite Using Rewind Slitter A three layer composite was edge trimmed (25.4 cm to 30.2 cm) using a rewind/slitter (SI AT Model 330). One liner was removed from the edge trimmed three layer composite in a separate converting step on the rewind/slitter. The web was slit at 6.8 meters per minute and the release liner was stripped at 2.3 meters per minute.

Example 6 - Die Cutting Pads of elastomer were cut by hand using a razor knife. The cut pads were then placed onto flex circuits. Integrated circuits were then placed face down onto the pressure sensitive pad and bonded by pressure to the pad and flex circuit. The leads of the flex circuits were then ultrasonically welded to the integrated circuit pads, and subsequently encapsulated in elastomer.

Example 7 - Composite Removal from Integrated Circuit and Flex Circuit An integrated circuit having a composite of this invention bonded thereon was dipped in liquid nitrogen for a short time. Adhesion of the pressure sensitive adhesive to the integrated circuit was observed to decrease, with further freezing the composite was easily pulled off the integrated circuit.

For some integrated circuits, the cryogenic temperatures may be too harsh. It is envisioned that a variety of solvents (for example acetone and methyl ethyl ketone) can be applied to swell the pressure sensitive adhesive, thereby facilitating removal of the composite from the integrated circuit.

Example 8 - Composite Pad Manufacture Using the method of either Example 1 or Example 4, additional composite pads were prepared using a variety of adhesive/interposer/adhesive combinations. Certain of the pads were evaluated to determine capacity to resist delamination (popcoraing effect) due to uptake of water by the adhesive of the pad.

The various combinations which were tested are as shown in Table I. TABLE I

In general, the combinations shown above in Table I were more resistant to delamination than the composite pad made from 3M VHB 9460/3M 7302H/3M VHB 9460.

Example 9 - Patterned Pads Various pads and shapes were made and tested in accordance with industry standard J-STD-020 October 1996. The thickness of the pads was 7 mil. The full pad patterns were cut using a flat-bed die. The dot patterns were produced using a punch and die set, and the strips and squares were cut manually with a razor knife. The results of the testing is set forth in Table II. In Table II, the lower the Level number, the better the resistance to delamination. For instance, a sample having a Level 1 test result is more resistant to moisture induced delamination that a sample having a Level 6 test result.

TABLE II

Other possible methods for producing patterns include: laser cutting; coating a patterned (microreplicated) liner; jet printing; flex-o-graphic printing; stenciling; screen printing.

Example 9 - Bake Process to Reduce Delamination A composite pad composed of 3M VHB9460/3M 7302H/3M VHB9460 was exposed to Level 3 humidity, baked under the following conditions, then exposed to solder reflow conditions. The results are shown in Table III.

TABLE III

It is believed that the same result could be accomplished by adjusting the temperature profile of the solder reflow oven so that the package is held below 160°C for a sufficient time to dry.

Claims

WHAT IS CLAIMED IS:

1. An electronic package for mounting a semiconductor device to a printed circuit board comprising: a flexible circuit including a dielectric layer having first and second sides and having a conductive trace layer disposed on the first side of said dielectric layer, said conductive trace layer establishing a plurality of elongated, free standing leads disposed around the perimeter of said dielectric layer, and a composite pad including a nonperforated interposer layer formed from a crosslinkable polymeric material and having first and second major surfaces, each major surface bearing a layer of adhesive thereon, one of said adhesive layers bonding said composite pad to said flexible circuit , wherein at least one of said adhesive layers is formed on said interposer layer prior to said interposer layer being substantially crosslinked.

2. An electronic package for mounting a semiconductor device to a printed circuit board according to claim 1 comprising: a flexible circuit including a dielectric layer having first and second sides and having a conductive trace layer disposed on the first side of said dielectric layer, said conductive trace layer establishing a plurality of elongated, free standing leads disposed around the perimeter of said dielectric layer, and a plurality of composite pads, each composite pad including a nonperforated interposer layer formed from a crosslinkable polymeric material and having first and second major surfaces, each major surface bearing a layer of adhesive thereon, one of said adhesive layers bonding each of said composite pads to said flexible circuit, wherein at least one of said adhesive layers is formed on said interposer layer prior to said interposer layer being substantially crosslinked.

3. The electronic package of claim 1 or 2, wherein the interposer layer is a silicone, an epoxy, or a urethane.

4. The electronic package of claims 1 or 2, wherein the first and second adhesives are independently a pressure sensitive adhesive, a hot melt adhesive, a thermoset adhesive, or an ultraviolet light curable adhesive.

5. The electronic package of claim 1 or 2, wherein the first and second adhesives are independently a silicone, an acrylate, an epoxy, or a fluorosilicone.

6. The electronic package of claims 1 or 2, wherein at least one of the first and second adhesive layers is selected from the group consisting of isooctylacrylate and isobornyl acrylate pressure sensitive adhesives.

7. The electronic package of claims 1 or 2 wherein said adhesive has vibration dampening properties.

8. The electronic package of claim lor 2 wherein the flexible circuit includes a plurality of vias in said dielectric layer.

9. The electronic package of claim 1 wherein said flexible circuit includes wire bonds or interlead bonds for attachment to said printed circuit board.