WO1999005724A1 - Memoire semm a grille flottante - Google Patents

Memoire semm a grille flottante Download PDF

Info

Publication number
WO1999005724A1
WO1999005724A1 PCT/US1997/013348 US9713348W WO9905724A1 WO 1999005724 A1 WO1999005724 A1 WO 1999005724A1 US 9713348 W US9713348 W US 9713348W WO 9905724 A1 WO9905724 A1 WO 9905724A1
Authority
WO
WIPO (PCT)
Prior art keywords
floating gate
nanometers
dielectric layer
gate
channel region
Prior art date
Application number
PCT/US1997/013348
Other languages
English (en)
Inventor
Stephen Y. Chou
Lingjie Guo
Effendi Leobandung
Original Assignee
Regents Of The University Of Minnesota
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Regents Of The University Of Minnesota filed Critical Regents Of The University Of Minnesota
Priority to AU38189/97A priority Critical patent/AU3818997A/en
Priority to PCT/US1997/013348 priority patent/WO1999005724A1/fr
Publication of WO1999005724A1 publication Critical patent/WO1999005724A1/fr

Links

Classifications

    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66439—Unipolar field-effect transistors with a one- or zero-dimensional channel, e.g. quantum wire FET, in-plane gate transistor [IPG], single electron transistor [SET], striped channel transistor, Coulomb blockade transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7888—Transistors programmable by two single electrons

Definitions

  • This invention relates generally to a data storage device, and more specifically to a
  • a data storage device capable of representing a bit of information (i.e., a logic '0' or a logic ' 1')
  • a widely-used semiconductor memory is the "floating gate” memory.
  • a floating gate is the "floating gate" memory.
  • memory has a floating gate interposed between a channel and a control gate.
  • the information stored in a floating gate memory can be determined because differing
  • relatively low threshold voltage e.g., no excess charges on the floating gate
  • a relatively high threshold voltage e.g., a plurality of charges
  • MOS memory cells have been fabricated which are capable of storing and
  • SEMM Single Electron MOS Memory
  • nanofabrication i.e., the fabrication of structures approaching the size of a nanometer
  • the present invention provides a Single Electron MOS Memory (SEMM) capable of
  • the SEMM comprises a source-to-drain path
  • a single floating gate for storing at least one charge carrier, the floating
  • the SEMM comprises a semiconductor
  • source-to-drain path which includes a channel region; a single floating gate disposed over the
  • floating gate having dimensions less than 10 nanometers (nm) by 10 nanometers by 10
  • the SEMM comprises a source-to-drain
  • path including a channel region having a width of less than 70 nanometers; a single floating
  • the floating gate having dimensions less than 10 nanometers by 10
  • the SEMM comprises a source-to-drain
  • the path including a channel region between a source and a drain, the channel region being a
  • the channel region having a length from the source to the drain and also
  • a floating gate for storing at least one charge carrier, the floating gate being
  • the floating gate having a width, wherein the width of the floating gate is self-
  • the SEMM comprises a source-to-drain
  • the path including a channel region between a source and a drain, the channel region being
  • a floating gate for storing at least one charge carrier
  • floating gate being disposed over the channel region and isolated from the channel region by
  • a first gate dielectric layer the floating gate having lateral dimensions defined by lithography
  • control gate disposed over the floating gate and isolated from the floating gate by a
  • the first gate dielectric layer to define a floating gate; oxidizing the floating gate to reduce its
  • first gate dielectric layer to define the floating gate
  • the channel region to reduce their dimensions such that the resulting dimension of the floating gate is less than 10 nanometers by 10 nanometers by 10 nanometers, and such that the
  • channel region has a width which is less than the Debye screening length of a single charge
  • substrate comprised of a buried dielectric layer with an overlying crystalline semiconductor
  • a first gate dielectric layer comprises forming a first gate dielectric layer on the crystalline semiconductor layer
  • a method for fabricating a SEMM is
  • the SEMM includes a source, a drain, a channel region having a length from the
  • a method for fabricating a SEMM is
  • the SEMM includes a source, a drain, a channel region having a width between
  • a floating gate having a width and disposed over the channel region
  • the floating gate capable of storing a single charge carrier, and a control gate disposed over
  • the fabrication method comprises the steps of forming a first gate
  • lateral dimensions of the floating gate are defined by lithography; forming a
  • the SEMM of the invention solves the problems encountered with previous SEMM
  • the charging process is self-limited.
  • Figure 1 shows a top-down view of the basic structure of a SEMM according to the
  • Figure 2 shows a cross-sectional view of the structure of Figure 1 along a source-to-
  • Figure 3 shows an isometric view of a crystalline silicon substrate, a buried oxide
  • Figure 4 shows a cross-sectional view of the structure of Figure 3.
  • Figure 5 shows an isometric view of the structure of Figure 3 after the source-to-drain
  • Figure 6 shows a cross-sectional view of the structure of Figure 5.
  • Figure 7 shows an isometric view of the structure of Figure 5 after the first poly layer
  • Figure 8 shows a cross-sectional view of the structure of Figure 7 after the formation
  • Figure 9 shows an isometric view of the structure of Figure 8 after the deposition of a
  • Figure 10 shows a cross-sectional view of the structure of Figure 9.
  • FIG 11 shows the I-V characteristics of the SEMM of Figure 1 after the application
  • Figure 12 shows the relationship between threshold voltage (V j ) and charging voltage
  • Figure 13 shows the relationship between threshold voltage (V,) and duration of
  • Figure 14 shows an energy band diagram for the SEMM of Figure 1 showing charging
  • Figure 15 shows an energy band diagram for the SEMM of Figure 1 after a single
  • Figure 16 shows a cross-sectional view of the SEMM of Figure 1 and shows the
  • FIGS 1 and 2 show the disclosed inventive SEMM 10.
  • the SEMM is comprised of:
  • a crystalline silicon substrate 12 a buried oxide layer 14; a source-to-drain path 16 including
  • a source 18, a drain 20, and a channel region 22 a gate oxide 24; a nanoscale floating gate or
  • the SEMM's channel width 32 is narrower than the Debye screening length of a
  • the floating gate 26 is sufficient to screen the entire channel (i.e., the full channel width 32)
  • the small floating gate 26 significantly increases the quantum energy of the electron
  • V charge the threshold voltage (V t )
  • the device's threshold voltage is determined by the section where the
  • floating gate 26 is located over the channel region 22.
  • the SEMM 10 can be fabricated using a silicon-on-insulator or SIMOX wafer 11
  • the buried oxide layer 14 which comprises crystalline silicon 12 and a buried oxide layer 14.
  • the buried oxide layer 14 comprises crystalline silicon 12 and a buried oxide layer 14.
  • the buried oxide layer 14 can be about 23 microns thick, although this thickness is not
  • a suitable wafer 11 pre-processed as described above can be purchased from IBIS,
  • the surface layer 13 should be lightly doped
  • the surface layer 13 will eventually be etched to
  • SIMOX wafer 11 the use of a commercially available SIMOX wafer 11 is preferred, other Silicon on Insulator (SOI) technologies (such as Silicon on Sapphire (SOS) or mechanical bonding of crystalline
  • SOI Silicon on Insulator
  • SOS Silicon on Sapphire
  • silicon to a insulting substrate are also suitable.
  • the gate oxide 24 is formed. For reasons
  • the gate oxide very thin, on the order of about 1
  • polysilicon or "poly"
  • layer 25 is preferably deposited using a Low-Pressure-Chemical-Vapor-Deposition (LPCVD)
  • the resulting structure is patterned and etched to form the source-to-drain path
  • EBL Beam Lithography
  • PMMA polymethymethacrylate
  • the resulting structure is then baked for 12 hours at 165 degrees Celsius to harden the PMMA resist.
  • the PMMA resist is then exposed by an
  • a suitable EBL system consists of a modified JEOL-840A Scanning Electron
  • Such a system is capable of producing a
  • this EBL system is used to pattern the source-to-
  • drain path 16 to leave a line width of about 25 nanometers of resist in the channel region 22
  • nanoimprint technology can also be used to pattern
  • This technique involves making a mold containing the desired
  • etchant is used to etch the resist to expose the regions underneath the resist that that were
  • oxides i.e., the gate oxide
  • the process can also be used to remove the very thin layer of gate oxide 24.
  • the etching can also be used to remove the very thin layer of gate oxide 24.
  • the etching process as disclosed will etch silicon (i.e., the first poly layer 25
  • the PMMA resist can be removed by first soaking the resulting structure in warm
  • the floating gate 26 (to be formed from the first poly layer 25) and the width 32 channel
  • the floating gate 26 is formed from the remaining first poly layer 25. This can be
  • thermal oxide 27 about 12 minutes at 900 degrees Celsius, atmospheric pressure, to form thermal oxide 27.
  • control gate 26 comprises a portion of the control gate oxide 28 (to be described in more detail later).
  • the oxidation step should consume about 9 nanometers from each of the exposed surfaces of
  • oxide 27 on the top and sides of the floating gate will be about 18 nanometers thick.
  • these parameters can be modified if necessary. For example, if longer
  • nitrogen can be added to the oxygen ambient to retard oxidation.
  • an oxide 29 is deposited on the resulting structure to a thickness of 22
  • control gate oxide 28 which is about 40 nanometers thick.
  • the thickness of the second poly layer 31 is not critical and can be, for example, 100 to
  • the second poly layer 31 is deposited using the same
  • the second poly layer 31 is then patterned and
  • control gate 30 is etched to form the control gate 30. Because the lateral dimensions of control gate 26 can be
  • optical lithography processes are easily capable of patterning resist line widths of less than a
  • the second poly layer 31 can be etched using the poly etch recipe disclosed above, with the etch time
  • control gate will ultimately define the extent of the channel region 22 of the SEMM device.
  • control gate 30 is not critical, but is preferably made to run over the
  • the resulting structure is ion implanted with arsenic (an N-type dopant) to dope
  • control gate 30 has a two-fold purpose; first, it dopes the control gate 30 to render it sufficiently conductive
  • source-to-drain path 16 in those regions not covered by the control gate 30 to form source 18
  • oxide 24 will not appreciably affect the implantation of the exposed portions of the source-to-
  • a conductive layer (preferably aluminum) is sputtered onto the surface of
  • the conductive layer is
  • the metal can be patterned and
  • a suitable passivating layer (such as an oxide or nitride) can be deposited over the
  • the device e.g., from bonding wires or probe tips.
  • a positive voltage pulse i.e., a charging voltage
  • the I-V characteristics of the SEMM 10 were measured by monitoring the source-to-drain current (I ds ) flowing through the source-
  • V cg control gate voltage
  • the I-V characteristics reveal the threshold voltage (V t ) of the device, defined as the
  • V cg value at which I ds 100 pA.
  • a simple switching circuit was used to allow I-V
  • V char2e charging voltages (V char2e ) of 2V, 7V, 10V and 14V. Note that as V charge is increased, the V t
  • V t shift is self-limited and is independent of the
  • Figure 1 1 shows that the disclosed SEMM 10 has a good subthreshold
  • V charge e.g., 5 to 8 Volts
  • an electron in the channel region 22 can tunnel through the gate
  • Figure 14 shows the energy band diagram of the SEMM 10 when the floating gate 26 is being charged with an electron.
  • Figure 15 shows how the stored
  • V charge e.g. 9-12V
  • nanometer by 7 nanometer floating gate with 40 nanometers of control oxide is about 4.4*10
  • channel region 22 is only partially screened by the floating gate 26.
  • control gate oxide 28 thickness 40 nanometers and an area of 70 x 26 x 2 nanometers
  • the threshold voltage can be adjusted to be
  • floating gate 26 become quantized and separate. By further reducing the size of the floating gate 26
  • the floating gate 26 is assumed to be a substantially flat "disk" of radius r, solutions to the
  • the quantum energy level spacing within the floating gate 26 must be significantly higher than the thermal energy
  • level spacing in the disclosed floating gate 26 is about 80 meV, or about 3 times the thermal
  • floating gate 26 be able to modulate the conductivity of the channel such that a resolvable
  • the channel width 32 must generally be smaller than the
  • L D for the disclosed SEMM 10 is estimated to be about 70 nanometers
  • channel width 32 of the disclosed SEMM 10 after oxidation is about 10 nanometers, a single electron can effectively modulate the channel conductivity, even when the control gate 30 is
  • the stored electron modulate the channel by causing the positive
  • a SEMM according to the invention has been shown useful for storing and detecting
  • the SEMM is orders of magnitude
  • gate oxide 24 and control gate oxide 28 could also be formed of
  • silicon nitride silicon nitride, tantalum dioxide or other suitable dielectric materials, or combinations
  • the floating gate could be formed of other suitably conductive materials, such as

Abstract

L'invention concerne une mémoire MOS à un seul électron (SEMM), dans laquelle un bit d'information est représenté par un seul électron stocké à température ambiante. Cette mémoire SEMM se présente sous la forme d'un transistor MOS en silicium à grille flottante, avec une largeur du canal (environ 10 nanomètres) inférieure à la distance de Debye d'un seul électron stocké sur la grille flottante (26). Ce transistor présente également un point en silicium polycristallin situé sur une échelle variant entre 7 nanomètres et 2 nanomètres, ladite grille flottante étant placée entre le canal et la grille de commande (30). Un électron stocké sur cette grille flottante (26) peut masquer le canal entier depuis le potentiel de ladite grille de commande, et créer: i) un décalage discret de la tension de seuil; ii) un rapport en escalier entre la tension de charge et ce décalage; et iii) un procédé de répartition de charge autolimitatif. La structure et la conception de cette mémoire SEMM sont particulièrement adaptée à la fabrication de circuits LSI.
PCT/US1997/013348 1997-07-25 1997-07-25 Memoire semm a grille flottante WO1999005724A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
AU38189/97A AU3818997A (en) 1997-07-25 1997-07-25 Single-electron floating-gate mos memory
PCT/US1997/013348 WO1999005724A1 (fr) 1997-07-25 1997-07-25 Memoire semm a grille flottante

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1997/013348 WO1999005724A1 (fr) 1997-07-25 1997-07-25 Memoire semm a grille flottante

Publications (1)

Publication Number Publication Date
WO1999005724A1 true WO1999005724A1 (fr) 1999-02-04

Family

ID=22261359

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1997/013348 WO1999005724A1 (fr) 1997-07-25 1997-07-25 Memoire semm a grille flottante

Country Status (2)

Country Link
AU (1) AU3818997A (fr)
WO (1) WO1999005724A1 (fr)

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2797349A1 (fr) * 1999-08-04 2001-02-09 X Ion Composant a elements mono-electron et dispositif quantique, ainsi que procede industriel de realisation et reacteur multichambres de mise en oeuvre
JP2001308289A (ja) * 2000-04-15 2001-11-02 Samsung Electronics Co Ltd 二重量子点を応用した単一電子多値メモリ及びその駆動方法
KR100343210B1 (ko) * 1999-08-11 2002-07-10 윤종용 단일 전자 충전 ｍｎｏｓ계 메모리 및 그 구동 방법
US6951173B1 (en) 2003-05-14 2005-10-04 Molecular Imprints, Inc. Assembly and method for transferring imprint lithography templates
US6982783B2 (en) 2002-11-13 2006-01-03 Molecular Imprints, Inc. Chucking system for modulating shapes of substrates
US7019835B2 (en) 2004-02-19 2006-03-28 Molecular Imprints, Inc. Method and system to measure characteristics of a film disposed on a substrate
US7041604B2 (en) 2004-09-21 2006-05-09 Molecular Imprints, Inc. Method of patterning surfaces while providing greater control of recess anisotropy
US7105452B2 (en) 2004-08-13 2006-09-12 Molecular Imprints, Inc. Method of planarizing a semiconductor substrate with an etching chemistry
US7186483B2 (en) 2000-07-16 2007-03-06 Board Of Regents, The University Of Texas System Method of determining alignment of a template and a substrate having a liquid disposed therebetween
US7241395B2 (en) 2004-09-21 2007-07-10 Molecular Imprints, Inc. Reverse tone patterning on surfaces having planarity perturbations
US7244386B2 (en) 2004-09-27 2007-07-17 Molecular Imprints, Inc. Method of compensating for a volumetric shrinkage of a material disposed upon a substrate to form a substantially planar structure therefrom
US7252715B2 (en) 2002-07-09 2007-08-07 Molecular Imprints, Inc. System for dispensing liquids
US7252777B2 (en) 2004-09-21 2007-08-07 Molecular Imprints, Inc. Method of forming an in-situ recessed structure
US7261830B2 (en) 2003-10-16 2007-08-28 Molecular Imprints, Inc. Applying imprinting material to substrates employing electromagnetic fields
US7270533B2 (en) 2003-10-02 2007-09-18 University Of Texas System, Board Of Regents System for creating a turbulent flow of fluid between a mold and a substrate
US7282550B2 (en) 2004-08-16 2007-10-16 Molecular Imprints, Inc. Composition to provide a layer with uniform etch characteristics
US7365103B2 (en) 2002-12-12 2008-04-29 Board Of Regents, The University Of Texas System Compositions for dark-field polymerization and method of using the same for imprint lithography processes
DE102007016302A1 (de) * 2007-03-26 2008-10-02 Qimonda Ag Verfahren zum Herstellen eines Nanodraht-Transistors, Nanodraht-Transistor-Struktur und Nanodraht-Transistor-Feld
US7504268B2 (en) 2004-05-28 2009-03-17 Board Of Regents, The University Of Texas System Adaptive shape substrate support method
US8850980B2 (en) 2006-04-03 2014-10-07 Canon Nanotechnologies, Inc. Tessellated patterns in imprint lithography
US9223202B2 (en) 2000-07-17 2015-12-29 Board Of Regents, The University Of Texas System Method of automatic fluid dispensing for imprint lithography processes

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4272774A (en) * 1979-07-19 1981-06-09 National Semiconductor Corporation Self-aligned floating gate memory cell and method of manufacture
US5446299A (en) * 1994-04-29 1995-08-29 International Business Machines Corporation Semiconductor random access memory cell on silicon-on-insulator with dual control gates
US5493140A (en) * 1993-07-05 1996-02-20 Sharp Kabushiki Kaisha Nonvolatile memory cell and method of producing the same
US5508543A (en) * 1994-04-29 1996-04-16 International Business Machines Corporation Low voltage memory
US5581102A (en) * 1993-02-05 1996-12-03 Semiconductor Energy Laboratory Co., Ltd. Transistor and method for manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4272774A (en) * 1979-07-19 1981-06-09 National Semiconductor Corporation Self-aligned floating gate memory cell and method of manufacture
US5581102A (en) * 1993-02-05 1996-12-03 Semiconductor Energy Laboratory Co., Ltd. Transistor and method for manufacturing the same
US5493140A (en) * 1993-07-05 1996-02-20 Sharp Kabushiki Kaisha Nonvolatile memory cell and method of producing the same
US5446299A (en) * 1994-04-29 1995-08-29 International Business Machines Corporation Semiconductor random access memory cell on silicon-on-insulator with dual control gates
US5508543A (en) * 1994-04-29 1996-04-16 International Business Machines Corporation Low voltage memory

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
LIU et al., "Self-Limiting Oxidation for Fabricating Sub-5nm Silicon Nanowires", APP. PHYS. LETTERS, 14 March 1994, Vol. 64, No. 11, pages 1383-1385. *
TIWARI et al., "A Silicon Nanocrystals Based Memory", APP. PHYS. LETTERS, 04 March 1996, Vol. 68, No. 10, pages 1377-1379. *
YANO et al., "Room-Temperature Single-Electron Memory", IEEE TRANS. ELEC. DEVICES, September 1994, Vol. 41, No. 9, pages 1628-1638. *

Cited By (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001011689A1 (fr) * 1999-08-04 2001-02-15 X-Ion Composant a elements mono-electron et dispositif quantique, ainsi que procede industriel de realisation et reacteur multichambres de mise en oeuvre
FR2797349A1 (fr) * 1999-08-04 2001-02-09 X Ion Composant a elements mono-electron et dispositif quantique, ainsi que procede industriel de realisation et reacteur multichambres de mise en oeuvre
KR100343210B1 (ko) * 1999-08-11 2002-07-10 윤종용 단일 전자 충전 ｍｎｏｓ계 메모리 및 그 구동 방법
JP2001308289A (ja) * 2000-04-15 2001-11-02 Samsung Electronics Co Ltd 二重量子点を応用した単一電子多値メモリ及びその駆動方法
US6597036B1 (en) 2000-04-15 2003-07-22 Samsung Electronics Co., Ltd. Multi-value single electron memory using double-quantum dot and driving method thereof
US7186483B2 (en) 2000-07-16 2007-03-06 Board Of Regents, The University Of Texas System Method of determining alignment of a template and a substrate having a liquid disposed therebetween
US9223202B2 (en) 2000-07-17 2015-12-29 Board Of Regents, The University Of Texas System Method of automatic fluid dispensing for imprint lithography processes
US7252715B2 (en) 2002-07-09 2007-08-07 Molecular Imprints, Inc. System for dispensing liquids
US6982783B2 (en) 2002-11-13 2006-01-03 Molecular Imprints, Inc. Chucking system for modulating shapes of substrates
US7365103B2 (en) 2002-12-12 2008-04-29 Board Of Regents, The University Of Texas System Compositions for dark-field polymerization and method of using the same for imprint lithography processes
US6951173B1 (en) 2003-05-14 2005-10-04 Molecular Imprints, Inc. Assembly and method for transferring imprint lithography templates
US7531025B2 (en) 2003-10-02 2009-05-12 Molecular Imprints, Inc. Method of creating a turbulent flow of fluid between a mold and a substrate
US7270533B2 (en) 2003-10-02 2007-09-18 University Of Texas System, Board Of Regents System for creating a turbulent flow of fluid between a mold and a substrate
US7261830B2 (en) 2003-10-16 2007-08-28 Molecular Imprints, Inc. Applying imprinting material to substrates employing electromagnetic fields
US7019835B2 (en) 2004-02-19 2006-03-28 Molecular Imprints, Inc. Method and system to measure characteristics of a film disposed on a substrate
US7504268B2 (en) 2004-05-28 2009-03-17 Board Of Regents, The University Of Texas System Adaptive shape substrate support method
US7105452B2 (en) 2004-08-13 2006-09-12 Molecular Imprints, Inc. Method of planarizing a semiconductor substrate with an etching chemistry
US7282550B2 (en) 2004-08-16 2007-10-16 Molecular Imprints, Inc. Composition to provide a layer with uniform etch characteristics
US7041604B2 (en) 2004-09-21 2006-05-09 Molecular Imprints, Inc. Method of patterning surfaces while providing greater control of recess anisotropy
US7252777B2 (en) 2004-09-21 2007-08-07 Molecular Imprints, Inc. Method of forming an in-situ recessed structure
US7241395B2 (en) 2004-09-21 2007-07-10 Molecular Imprints, Inc. Reverse tone patterning on surfaces having planarity perturbations
US7244386B2 (en) 2004-09-27 2007-07-17 Molecular Imprints, Inc. Method of compensating for a volumetric shrinkage of a material disposed upon a substrate to form a substantially planar structure therefrom
US8850980B2 (en) 2006-04-03 2014-10-07 Canon Nanotechnologies, Inc. Tessellated patterns in imprint lithography
DE102007016302A1 (de) * 2007-03-26 2008-10-02 Qimonda Ag Verfahren zum Herstellen eines Nanodraht-Transistors, Nanodraht-Transistor-Struktur und Nanodraht-Transistor-Feld

Also Published As

Publication number Publication date
AU3818997A (en) 1999-02-16

Similar Documents

Publication Publication Date Title
US6069380A (en) Single-electron floating-gate MOS memory
WO1999005724A1 (fr) Memoire semm a grille flottante
EP1341184B1 (fr) Dispositif memoire utilisant des nanotubes de carbon et procédé pour son fabrication
US6211013B1 (en) Method for fabricating single electron transistor
KR100305038B1 (ko) 부유게이트의밀도와치수의제어성을개선할수있는반도체기억소자
KR100294691B1 (ko) 다중층양자점을이용한메모리소자및제조방법
US6690059B1 (en) Nanocrystal electron device
US6730567B2 (en) Dynamic memory based on single electron storage
Wu et al. Room-temperature Si single-electron memory fabricated by nanoimprint lithography
JP2002543596A (ja) 静電的に制御されるトンネリング・トランジスタ
Ranade et al. Molybdenum as a gate electrode for deep sub-micron CMOS technology
US20050142753A1 (en) Methods of forming silicon quantum dots and methods of fabricating semiconductor memory device using the same
KR100418182B1 (ko) 실리콘 단전자 기억 소자의 제작방법
US7525147B2 (en) Memory structure
Nakao Silicon single-electron memory using ultra-small floating gate
Nakajima et al. Si single-electron tunneling transistor with nanoscale floating dot stacked on a Coulomb island by self-aligned process
US6929983B2 (en) Method of forming a current controlling device
KR100468834B1 (ko) 산화공정을 이용한 단일전자 트랜지스터 및그 제조방법
Kim et al. Charge retention characteristics of SiGe quantum dot flash memories
Depas et al. Ultra-thin gate oxide yield and reliability
KR20100043342A (ko) 금속 실리사이드 입자를 구비하는 비휘발성 메모리 소자의 제조방법
KR101071520B1 (ko) 금속 실리사이드 입자를 구비하는 비휘발성 메모리 소자의 제조방법
Yamamoto et al. Sub-micron tungsten gate process compatible with silicon gate process
JPH06252417A (ja) 半導体装置およびその製造方法
Su et al. Novel tunneling dielectric prepared by oxidation of ultrathin rugged polysilicon for 5-V-only nonvolatile memories

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AU KR US

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
NENP Non-entry into the national phase

Ref country code: KR