WO1998055932A3 - Processor interfacing to memory mapped computing engine - Google Patents
Processor interfacing to memory mapped computing engine Download PDFInfo
- Publication number
- WO1998055932A3 WO1998055932A3 PCT/US1998/010549 US9810549W WO9855932A3 WO 1998055932 A3 WO1998055932 A3 WO 1998055932A3 US 9810549 W US9810549 W US 9810549W WO 9855932 A3 WO9855932 A3 WO 9855932A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- series
- memory
- mcc
- memory mapped
- start address
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units
- G06F9/3893—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
- G06F9/3895—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros
- G06F9/3897—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros with adaptable data path
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline, look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/42—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation
- H04N19/423—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation characterised by memory arrangements
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/60—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding
- H04N19/61—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using transform coding in combination with predictive coding
Abstract
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU76931/98A AU7693198A (en) | 1997-06-04 | 1998-05-22 | Processor interfacing to memory-centric computing engine |
EP98924857A EP0986787A2 (en) | 1997-06-04 | 1998-05-22 | Processor interfacing to memory mapped computing engine |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/869,148 US6691206B1 (en) | 1997-03-21 | 1997-06-04 | Processor interfacing to memory-centric computing engine |
US08/869,277 | 1997-06-04 | ||
US08/869,148 | 1997-06-04 | ||
US86927797A | 1997-06-21 | 1997-06-21 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1998055932A2 WO1998055932A2 (en) | 1998-12-10 |
WO1998055932A3 true WO1998055932A3 (en) | 1999-08-12 |
Family
ID=27128095
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/010549 WO1998055932A2 (en) | 1997-06-04 | 1998-05-22 | Processor interfacing to memory mapped computing engine |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0986787A2 (en) |
AU (1) | AU7693198A (en) |
WO (1) | WO1998055932A2 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10003006A1 (en) * | 2000-01-25 | 2001-07-26 | Bosch Gmbh Robert | Arrangement and method for signal processing and storage |
US6643800B1 (en) * | 2000-02-02 | 2003-11-04 | Hewlett-Packard Development Company, L.P. | Method and apparatus for testing microarchitectural features by using tests written in microcode |
WO2002093508A1 (en) * | 2001-05-16 | 2002-11-21 | Georges Chiche | Portable personal medical file system |
AU2003250575A1 (en) * | 2002-08-07 | 2004-02-25 | Mmagix Technology Limited | Apparatus, method and system for a synchronicity independent, resource delegating, power and instruction optimizing processor |
US20060176955A1 (en) * | 2005-02-07 | 2006-08-10 | Lu Paul Y | Method and system for video compression and decompression (codec) in a microprocessor |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0139254A2 (en) * | 1983-10-18 | 1985-05-02 | International Business Machines Corporation | Apparatus and method for direct memory to peripheral and peripheral to memory data transfer |
GB2155671A (en) * | 1982-02-19 | 1985-09-25 | Sony Corp | Digital signal processing systems |
US4862407A (en) * | 1987-10-05 | 1989-08-29 | Motorola, Inc. | Digital signal processing apparatus |
EP0498107A2 (en) * | 1991-02-07 | 1992-08-12 | Mitsubishi Denki Kabushiki Kaisha | A semiconductor memory device with an internal voltage generating circuit |
US5230042A (en) * | 1987-09-25 | 1993-07-20 | Minolta Camera Kabushiki Kaisha | Digital image processing apparatus |
WO1994012929A1 (en) * | 1992-11-23 | 1994-06-09 | Seiko Epson Corporation | A microcode cache system and method |
US5396634A (en) * | 1992-09-30 | 1995-03-07 | Intel Corporation | Method and apparatus for increasing the decoding speed of a microprocessor |
DE4432217A1 (en) * | 1993-09-13 | 1995-03-16 | Mitsubishi Electric Corp | Clock-synchronous semiconductor memory device |
US5448715A (en) * | 1992-07-29 | 1995-09-05 | Hewlett-Packard Company | Dual clock domain interface between CPU and memory bus |
JPH0934783A (en) * | 1995-07-14 | 1997-02-07 | Mitsubishi Electric Corp | Semiconductor memory device |
-
1998
- 1998-05-22 AU AU76931/98A patent/AU7693198A/en not_active Abandoned
- 1998-05-22 EP EP98924857A patent/EP0986787A2/en not_active Withdrawn
- 1998-05-22 WO PCT/US1998/010549 patent/WO1998055932A2/en not_active Application Discontinuation
Patent Citations (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2155671A (en) * | 1982-02-19 | 1985-09-25 | Sony Corp | Digital signal processing systems |
EP0139254A2 (en) * | 1983-10-18 | 1985-05-02 | International Business Machines Corporation | Apparatus and method for direct memory to peripheral and peripheral to memory data transfer |
US5230042A (en) * | 1987-09-25 | 1993-07-20 | Minolta Camera Kabushiki Kaisha | Digital image processing apparatus |
US4862407A (en) * | 1987-10-05 | 1989-08-29 | Motorola, Inc. | Digital signal processing apparatus |
EP0498107A2 (en) * | 1991-02-07 | 1992-08-12 | Mitsubishi Denki Kabushiki Kaisha | A semiconductor memory device with an internal voltage generating circuit |
US5448715A (en) * | 1992-07-29 | 1995-09-05 | Hewlett-Packard Company | Dual clock domain interface between CPU and memory bus |
US5396634A (en) * | 1992-09-30 | 1995-03-07 | Intel Corporation | Method and apparatus for increasing the decoding speed of a microprocessor |
WO1994012929A1 (en) * | 1992-11-23 | 1994-06-09 | Seiko Epson Corporation | A microcode cache system and method |
DE4432217A1 (en) * | 1993-09-13 | 1995-03-16 | Mitsubishi Electric Corp | Clock-synchronous semiconductor memory device |
JPH0934783A (en) * | 1995-07-14 | 1997-02-07 | Mitsubishi Electric Corp | Semiconductor memory device |
US5726947A (en) * | 1995-07-14 | 1998-03-10 | Mitsubishi Denki Kabushiki Kaisha | Synchronous semiconductor memory device suitable for graphic data processing |
Non-Patent Citations (3)
Title |
---|
A. C. DAVIES ET AL.: "Interfacing a Hardware Multiplier to a General-purpose Microprocessor", MICROPROCESSORS AND MICROSYSTEMS., vol. 1, no. 7, October 1977 (1977-10-01), LONDON GB, pages 425 - 431, XP000212024 * |
ERTEM M C: "A RECONFIGURABLE CO-PROCESSOR FOR MICROPROCESSOR SYSTEMS", PROCEEDINGS OF THE SOUTHEAST CONFERENCE, TAMPA, APRIL 5 - 8, 1987, vol. 1, 5 April 1987 (1987-04-05), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 225 - 228, XP000212298 * |
PATENT ABSTRACTS OF JAPAN vol. 097, no. 006 30 June 1997 (1997-06-30) * |
Also Published As
Publication number | Publication date |
---|---|
EP0986787A2 (en) | 2000-03-22 |
WO1998055932A2 (en) | 1998-12-10 |
AU7693198A (en) | 1998-12-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5569855A (en) | Data processing system | |
WO2003010657A3 (en) | Method and system for encoding instructions for a vliw that reduces instruction memory requirements | |
TW345649B (en) | Method for executing different sets of instructions that cause a processor to perform different data type operations | |
JPS56149646A (en) | Operation controller | |
KR920001319A (en) | Processor and treatment method | |
EP0911724A3 (en) | Process and method for utilizing register file resources | |
RU96118510A (en) | DISPLAYING USING MULTI-SETS OF TEAMS | |
MY116707A (en) | Coprocessor data access control | |
CA2152041A1 (en) | An Apparatus for Executing a Plurality of Program Segments Having Different Object Code Types in a Single Program or Processor Environment | |
MY127147A (en) | Restarting translated instructions | |
GB2345564A (en) | Method and apparatus for providing execution of system management mode services in virtual mode | |
MY127357A (en) | A data processing apparatus and method for saving return state | |
WO1998055932A3 (en) | Processor interfacing to memory mapped computing engine | |
KR100463642B1 (en) | Apparatus for accelerating multimedia processing by using the coprocessor | |
AU2001285072A1 (en) | Method and apparatus for instruction set architecture to perform primary and shadow digital signal processing sub-instructions simultaneously | |
KR950033813A (en) | Data processing device | |
JPH0523447B2 (en) | ||
JPH02122343A (en) | Digital signal processor | |
JPS57756A (en) | Data processor | |
WO2003098431A3 (en) | Method and apparatus for decoding instruction sequences | |
WO2005033873A3 (en) | Method and system for processing a sequence of instructions | |
KR970014285A (en) | Video data processing system for spatial light modulator | |
KR970705077A (en) | Apparatus and Method for Executing Pop Instructions | |
JPH0683624A (en) | Processor and its control method | |
JPS62133533A (en) | Switching system for os in electronic computer system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A2 Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM GW HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD TG |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1998924857 Country of ref document: EP |
|
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
AK | Designated states |
Kind code of ref document: A3 Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GE GH GM GW HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW |
|
AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN ML MR NE SN TD TG |
|
WWW | Wipo information: withdrawn in national office |
Ref document number: 1998924857 Country of ref document: EP |
|
NENP | Non-entry into the national phase |
Ref country code: JP Ref document number: 1999502520 Format of ref document f/p: F |
|
WWP | Wipo information: published in national office |
Ref document number: 1998924857 Country of ref document: EP |
|
REG | Reference to national code |
Ref country code: DE Ref legal event code: 8642 |
|
NENP | Non-entry into the national phase |
Ref country code: CA |