WO1998048572A1 - Image pick-up method and apparatus using the image pick-up method - Google Patents
Image pick-up method and apparatus using the image pick-up method Download PDFInfo
- Publication number
- WO1998048572A1 WO1998048572A1 PCT/JP1998/001801 JP9801801W WO9848572A1 WO 1998048572 A1 WO1998048572 A1 WO 1998048572A1 JP 9801801 W JP9801801 W JP 9801801W WO 9848572 A1 WO9848572 A1 WO 9848572A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- image
- image data
- memory
- data
- circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
- H04N5/772—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera the recording apparatus and the television camera being placed in the same enclosure
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/76—Television signal recording
- H04N5/765—Interface circuits between an apparatus for recording and another apparatus
- H04N5/77—Interface circuits between an apparatus for recording and another apparatus between a recording apparatus and a television camera
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N9/00—Details of colour television systems
- H04N9/79—Processing of colour television signals in connection with recording
- H04N9/87—Regeneration of colour television signals
- H04N9/877—Regeneration of colour television signals by assembling picture element blocks in an intermediate memory
Definitions
- the present invention relates to an image pick-up apparatus, image pick-up method and display method, for picking up an image of an object and effecting display and recording based on image data.
- the structure and operation of a conventional image pick-up apparatus are so constructed as to enable a selection of a recording mode for picking up and recording the image of an object and a reproducing mode for reproducing and displaying image picked-up data already recorded.
- image data picked up from a CCD charge coupled device
- the CCD generates a photoelectric conversion output as one corresponding image for a predetermined cycle.
- This output is sampled/held by a sampling/holding circuit and converted by an A/D converter to digital data.
- the digital signal is converted by a YUV signal processing circuit to a multiplexed signal (signal containing at least a luminance signal and color difference, hereinafter referred to YUV data) containing a digital luminance and color difference and it is output to a DMA (Direct Memory Access) controller.
- the DMA controller allows the YUV data which is input to be written to its interior buffer and the data to be DMA-transferred to a DRAM (Dynamic Random Access Memory) via a DRAM I/F (Dynamic Random Access Memory Interface) .
- a CPU After the YUV data has been DMA-transferred to the DRAM, a CPU enables the YUV data to be read out from the DRAM via the DRAM I/F and the data to be written to a VRAM (Video Random Access Memory) via a VRAM controller.
- VRAM Video Random Access Memory
- a shutter key is operated in a timing for the user to record/preserve it, generating a trigger.
- CPU Central Processing Unit
- CPU stops a path from the CCD to the DRAM, effecting a shift to a recording/reserving state.
- the CPU enables YUV data of one frame written to the DRAM to be read out via the DRAM I/F and the data to be written to the compandor circuit.
- the CPU enables the code data which is compressed in the compandor circuit to be read from the compandor circuit and the data to be written to a flash memory comprised of a nonvolatile memory.
- the CPU With the YUV data of one frame compress-processed and full compressed data written to the flash memory, the CPU enables the restarting of data transfer from the CCD to the DRAM.
- the image data stored in the flash memory is displayed on the display device in the following sequence.
- the CPU stops the path from the CCD to the DRAM and enables the code data of a specific one frame to be read out from the flash memory in accordance with the depression of an image select key, etc., by the user and the data to be written to the compandor circuit. And the CPU enables expand-processing to be effected by the compandor circuit and the YUV data of one frame to be developed into the VRAM through the VRAM controller. Then a video encoder creates a video signal from the YUV data of one frame developed into the VRAM and it is displayed on the display device.
- the YUV data of one frame is developed into the DRAM at the recording and reproducing modes as set out above and, at each completion of the development of the YUV data into the DRAM, the YUV data is transferred from the DRAM to the VRAM by the video encoder and it is displayed. That is, since the display of the image is effected while using the DRAM as a memory for operation and the VRAM as a memory for display, these separate memories, for operation and for display, exist, thus leading to an increase in cost and a larger increase in the size of a circuit.
- both the memories exist separately, at each updating of the image information obtained from the CCD in the recording mode and at each expansion of the compressed YUV data in the reproducing mode the YUV data developed into the DRAM has to be transferred to the VRAM, so that there unavoidably occurs a dissipation power loss.
- a preferred aspect of the present invention comprises : image pick-up means for picking up an image of an object and for generating a corresponding signal; generating means for generating image data of the object image based on the signal generated from the image pickup means; recording means for recording, in response to a picking-up operation, the image data generated from the generating means ; display control means for displaying the object image based on the image data generated from the generating means and for displaying, in response to a reproducing operation, an image based on the image data stored in the recording means; memory means for operation; and transfer means for transferring the image data from the generation means and recording means, in predetermined format, to the memory means while transferring the image data, in the predetermined format, from the memory means to the display control means .
- an image stored in the preservation memory can be displayed on the display screen of the display device .
- Another preferred aspect of the present invention comprises : image pick-up means for picking up an image of an object and for generating image data corresponding to the object; a temporary storing memory for temporarily storing the image data from the image pick- up means ; display means for displaying the image data of the temporary storing memory; and transfer means for transferring the image data of the image pick-up means to the temporary storing memory and display means .
- Another preferred aspect of the present invention comprises : an image pick-up element for picking up image data; a temporary storing memory for temporarily storing the image data from the image pick-up element; a compressing circuit for compressing the image data stored in the temporary storing memory; a preservation memory for preserving the image data compressed by the compressing circuit; display means for displaying the image data stored in the temporary storing memory; and transferring means for transferring the image data in the temporary storing memory to the compressing circuit and display means .
- an image stored in the preservation memory can be displayed on the display screen of the display device without using a VRAM controller and VRAM in the conventional apparatus. Further, since it is possible to reduce the data transfer via the control means, so that there arises less load on the control means .
- Another preferred aspect of the present invention comprises : a preservation memory for preserving compressed image data; an expanding circuit for expanding the compressed image data of the preservation memory; a temporary storing memory for storing the image data expanded by the expanding circuit; display means for displaying data encoded by the video encoder; and transfer means for transferring the image data which is expanded by the expanding circuit to the temporary storing memory and display means .
- the image stored in the preservation memory can be displayed on the display screen of the display device without using the VRAM controller and VRAM in the conventional apparatus. Further, it is possible to reduce the data transfer via the control means, so that less load is exerted on the load.
- Another preferred aspect of the present invention comprises : picking up image data by an image pick-up element (SI); storing the image data from the image pick-up element in the temporary storing means (S2); and reading out the image data of the temporary storing memory while overlapping with the step, and sending the image data to display means (S3, S4).
- SI image pick-up element
- S2 temporary storing means
- S3 display means
- Another preferred aspect of the present invention comprises : picking up the image data by an image pick- up element (SI); storing the image data from the image pick-up element in a temporary storing memory (S2); compressing, by a compandor circuit, the image data stored in the temporary storing memory (S5); storing the image data which is compressed by the compandor circuit in a preservation memory (S6); and displaying, by displaying means , the image data which is stored in the temporary storing memory (S8) while overlapping with the step (S5) .
- Still another preferred aspect of the present invention comprises: sending compressed image data from a preservation memory to the expander circuit (S9); and sending the image data which is expanded by the expander circuit to a temporary preservation memory and sending the image data which is stored in the temporary preservation memory to display means (S10-S12).
- the image stored in the preservation memory can be displayed on the display screen of the display device without using the VRAM controller and VRAM in the conventional apparatus. Further, since the data transfer via the control means can be reduced, less load is exerted on the control means.
- FIG. 1A is a perspective view showing an outer appearance of a digital camera according to one aspect of the present invention
- FIG. IB is a perspective view showing the digital camera as viewed in a different direction
- FIG. 2 is a schematic block diagram of the digital camera
- FIG. 3 is a schematic block diagram showing a detail of a DMA controller and a state of connection to any other blocks ;
- FIG. 4 is a view showing an image map of YUV data corresponding to one frame
- FIGS. 5A to 5D each, show a relation between YUV data writing lines of a YUV signal processing circuit and YUV data reading lines of a video encoder;
- FIG. 6 is a view showing a relation between YUV data writing lines of a YUV signal processing circuit and YUV data reading lines of a video encoder in a second aspect of the present invention
- FIG. 7A is a view showing a moving path of data in a recording mode
- FIG. 7B is a view showing a moving path of data at a time of taking an image in a recording mode.
- FIG. 7C is a view showing a moving path of data in a reproducing mode. Best Mode of Carrying Out the Invention
- FIGS. 1A and IB are external views showing a digital camera according to an aspect of the present embodiment.
- the digital camera has a body 1 of a rectangular parallelepiped configuration with a display screen 2 on the back surface of the body 1, a lens 3 on a. front corner portion and a shutter key 4 on an upper face, any other keys, such as an image select key, being arranged.
- FIG. 2 is a block diagram of a digital camera according to the aspect of the present embodiment.
- a CCD 6 is arranged behind the lens 3 and driven by a timing generator 7 and vertical driver 8 to produce a photoelectric conversion output as one corresponding image at each given frequency.
- the photoelectric conversion output is subjected to sample/hold-processing by a sample/hold circuit 9 and it is converted by an A/D converter 10 to digital data.
- a multiplexed signal (signal containing at least a luminance signal and color difference signal, herein- after referred to as a YUV data) containing a digital luminance and color difference is output by a YUV signal processing circuit 11 to a DMA (Direct Memory Access) controller 12.
- DMA Direct Memory Access
- a compandor circuit 13 DRAM (Dynamic Random Access Memory) 14 and video encoder 15.
- a display device 16 having the display image screen 2.
- FIG. 3 is a block diagram showing the DMA controller 12 and a state of connection between the DMA controller 12 and other blocks.
- the YUV data output of the YUV signal processing circuit 11 is written into a first FIFO (First in First Out) 20 and, by a DMA controller circuit 21, DMA-transferred to the DRAM 14 through a DRAM I/F 22. Further, through a DMA transfer from the DRAM 14 via a DRAM I/F 22 to a video encoder 15, the DMA control circuit 21 allows the YUV data to be written into a second FIFO 23 and the YUV data to be output in response to a read-out control signal of the video encoder 15.
- FIFO First in First Out
- the DMA control circuit 21 extracts a 8x8 basic block of the YUV data through the DRAM I/F 22 from the DRAM 14 and transfers the block through the DMA transfer to a third FIFO 24. And the DMA control circuit 21 outputs the YUV data from the third FIFO 24 to a compandor circuit 13 in accordance with a read-out control signal of the compandor circuit 13.
- the image data obtained from the CCD is made to correspond to the YUV data of one frame output from the YUV signal processing circuit 11 at a given frequency (SI).
- the data is written, in a periodic fashion, by the DMA transfer in the DRAM 14 via the DMA controller 12 (S2).
- the DMA controller 12 periodically reads out the YUV data which is developed from the YUV signal processing circuit 11 onto the DRAM 14 from the DRAM 14 in a way to correspond to the image map and the DMA controller 12 delivers the data to the video encoder 15 (S2-S3).
- the video encoder 15 In accordance with the periodic updating, on the DRAM 14, of the image information obtained by the CCD 6 the video encoder 15 generates a video signal based on the automatically updated information, so that it is possible to display a current image on a display screen 2 of the display device 16 without using the VRAM controller and VRAM provided on the conventional apparatus (S4) . By doing so, it is possible to make a cost lower and a circuit size smaller and to avoid a loss in dissipation power since there is no need for effecting data transfer to the VRAM.
- the CPU 17 allows a shift to an image recording/holding state and, at a completion of the transfer of a frame from the YUV signal processing circuit 11 to the DRAM 14, allows the DMA controller 12 to stop the obtainment of the YUV data. Simultaneously with this stopping, the compandor circuit 13 is started and the DMA controller 12 allows the YUV data of one frame to be DMA transferred from the DRAM 14 toward the compandor circuit 13 in an 8X8 basic block unit to correspond to the image map (S5) .
- the CPU 17 sequentially reads, from the compandor circuit 13, compressed data generated at the compandor circuit 13 and writes it to the flash memory 18 (S6).
- the data is moved as shown in FIG. 7C. That is, the YUV signal processing circuit 6 and its proceeding stage are set in a stopping state by the instruction of the CPU 17.
- the code data of a specific image is read out from the flash memory 18 and written to the compandor circuit 13 (S9).
- the data of the 8x8 basic block unit obtained by the expand-processing of the compandor 13 is DMA- transferred, by the DMA controller 12 under the instruction of the CPU 17, in a way to correspond to the image map to the DRAM 14 (S10).
- the DMA controller 12 effects the DMA-transfer to the video encoder 15 in a way to correspond to the image map and the image expanded thereby is displayed automatically on the display screen 2 of the display device 16 (S11-S12). Therefore, as in the same way as set out above, an image selected by the operation of the image select key which is stored in the flash memory 18 can be displayed on the display screen 2 of the display device 16 without using the VRAM controller and VRAM in the prior art apparatus . It is to be noted that other than the data readout from the flash memory 18 and data writing to the compandor circuit 13 is done by the DMA controller, etc., under the instruction of the CPU 17 and it is possible to effect a high-speed data movement because the data is not via the CPU 17.
- a periodic development area of the YUV data in the YUV signal processing circuit 11 onto the memory area and readout area of it onto the memory of the video encoder 15 becomes matched to the same area on the DRAM 14. Since, however, the frame development period of the YUV data in the YUV signal processing circuit and frame readout period of the YUV data in the video encoder 15 are not necessarily synchronized with each other, if both gain access to the same area in such a way, there are sometimes the cases where an image display on the display device 16 is degenerated depending upon their periodic relation as shown in FIGS. 5A to 5D.
- FIGS. 5A to 5C represent, on a time base, a YUV data writing line of the YUV signal processing circuit 11 and a YUV data reading line of the video encoder 15 in the case where the development area of the YUV data in the YUV signal processing circuit 11 and readout area of the YUV data of the video encoder 15 are the same.
- the line means a horizontal line of the image and the horizontal line of this image is indicated by the ordinate axis and the time is set on the abscissa.
- a dot- dash line shows the development of the YUV signal processing circuit 11 and a spacing between those adjacent dot-dash lines is a development period.
- the solid line corresponds to the readout of the first field of the video encoder 15 and the dotted line to the second field.
- the spacing between those adjacent solid lines and that between those adjacent dotted lines are the readout period of the video encoder 15.
- the occurrence of the crossings between the development lines and the readout lines means that there occurs a mixed state between pre- and post- updated images of the development frames at the field (1/2 frame) displayed on the display screen 2. If any moving object is imaged, then a displayed object image is displaced on the display screen 2.
- FIG. 6 shows the aspect of another embodiment of the present invention according to which any displace- ment on a displacement object image is eliminated by using two areas. That is, the relation of the development period of a YUV signal processing circuit 11 and the readout period of the field (1/2 frame) of the video encoder 15 is set to the development period > the readout period. Further, an area A and area B are provided at a DRAM 14 and, by a DMA controller circuit 21, the YUV signal processing circuit 11 performs an alternate development onto the areas A and B. At this time, the YUV signal processing circuit 11 allows an area control signal S which rises at a completion of a development onto the area A and falls at a completion of a development onto the area B to be generated at the DMA control circuit 21.
- the video encoder 15 effects a signal readout from the area B when the area control signal S is in a low-level state and a signal readout from the area A when the control signal S is in a high- level state. By doing so, no crossing occurs between the development and readout lines on the same area and it is possible to eliminate any displacement of a displayed object image in the display screen caused when a moving object image is taken.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019980710416A KR100302307B1 (en) | 1997-04-22 | 1998-04-20 | Image pickup method and apparatus using this method |
EP98914100A EP0920774A1 (en) | 1997-04-22 | 1998-04-20 | Image pick-up method and apparatus using the image pick-up method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP11876497 | 1997-04-22 | ||
JP9/118764 | 1997-04-22 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1998048572A1 true WO1998048572A1 (en) | 1998-10-29 |
Family
ID=14744492
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1998/001801 WO1998048572A1 (en) | 1997-04-22 | 1998-04-20 | Image pick-up method and apparatus using the image pick-up method |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0920774A1 (en) |
KR (1) | KR100302307B1 (en) |
TW (1) | TW449739B (en) |
WO (1) | WO1998048572A1 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1026891A2 (en) * | 1999-02-08 | 2000-08-09 | SANYO ELECTRIC Co., Ltd. | Motion image recording apparatus and digital camera |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005012764A (en) * | 2003-05-22 | 2005-01-13 | Casio Comput Co Ltd | Data communication apparatus, image transmitting method, and image transmitting program |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4262301A (en) * | 1978-03-30 | 1981-04-14 | Polaroid Corporation | Electronic imaging camera |
US5153730A (en) * | 1989-07-27 | 1992-10-06 | Olympus Optical Co., Ltd. | Electronic still camera having two recording stages for recording still-image signals |
US5463419A (en) * | 1993-06-11 | 1995-10-31 | Fuji Photo Film Co., Ltd. | Image signal processing device for thinning images |
-
1998
- 1998-04-20 EP EP98914100A patent/EP0920774A1/en not_active Withdrawn
- 1998-04-20 KR KR1019980710416A patent/KR100302307B1/en not_active IP Right Cessation
- 1998-04-20 WO PCT/JP1998/001801 patent/WO1998048572A1/en not_active Application Discontinuation
- 1998-04-21 TW TW087106070A patent/TW449739B/en not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4262301A (en) * | 1978-03-30 | 1981-04-14 | Polaroid Corporation | Electronic imaging camera |
US5153730A (en) * | 1989-07-27 | 1992-10-06 | Olympus Optical Co., Ltd. | Electronic still camera having two recording stages for recording still-image signals |
US5463419A (en) * | 1993-06-11 | 1995-10-31 | Fuji Photo Film Co., Ltd. | Image signal processing device for thinning images |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1026891A2 (en) * | 1999-02-08 | 2000-08-09 | SANYO ELECTRIC Co., Ltd. | Motion image recording apparatus and digital camera |
EP1026891A3 (en) * | 1999-02-08 | 2002-10-09 | SANYO ELECTRIC Co., Ltd. | Motion image recording apparatus and digital camera |
US6697568B1 (en) | 1999-02-08 | 2004-02-24 | Sanyo Electric Co., Ltd. | Motion image recording apparatus and digital camera |
Also Published As
Publication number | Publication date |
---|---|
EP0920774A1 (en) | 1999-06-09 |
KR20000016804A (en) | 2000-03-25 |
TW449739B (en) | 2001-08-11 |
KR100302307B1 (en) | 2001-11-22 |
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